KR20050116509A - Electro luminecence display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electroluminescent display device, comprising: a pixel portion for displaying an image in which a plurality of pixels are arranged in a plurality of rows and columns; A plurality of scan lines to be applied and a plurality of power supply lines to supply power to the plurality of pixels, wherein two adjacent pixels in one row of the plurality of pixels share one data line of the plurality of data lines and An electroluminescent display device connected to two different scan lines among scan lines is provided.

The pixel is positioned between the power supply line and the data line, thereby preventing short circuit failure between the power supply line and the data line.

In addition, since the two pixels use one data line or / and a power supply line in common, the number of wirings around the pixels of the electroluminescent display can be reduced.

Description

EL display {ELECTRO LUMINECENCE DISPLAY}

The present invention relates to an electroluminescent display and a driving method thereof. More particularly, the present invention relates to an electroluminescent display in which two adjacent pixels in a row share one data line.

Recently, various flat panel display devices having a smaller weight and volume than the cathode ray tube have been developed, and in particular, electroluminescent display devices having excellent luminous efficiency, brightness, viewing angle, and fast response speed have been attracting attention. The electroluminescent display is classified into an inorganic electroluminescent display and an organic electroluminescent display according to the material of the light emitting layer.

The pixel of the OLED display has a structure in which a light emitting layer, which is a thin film for emitting light, is positioned between a cathode electrode and an anode electrode, and excitons are generated by injecting electrons and holes into the light emitting layer to recombine them, and the excitons fall to low energy. It has a characteristic of emitting light.

1 is an equivalent circuit diagram of a plurality of pixels employed in an electroluminescent display according to the related art. Referring to FIG. 1, in the electroluminescent display, the scan lines S are arranged in the row direction, and the data lines D1, D2, D3, D4 and the power supply line Vdd are arranged in the column direction. A plurality of pixels is connected to the scan line S, the data lines D1, D2, D3, and D4 and the power supply line Vdd. The pixel includes a light emitting device (LED), a first transistor M1, a storage capacitor SC, and a second transistor M2.

In one pixel, the scan line S is connected to the gate electrode of the second transistor M2, and the source electrode of the second transistor M2 is connected to the data lines D1, D2, D3, and D4. The drain electrode of M2 is connected to the gate electrode of the first transistor M1.

In addition, the source electrode of the first transistor M1 is connected to the power supply line Vdd and the drain electrode of the first transistor M1 is connected to the anode electrode of the light emitting device. In addition, the storage capacitor SC is connected to the pixel power supply line Vdd and the gate electrode of the first transistor M1.

Due to this configuration, each pixel positioned in one row is turned on by the selection signal applied to the gate of the second transistor M2, and the data transistors D1, D2, and D3 are turned on. The data signal is applied to the gate electrode of the first transistor M1 through D4. In response to the data signal, current flows through the first transistor M1 to emit light, and emits red, green, and blue colors depending on the light emitting material of the light emitting device.

In addition, the storage capacitor SC is charged with a voltage corresponding to a difference between the voltage of the power supply line Vdd and the voltage input through the data line, and the predetermined time even when the input of the selection signal input through the scan line S is terminated. The voltage charged in the storage capacitor SC is applied between the gate electrode and the source electrode of the first transistor M1 so that a current flows through the light emitting device.

FIG. 2 is a transmissive plan view illustrating a layout of the electroluminescent display of FIG. 1. Referring to FIG. 2, a first transistor M1 and a second transistor M2 are formed on a transparent substrate, and the first of the storage capacitor SC is disposed between the first transistor M1 and the second transistor M2. An electrode is formed, and the first electrode of the storage capacitor SC is connected to the gate electrode of the first transistor M1 and the drain electrode of the second transistor M2. The drain electrode of the first transistor M1 and the anode electrode of the pixel are connected.

The scan line S is formed in the horizontal direction, the scan line S is connected to the gate electrode of the second transistor M2, and the data lines D1, D2, D3, D4 and the pixel power supply line Vdd are scan lines. It is formed to cross perpendicular to (S).

The second electrode of the storage capacitor SC is formed at a position opposite to the first electrode of the storage capacitor SC, and the second electrode is connected to the pixel power supply line Vdd and the source electrode of the first transistor M1. do.

 In the conventional EL display device, the voltage supply line and the data line are adjacent to each other between the pixel and the pixel. Therefore, a problem occurs in that the data line and the power supply line are shorted due to the adjoining of the data line applying the data signal to the pixel and the power supply line supplying power to the adjacent pixel. In addition, there is a problem that the wiring structure around the pixel becomes complicated.

Therefore, the present invention was created to solve the problems of the prior art, and an object of the present invention is to prevent the power supply line and the data line from adjoining so that the data line and the pixel power supply line do not short-circuit, and two pixels are connected to the power supply line. Alternatively, the present invention provides an electroluminescent display device in which the number of power supply lines and / or data lines is reduced by using the data lines in common, thereby simplifying the wiring structure around the pixel.

In order to achieve the above object, an electroluminescent display device according to the present invention comprises: a pixel portion in which a plurality of pixels are arranged in a plurality of rows and columns to display an image; A plurality of data lines for applying a data signal to the plurality of pixels; A plurality of scan lines for applying a selection signal to the plurality of pixels; And a plurality of power supply lines for supplying power to the plurality of pixels, wherein two adjacent pixels in one row of the plurality of pixels share one data line of the plurality of data lines and the plurality of scan lines Are connected to two different scanning lines, respectively.

Preferably, two power supply lines of the plurality of power supply lines are connected to the two adjacent pixels, respectively.

In addition, two pixels are connected to one power supply line of the plurality of power supply lines, and the two pixels are connected to two different data lines.

In addition, the two scanning lines connected to two adjacent pixels positioned in the one row are arranged adjacent to each other.

In addition, the two scanning lines connected to two adjacent pixels positioned in the one row are arranged at predetermined intervals.

The pixel may further include a switching transistor configured to apply a data signal applied to the data line to the first node in response to a selection signal applied to the scan line; A first capacitor connected to the first node and a second terminal connected to the second node, the first capacitor maintaining a constant voltage for a predetermined period of time; A gate is connected to the first node, a source is connected to the second node, and includes a driving transistor configured to allow a current to flow through the light emitting device in response to a voltage charged in the first capacitor, and the two adjacent pixels are adjacent to each other. It is connected to another scan line.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

3 is a configuration diagram showing the configuration of an embodiment of an electroluminescent display according to the present invention. Referring to FIG. 3, an electroluminescent display device according to an exemplary embodiment of the present invention includes a pixel driver 100 including a plurality of pixels, a scan driver 200 and a pixel driver for selecting a specific row of the pixel driver 100. It is composed of a data driver 300 for transmitting a data signal to the 100.

The pixel unit 100 is a means for displaying an image and includes a plurality of scan lines S1.1, S1.2, S2.1, and S2.2. ..... Sn-1.1, Sn-1.2, Sn.1, Sn.2) and the plurality of data lines D1, D2 ... Dk-1, Dk intersect the scan line S It consists of a plurality of pixels (not shown) which emit light according to the signal applied to the data line D. FIG. Each pixel includes a light emitting element and a circuit for driving the light emitting element.

The selection signal is applied to the pixels in one row by the first scan line SN.1 and the second scan line SN.2. In addition, two adjacent pixels in one row share one data line DK, and one of the two pixels is connected to the first scan line SN.1, and the other pixel is the second scan line. (SN.2). Therefore, if there are M pixels in one row, the total number k of data lines is M / 2. Where K is an integer between 1 and k and N represents an integer between 1 and n.

The scan driver 200 is a means for generating a selection signal for selecting a specific row of the pixel unit 100 and transmitting the generated selection signal to the scan line of the pixel unit 100.

The data driver 300 is a means connected to the data line of the pixel unit 100 to apply a data signal to the pixel, and applies the data signal to a plurality of pixels selected by the scan line.

4 is an equivalent circuit diagram of a plurality of pixels employed in an electroluminescent display according to the present invention. Referring to FIG. 4, in the electroluminescent display, the first scan line Sk.1 and the second scan line Sk.2 for applying the selection signal to the pixels located in the same row are arranged in the row direction and the column direction. The data line and the power supply line are arranged. The first scan line Sk.1 and the second scan line Sk.2 may be arranged adjacent to each other as shown in the drawing, or may be arranged at regular intervals. If the first scan line Sk.1 and the second scan line Sk.2 have a predetermined interval, the pixel is positioned therebetween. The scan line, the data line, and the power supply line are connected to the plurality of pixels. The pixel includes a light emitting device (LED), a first transistor M1, a storage capacitor SC, and a second transistor M2.

The first pixel 10, the second pixel 20, the third pixel 30, and the fourth pixel 40 are sequentially called from the left to the right, and each pixel includes the first light emitting element LED1 and the second. The light emitting device LED2, the third light emitting device LED3, and the fourth light emitting device LED4 are respectively included.

In the second pixel 20, the gate electrode of the second transistor M2 is connected to the first scan line Sk.1, and the third pixel 30 is connected to the second transistor M2 in the first scan line Sk.2. ) Is connected to the gate electrode. In addition, the second data line D2 is positioned between the second pixel 20 and the third pixel 30, and the second transistor M2 of the second pixel 20 and the second pixel of the third pixel 30 are disposed. The source electrode of the transistor M2 is connected to the second data line D2. Therefore, the second pixel 20 and the third pixel 30 share the second data line D2. In the second transistor M2 of the second pixel 20 and the third pixel 30, a drain electrode is connected to a lower electrode of the storage capacitor SC and a gate electrode of the first transistor M1.

The source electrode of the first transistor M1 in the second pixel 20 is connected to the power supply line Vdd and the drain electrode is connected to the anode electrode of the second light emitting device LED2. In this case, the first pixel 10 is connected to a power supply line different from the power supply line connected to the second pixel 20, and is connected to the drain electrode of each first transistor M1 to the anode electrode of each light emitting device. do.

In addition, the storage capacitor SC is connected to the pixel power supply line Vdd and the gate electrode of the first transistor M1.

Due to this configuration, when the selection signal is applied to the first scan line Sk. 1, the second pixel 20 is selected so that the data signal input through the data line D2 is the driving transistor of the second pixel 20. When the selection signal is applied to the gate electrode of M1 and the selection signal is applied to the second scan line Sk. 2, the third pixel 30 is selected and the data signal input through the data line D2 is transferred to the third pixel 30. Is applied to the gate electrode of the driving transistor M1.

The storage capacitor SC maintains a signal input to the gate electrode of the first transistor M1 for a predetermined time so that the light emitting device emits light during the time.

FIG. 5 is a perspective plan view based on the layout of the pixel represented in FIG. 4. Referring to FIG. 5, four adjacent pixels are referred to as a first pixel 10, a second pixel 20, a third pixel 30, and a fourth pixel 40 from left to right. On the upper portion of each pixel, a scanning line made up of the first scanning line Sk.1 and the second scanning line Sk.2 is formed adjacent to each other, and a predetermined interval in a direction perpendicular to the scanning lines Sk.1 and Sk.2 is formed. A plurality of data lines D1, D2, D3 and power supply lines Vdd are formed. In addition, the first pixel 10, the second pixel 20, the third pixel 30, and the fourth pixel 40 are respectively the first light emitting device LED1, the second light emitting device LED2, and the third light emitting device. The device LED3 and the fourth light emitting device LED4 are included.

The data lines D1, D2, and D3 are formed on the left side of the first pixel 10, between the second pixel 20 and the third pixel 30, and on the right side of the fourth pixel 40, and supply a power supply line. Vdd is formed on the right side of the first pixel 10, the left side of the second pixel 20, the right side of the third pixel 30, and the left side of the fourth pixel 40.

The second pixel 20 and the fourth pixel 40 have a connector C, so that the gate electrode of the second transistor M2 of the second pixel 20 and the fourth pixel 40 is second. Instead of being connected to the scan line Sk. 2, the contactor C is connected to the first scan line Sk. 1.

The first electrode of the storage capacitor SC is formed between the first transistor M1 and the second transistor M2, and the first electrode of the storage capacitor SC is connected to the gate electrode of the first transistor M1. And a drain electrode of the second transistor M2. In addition, the second electrode of the storage capacitor SC is formed to face the first electrode and is connected to the power supply line Vdd. The drain electrode of the first transistor M1 and the anode electrode of the light emitting device LED are connected to each other.

In this case, the first transistor M1, the second transistor M2, and the storage capacitor SC are positioned between the scan line including the first scan line Sk.1 and the second scan line Sk.2 and the light emitting device. An array of a plurality of pixels is formed side by side.

As described above, the adjacent second pixel 20 and the third pixel 30 share one data line, two power supply lines are adjacent to each other, and the power supply line and the data line maintain a constant distance. do.

6 illustrates a cross-sectional structure along the line VI-VI ′ of FIG. 5. 6 illustrates only the first transistor M1, the storage capacitor SC, and the light emitting device LED.

A buffer layer 401 made of an oxide film is formed on a transparent insulating substrate 400 such as glass, and an active layer 402 is formed on the buffer layer 401. As the active layer 402, polycrystalline silicon obtained by heat-treating amorphous silicon may be used.

A gate insulating layer 403 formed of an oxide film is formed on the active layer 402, and a metal layer such as aluminum is formed on the gate insulating layer 403 and patterned to form the gate electrode 407a and the lower electrode 407b. Form. In addition, a region under the gate electrode 407a of the active layer 402 corresponds to a channel, and regions on both sides of the channel doped with P-type impurities by ion implantation are the source electrode 402b and the drain electrode 402a. Corresponds to).

The interlayer insulating film 404 is deposited on the gate electrode 407a and the lower electrode 407b, and patterned to form a first contact hole 413 and a second contact hole on the source electrode 402b and the drain electrode 402a. 412 to be formed. The metal layer 405 is deposited on the interlayer insulating film 404 and patterned, and the metal layer 405 and the drain electrode 402a and the source are formed through the first contact hole 412 and the second contact hole 413. Contact with the electrode 402b.

In addition, the protective layer 406 is deposited on the metal layer 405 and patterned to form a third contact hole 414 in the protective layer, and the anode electrode 408 is deposited on the protective layer 406 so that the anode electrode 408 is formed. The third contact hole 414 and the second contact hole 412 are electrically connected to the drain electrode 402a.

Then, the planarization film 409 formed of an insulating film is deposited and patterned thereon to form an opening, the light emitting material 410 is coated on the opening, and the cathode electrode 411 is formed on the entire surface including the light emitting material 410. .

Accordingly, the first transistor M1 is formed by the source electrode 402b and the drain electrode 402a and the gate electrode 407a formed on the active layer 402 and the lower electrode. The storage capacitor SC is formed by the metal layer 405 disposed over the 407b and the lower electrode 407b. In addition, the light emitting device is formed by the anode electrode 408, the light emitting material 410, and the cathode electrode 411.

FIG. 7 is another example of a projection plan view based on the layout of the pixels represented in FIG. 4. Referring to FIG. 7, four adjacent pixels are referred to as a first pixel 10, a second pixel 20, a third pixel 30, and a fourth pixel 40 from left to right. Scan lines made up of the first scan line Sk.1 and the second scan line Sk.2 are formed in the lower and upper portions of each light emitting device, respectively. The data lines D1, D2, and D3 and the power supply line Vdd are formed at regular intervals perpendicular to the scan lines, and the data lines D1, D2, and D3 are arranged on the left side and the second side of the first pixel 10. FIG. It is formed between the pixel 20 and the third pixel 30 and on the right side of the fourth pixel 40, on the right side of the first pixel 10, on the left side of the second pixel 20, and on the third pixel 30. The power supply line Vdd is formed on the right side of the left side and the left side of the fourth pixel 40.

The first pixel 10 and the third pixel 30 receive a selection signal through the second scan line Sk. 2 located above the pixel, and the second pixel 20 and the fourth pixel 40. The select signal is applied through the first scan line Sk. 1 under the pixel.

The pixel is connected to the power supply line Vdd through the first transistor M1, the drain electrode of the first transistor M1 is connected to the anode electrode of the first light emitting device LED1, and the source electrode is connected to the power supply line Vdd. ). The gate electrode is connected to the data lines D1, D2, and D3 through the second transistor M2. In addition, the storage capacitor SC is connected between the power supply line Vdd and the gate electrode.

In the second transistor M2, a gate electrode is connected to the first scan line Sk. 1 of the scan line, and a source electrode is connected to the data lines D1, D2, and D3. In addition, the drain electrode is connected to the gate electrode of the first transistor M1.

Therefore, as shown between the second pixel 20 and the third pixel 30, two adjacent pixels share one data line D2, and two power supply lines Vdd are adjacent to each other.

8 is another equivalent circuit diagram of a plurality of pixels employed in the EL display device according to the present invention. Referring to FIG. 8, in the electroluminescent display, the first scan line Sk.1 and the second scan line Sk.2 for applying the selection signal to the pixels located in the same row are arranged in the row direction, and the data line. And a power supply line are arranged in the column direction. The first scan line Sk.1 and the second scan line Sk.2 may be arranged adjacent to each other as shown in the drawing, or may be arranged at regular intervals. If the first scan line Sk.1 and the second scan line Sk.2 have a predetermined interval, the pixel is positioned therebetween. A plurality of pixels is connected to the scan line, the data line, and the power supply line. The pixel includes a light emitting device (LED), a first transistor M1, a storage capacitor SC, and a second transistor M2.

The first pixel 10, the second pixel 20, the third pixel 30, and the fourth pixel 40 are described in order from left to right, and the second pixel 20 is a first scan line. The gate electrode of the second transistor M2 is connected to Sk.1, and the gate electrode of the second transistor M2 is connected to the second scan line Sk.2 in the third pixel 30. In addition, the second data line D2 is positioned between the second pixel 20 and the third pixel 30, and the second transistor M2 of the second pixel 20 and the second pixel of the third pixel 30 are disposed. The source electrode of the transistor M2 is connected to the second data line D2. Thus, the second pixel 20 and the third pixel 30 share a data line. In the second transistor M2 of the second pixel 20 and the third pixel 30, a drain electrode is connected to a lower electrode of the storage capacitor SC and a gate electrode of the first transistor M1.

In addition, one power supply line is positioned between the first pixel 10 and the second pixel 20, the third pixel 30, and the fourth pixel 40, and the first pixel 10 and the second pixel ( 20 and the third pixel 30 and the fourth pixel 40 each share one power supply line Vdd.

The source electrode of the first transistor M1 in the second pixel 20 is connected to the power supply line Vdd and the drain electrode is connected to the anode electrode of the light emitting device. In this case, the first pixel 10 is connected to a power supply line different from the power supply line connected to the second pixel 20, and is connected to the drain electrode of each first transistor M1 to the anode electrode of each light emitting device. do.

In addition, the storage capacitor SC is connected to the pixel power supply line Vdd and the gate electrode of the first transistor M1.

Due to this configuration, when the selection signal is applied to the first scan line, the second pixel 20 is selected and the data signal input through the data line D2 is applied to the first transistor M1 of the second pixel 20. When the selection signal is applied to the gate electrode and the selection signal is applied to the second scan line, the third pixel is selected and the data signal input through the data line D2 is applied to the gate electrode of the first transistor M1 of the third pixel 30. To be authorized.

The storage capacitor SC maintains a signal input to the gate electrode of the first transistor M1 for a predetermined time so that the light emitting device emits light during the time.

9 is a perspective plan view based on the layout of the pixel represented in FIG. 8. Referring to FIG. 9, four adjacent pixels 10 are referred to as a first pixel 10, a second pixel 20, a third pixel 30, and a fourth pixel 40 from left to right. . Scan lines Sk.1 and Sk.2 each of the first scan line Sk.1 and the second scan line Sk.2 are horizontally adjacent to each other and formed in parallel to each other.

The data lines D1, D2, and D3 having a predetermined interval in the direction perpendicular to the scan lines Sk.1 and Sk.2 are formed, and the data lines D1, D2, and D3 are formed of the first pixel 10. On the left side, between the second pixel 20 and the third pixel 30 and to the right of the fourth pixel 40, between the first pixel 10 and the second pixel 20, A power supply line Vdd is formed between 30 and the fourth pixel 40. In addition, the first pixel 10, the second pixel 20, the third pixel 30, and the fourth pixel 40 are respectively the first light emitting device LED1, the second light emitting device LED2, and the third light emitting device. Element LED3 and fourth light emitting element LED4.

Thus, as shown between the second pixel 20 and the third pixel 30, two adjacent pixels share one data line and one power supply line.

In addition, a connector C is provided to prevent the second pixel 20 and the fourth pixel 40 from being connected to the first scan line Sk.1 and not connected to the second scan line Sk.2. The gate electrodes of the second transistor M1 of the second light emitting device LED2 and the fourth light emitting device LED4 are not connected to the second scanning line Sk.2 by the contactor C, but the first scanning line Sk. .1).

The storage capacitor SC is connected to one power supply line Vdd and is symmetrical with each other.

The connection of the storage capacitor SC is the same as that of FIG. 5 and will be omitted.

FIG. 10 is another example of a perspective plan view based on the layout of the pixel represented in FIG. 8. Referring to FIG. 10, the first pixel 10, the second pixel 20, the third pixel 30, and the fourth pixel 40 are referred to from left to right. Scan lines made up of the first scan line Sk.1 and the second scan line Sk.2 are formed in the lower and upper portions of each pixel, respectively. The data lines D1, D2, and D3 and the power supply line Vdd are formed at regular intervals perpendicular to the scan line, and the data lines are formed on the left side of the first pixel 10, the second pixel 20, and the third pixel. It is formed between the pixels 30 and on the right side of the fourth pixel 40, between the first pixel 10 and the second light emitting element 20, between the third pixel 30 and the fourth pixel 40. The power supply line Vdd is formed in the. Therefore, two adjacent pixels share one data line and a power supply line Vdd.

In addition, the first light emitting device LED1 and the third light emitting device LED3 receive a selection signal through the second scanning line Sk. 2 located above the pixel, and the second light emitting device LED2 and the fourth light emission. The device LED4 receives the selection signal through the first scan line Sk.1 under the pixel. Therefore, the configuration of two adjacent pixels is shown to be symmetrical 180 degrees to each other.

The second pixel 20 is connected to the power supply line Vdd through the first transistor M1, the drain electrode of the first transistor M1 is connected to the anode electrode of the first light emitting device LED1, and the source electrode. Is connected to the power supply line Vdd. The gate electrode is connected to the data line through the second transistor M2. In addition, the storage capacitor SC is connected between the power supply line Vdd and the gate electrode.

In the second transistor M2, a gate electrode is connected to the first scan line Sk. 1 of the scan line, and a source electrode is connected to the data line D2. In addition, the drain electrode is connected to the gate electrode of the first transistor M1, and the third pixel 30 has the same configuration as that of the second pixel 20, and the second transistor M2 has the second scan line Sk. 2) connected to the configuration.

Therefore, as shown between the second pixel 20 and the third pixel 30, two adjacent light emitting devices share one data line and one power supply line.

3 to 10 have a problem in that the amount of current flowing through each pixel is different when the threshold voltage of the first transistor M1 is different, which makes it difficult to display a uniform image. . Therefore, in order to solve this problem, various methods have been proposed in which the amount of current flowing through the pixel is constant regardless of the magnitude of the Vth voltage.

In the method of making the current amount constant, the scanning line and the data line can be configured as shown in FIGS. 3 to 10, so that the power supply line and the data line are not adjacent to each other so that a short circuit does not occur between the power supply line and the data line. It is also possible.

While preferred embodiments of the present invention have been described using specific terms, such descriptions are for illustrative purposes only, and it is understood that various changes and modifications may be made without departing from the spirit and scope of the following claims. Should be done.

In the electroluminescent display according to the present invention, a pixel is positioned between a power supply line and a data line to maintain a constant distance between the power supply line and the data line, thereby preventing short circuit failure between the power supply line and the data line. Can be.

In addition, since the two pixels share one data line or / and power supply line in common, the number of wirings around the pixels of the electroluminescent display can be reduced and simplified, thereby simplifying the process of the electroluminescent display to reduce the production cost. You can save.

1 is an equivalent circuit diagram of a plurality of pixels employed in an electroluminescent display according to the related art.

FIG. 2 is a transmissive plan view illustrating a layout of the electroluminescent display of FIG. 1.

3 is a configuration diagram showing the configuration of an embodiment of an electroluminescent display according to the present invention.

4 is an equivalent circuit diagram of a plurality of pixels employed in an electroluminescent display according to the present invention.

FIG. 5 is a perspective plan view based on the layout of the pixel represented in FIG. 4.

6 illustrates a cross-sectional structure along the line VI-VI ′ of FIG. 5.

FIG. 7 is another example of a projection plan view based on the layout of the pixels represented in FIG. 4.

8 is another equivalent circuit diagram of a plurality of pixels employed in the EL display device according to the present invention.

9 is a perspective plan view based on the layout of the pixel represented in FIG. 8.

FIG. 10 is another example of a perspective plan view based on the layout of the pixel represented in FIG. 8.

*** Description of the main parts of the drawings ***

100: pixel portion 200: scan driver

300: data driver S1, S2: first scan line, second scan line

D1, D2, D3: data lines M1, M2: first transistor, second transistor

SC: Storage Capacitor Vdd: Power Supply Line

Claims (6)

A pixel portion in which a plurality of pixels are arranged in a plurality of rows and columns to display an image; A plurality of data lines for applying a data signal to the plurality of pixels; A plurality of scan lines for applying a selection signal to the plurality of pixels; And It includes a plurality of power supply lines for supplying power to the plurality of pixels, And two adjacent pixels in one row of the plurality of pixels share one data line of the plurality of data lines and are respectively connected to two different scan lines of the plurality of scan lines. The method of claim 1, And two power supply lines of the plurality of power supply lines are respectively connected to the two adjacent pixels. The method of claim 1, Two pixels are connected to one power supply line of the plurality of power supply lines, and the two pixels are connected to two different data lines. The method of claim 1, And two scan lines connected to two adjacent pixels positioned in the one row are arranged adjacent to each other. The method of claim 1, And two scan lines connected to two adjacent pixels positioned in the one row are disposed to face each other with the pixels interposed therebetween. The method of claim 1, The pixel may include a switching transistor configured to apply a data signal applied to the data line to the first node in response to a selection signal applied to the scan line; A first capacitor connected to the first node and a second terminal connected to a power supply line, the first capacitor maintaining a constant voltage for a predetermined period of time; A gate is connected to the first node, a source is connected to the power supply line, and includes a driving transistor for flowing a current through the light emitting device in response to the voltage charged in the first capacitor, And two adjacent pixels connected to different scan lines.