KR20050079729A - Correlated double sampling circuit having reduced number of sampling capacitor and cmos image sensor including the same - Google Patents

Abstract

Correlated Double Sampling (CDS) circuits and CMOS with them, which can greatly reduce the layout area, prevent the timing of applying the offset voltage from being restricted by other operations, and eliminate the voltage distortion of the ramp signal. An image sensor is disclosed. The CDS circuit includes a capacitor having one end connected to an output terminal of a pixel sensor included in a CMOS image sensor, and a comparator having a ramp signal applied directly to a positive input terminal without passing through a capacitor, and the other end of the capacitor connected to a negative input terminal. Characterized in having a.

Description

Correlated double sampling circuit having reduced number of sampling capacitor and CMOS image sensor including the same}

TECHNICAL FIELD The present invention relates to a CMOS image sensor, and more particularly, to a correlated double sampling (CDS) circuit for a CMOS image sensor.

The image sensor refers to a device for capturing an image by using a property of a semiconductor that reacts to light. Most of the image sensors developed in the past have used a charge coupled device (CCD).

Recently, however, with the rapid development of CMOS technology, many image sensors using CMOS transistors are being developed. Such a CMOS image sensor is an analog-to-digital converter (Analog-Digital), which is implemented as a separate integrated circuit in a conventional CCD image sensor. Converter, hereinafter referred to as ADC) has the advantage that can be included inside.

On the other hand, the analog-to-digital converter in such a CMOS image sensor is generally composed of a correlated double sampling (hereinafter referred to as CDS) structure and includes as many comparators as the number of columns of a pixel sensor array in the image sensor. These comparators are the components that greatly affect the quality of the output image because they perform the function of converting pixel signals into digital signals.

1 is a block diagram of a column-parallel CMOS image sensor having a CDS structure.

Referring to FIG. 1, a column-parallel CMOS image sensor having a CDS structure includes an active pixel sensor array 11, an ADC 12 having a CDS structure, a data buffer 13, and a ramp. A signal generator 14, a row driver 15, and a timing control signal generator 16 are provided.

The ADC 12 (hereinafter referred to as a CDS circuit) generally uses a single-slope ADC because all columns simultaneously perform an analog-to-digital conversion function in each row.

FIG. 2 is a circuit diagram illustrating an active pixel sensor and a CDS circuit illustrated in FIG. 1, and FIG. 3 is an operation timing diagram of the CDS circuit of FIG. 2.

The active pixel sensor 21 has a structure including four transistors M1-M4 and a photo diode D1. The CDS circuit 23 converts the output signal VIN of the pixel sensor 21 into a digital signal by correlated double sampling using the ramp signal VRAMP and switches S1-S4 and capacitors. And C0-C2 and inverters INV1 and INV2. The ramp signal VRAMP is generated by the ramp signal generator 14 of FIG. 1.

More specifically, the reset voltage Vres and the pixel signal voltage Vsig of the pixel sensor 21 are sampled and stored in the capacitor C0. However, since the DC voltage value of the lamp signal VRAMP should not affect the signal sampling, a capacitor C1 is attached to the node Vx so that the DC voltage value of the lamp signal VRAMP is blocked through the capacitor C1, and the ramp signal is blocked. Only the voltage change of VRAMP is transmitted to the node Vx.

Therefore, when the voltage value of the ramp signal VRAMP transmitted to the node Vx rises by the difference between Vres and Vsig, the state of the output signal OUT1 is changed and the output signal OUT1 is the capacitor C2 and the inverter ( It is input to the data buffer 13 through INV2).

However, the above-described disadvantage of the conventional CDS circuit 23 is that the two capacitors (C0, C1) for sampling and storing the output signal (VIN) of the pixel sensor 21 and blocking the DC voltage value of the ramp signal (VRAMP) Is necessary. However, since these capacitors occupy most of the layout area of the CDS circuit 23, the total chip area is increased.

In addition, in the conventional CDS circuit 23, when the offset Voff is to be applied to the signal as shown in FIG. 4, the signal controlling the on / off of the switch S1 goes to the second high. Only after the transition, that is, after all signal sampling operations have been completed, can the offset be added. This is because when the offset is applied before the signal sampling, the offset value disappears as the Vx node is updated with the Vsig voltage again during signal sampling. As such, the time point at which the offset is applied must be made after the signal sampling reduces the margin for the overall operation timing of the CDS circuit 23.

In the conventional CDS circuit 23, since the input capacitance of the first inverter INV1 and the junction capacitance of the switch S3 are small, the voltage of the ramp signal VRAMP transmitted to the node Vx is reduced. Not all of them are delivered to the IN1 node, but gain is applied as shown in the following equation, resulting in distortion of the voltage of the ramp signal VRAMP.

{C0 * C1 / (C0 + C1)} / {C0 * C1 / (C0 + C1) + Cin}

Here, Cin represents the sum of the input capacitance of the inverter INV1 and the junction capacitance of the switch S3.

Therefore, the technical problem to be achieved by the present invention is to reduce the number of capacitors used by separating the node for sampling the pixel signal and the node for transmitting the ramp signal, which can greatly reduce the layout area and the operation of different timing for applying the offset voltage It is to provide a CDS circuit that can be free from the constraints and eliminate the voltage distortion of the ramp signal.

Another object of the present invention is to provide a CMOS image sensor having the CDS circuit as described above.

According to an aspect of the present invention, a CDS circuit includes: a CDS circuit of a CMOS image sensor, comprising: a capacitor having one end connected to an output terminal of a pixel sensor included in the CMOS image sensor; And a comparator having a ramp signal directly applied to the positive input terminal without passing through the capacitor and a negative terminal connected to the other end of the capacitor.

The CDS circuit may further include a first switch connected between an output terminal of the pixel sensor and one end of the capacitor and / or a second switch connected between the ramp signal and a positive input terminal of the comparator.

The CDS circuit may further include a third switch connected between the negative input terminal of the comparator and the output terminal of the comparator.

The CDS circuit may further include: another capacitor having one end connected to an output terminal of the comparator; An inverter having an input connected to the other end of the other capacitor; And another switch connected between the input terminal of the inverter and the output terminal of the inverter.

The comparator consists of a differential amplifier.

According to another aspect of the present invention, a CMOS image sensor includes a pixel sensor; And a correlated double sampling circuit for sampling an output signal of the pixel sensor and converting the output signal of the pixel sensor into a digital signal, wherein the correlated double sampling circuit comprises: the pixel to which the output signal is output; A capacitor having one end connected to the output terminal of the sensor; And a comparator having the ramp signal directly applied to the positive input terminal without passing through the capacitor and the other end of the capacitor connected to the negative input terminal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

5 is a circuit diagram illustrating a CDS circuit for a CMOS image sensor according to an exemplary embodiment of the present invention. Here, the pixel sensor 51 is shown together for convenience of description.

Referring to FIG. 5, the CDS circuit 53 according to an embodiment of the present invention may correlate double sampling the output signal VIN of the pixel sensor 51 using a ramp signal VRAMP. Convert to a digital signal. The CDS circuit 53 according to an embodiment of the present invention includes four switches S1-S4, two capacitors C0 and C2, a comparator CP composed of a differential amplifier, and an inverter INV. Equipped. The ramp signal VRAMP is generated by the ramp signal generator 14 of FIG. 1.

The switch S1 is connected between the output terminal of the pixel sensor 51 and one end of the capacitor C0. The other end of the capacitor C0 is connected to the negative input terminal of the comparator CP. The switch S2 is connected between the ramp signal VRAMP and the positive input terminal of the comparator CP. Therefore, the ramp signal VRAMP is directly applied to the positive input terminal of the comparator CP without passing through the capacitor. Meanwhile, the switch S1 and / or the switch S2 may not be included as necessary.

The switch S3 is connected between the negative input terminal of the comparator CP and the output terminal of the comparator CP. One end of the capacitor C2 is connected to the output terminal of the comparator CP, the inverter INV is connected to the other end of the capacitor C2, and the output signal OUT2 of the inverter INV is the data shown in FIG. It is input to the buffer 13. The switch S4 is connected between the input terminal of the inverter INV and the output terminal of the inverter INV.

More specifically, in the CDS circuit according to the present invention, a differential amplifier is used as a comparator CP, and an output signal VIN of the pixel sensor 51 through the capacitor C0 is applied to the negative input terminal, that is, the pixel sensor 51. The difference between the reset voltage Vres and the pixel signal voltage Vsig is sampled and the ramp signal VRAMP is directly applied to the positive input terminal without passing through the capacitor. This reduces one capacitor compared to conventional CDS circuits.

6 is an operation timing diagram of a CDS circuit according to the present invention of FIG. 5. The operation of the CDS circuit according to the present invention of FIG. 5 is described in detail with reference to this. First, all the switches S1-S4 are turned on at the ① point. As a result, Vcom, the start voltage of the ramp signal VRAMP, enters the positive input terminal of the comparator CP and the comparator CP receives unity-gain feedback. Got caught.

Next, after all of the switches S1-S4 are turned off at the point ②, the control signal TG of the pixel sensor 51 is activated to a logic high, so that the pixel signal voltage Vsig becomes the output terminal of the pixel sensor 51. Vin). Next, at the point 3, S1 and S2 are turned on again, and the difference between the reset voltage Vres and the pixel signal voltage Vsig of the pixel sensor 51 is stored in C0. Next, at the point ④, the voltage level of the ramp signal VRAMP begins to drop and at the point ⑤ where Vres-Vsig is dropped from Vcom, the final output OUT2 transitions from low to high. At this time, the counter (not shown) code value CODE becomes an output value of the pixel.

The best embodiment has been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, in the CDS circuit according to the present invention, since one capacitor is reduced as compared with the related art, the layout area may be greatly reduced. In addition, as shown in FIG. 7, when the offset voltage Voff is applied, there is no need to wait until signal sampling is completed, unlike in the prior art. This is because the node sampling the output signal VIN of the pixel sensor 51, that is, the node sampling the reset voltage Vres and the pixel signal voltage Vsig of the pixel sensor 51 and the node to which the ramp voltage VRAMP is transmitted are different from each other. to be. Accordingly, since the operation of applying the offset voltage Voff is independent from other signal sampling operations, the CDS timing can be more relaxedly operated. In addition, since the ramp signal VRAMP is directly applied to the positive input terminal of the comparator CP, there is an advantage in that voltage distortion of the ramp signal due to parasitic capacitance components is eliminated.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram of a column-parallel CMOS image sensor having a CDS structure.

FIG. 2 is a circuit diagram illustrating an active pixel sensor and a CDS circuit shown in FIG. 1.

3 is an operation timing diagram of the CDS circuit of FIG. 2.

4 is a timing diagram when an offset is to be applied in the CDS circuit of FIG. 2.

5 is a circuit diagram illustrating a CDS circuit for a CMOS image sensor according to an exemplary embodiment of the present invention.

6 is an operation timing diagram of a CDS circuit according to the present invention of FIG. 5.

FIG. 7 is a timing diagram when an offset is to be applied in the CDS circuit of FIG. 5.

Claims (14)

In a correlated double sampling (CDS) circuit of a CMOS image sensor, A capacitor having one end connected to an output terminal of the pixel sensor included in the CMOS image sensor; And And a comparator having a ramp signal directly applied to the positive input terminal without passing through the capacitor, and a comparator connected to the negative input terminal of the other end of the capacitor. The method of claim 1, And a switch coupled between the output terminal of the pixel sensor and one end of the capacitor. The method of claim 1, And a switch coupled between the ramp signal and the positive input terminal of the comparator. The method of claim 1, A first switch connected between an output terminal of the pixel sensor and one end of the capacitor; And And a second switch connected between the ramp signal and the positive input terminal of the comparator. The method of claim 1, And a switch connected between the negative input terminal of the comparator and the output terminal of the comparator. The method of claim 5, Another capacitor having one end connected to an output terminal of the comparator; An inverter having an input connected to the other end of the other capacitor; And And a further switch connected between the input end of the inverter and the output end of the inverter. 2. The correlated double sampling circuit of claim 1, wherein the comparator comprises a differential amplifier. Pixel sensors; And A correlated double sampling circuit for sampling the output signal of the pixel sensor using a ramp signal and converting the signal into a digital signal; The correlated double sampling circuit, A capacitor having one end connected to an output terminal of the pixel sensor to which the output signal is output; And And a comparator having a positive input terminal directly applied to the ramp signal without passing through a capacitor and a negative input terminal having a comparator connected to the other end of the capacitor. The method of claim 8, wherein the correlated double sampling circuit comprises: And a switch connected between the output terminal of the pixel sensor and one end of the capacitor. The method of claim 8, wherein the correlated double sampling circuit comprises: And a switch connected between the ramp signal and a positive input terminal of the comparator. The method of claim 8, wherein the correlated double sampling circuit comprises: A first switch connected between an output terminal of the pixel sensor and one end of the capacitor; And And a second switch connected between the ramp signal and a positive input terminal of the comparator. The method of claim 8, wherein the correlated double sampling circuit comprises: And a switch connected between the negative input terminal of the comparator and the output terminal of the comparator. The method of claim 12, wherein the correlated double sampling circuit comprises: Another capacitor having one end connected to an output terminal of the comparator; An inverter having an input connected to the other end of the other capacitor; And And another switch connected between the input terminal of the inverter and the output terminal of the inverter. 10. The CMOS image sensor of claim 8, wherein the comparator comprises a differential amplifier.