KR20050024099A - method of fabricating SRAM device and SRAM device fabricated thereby - Google Patents

Abstract

PURPOSE: A method of manufacturing an SRAM(Static Random Access Memory) device and the SRAM device thereof are provided to prevent impurities from diffusing between an N type gate electrode and a P type gate electrode by using a gate isolating layer. CONSTITUTION: A gate conductive layer is formed on a semiconductor substrate(300) with an NMOS(N channel Metal Oxide Semiconductor) transistor region and a PMOS(P channel MOS) transistor region. An N type gate electrode(307a) and a P type gate electrode(309a) are formed within the NMOS and PMOS transistor regions by patterning the gate conductive layer. At this time, the N type and P type gate electrodes are adjacent to each other. An insulating layer for filling a gap between the N type and P type gate electrodes is formed thereon. A spacer(316) for covering sidewalls of the gate electrodes and a gate isolating layer(318) between the gate electrodes are simultaneously formed by performing an etch-back process on the insulating layer.

Description

Method of fabricating SRAM device and SRAM device manufactured thereby Method of fabricating SRAM device and SRAM device fabricated thereby

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device manufactured thereby, and more particularly, to a method for manufacturing a static random access memory (SRAM) device and an SRAM device manufactured thereby.

One of the semiconductor memory devices, an SRAM device, has an advantage of having a low power consumption and a high operating speed as compared to a DRAM device. Therefore, the SRAM device has been widely adopted in portable electronic products. In addition, the SRAM device is widely used as a cache memory device of a computer.

The unit cells of the SRAM device may be classified into a load resistor cell and a CMOS cell. The load resistance cell uses a resistor as a load element, and the CMOS cell uses a PMOS transistor as a load element. The CMOS cells may be further classified into thin film transistor cells and full CMOS cells. The thin film transistor cell uses a PMOS thin film transistor as a load element, and the complete CMOS cell uses a PMOS bulk transistor formed on a semiconductor substrate as a load element. The thin film transistor cell is advantageous in terms of integration degree compared to the full CMOS cell, but has a disadvantage in that the manufacturing process is complicated. Therefore, recently, the complete CMOS cell has been widely adopted in SRAM devices.

The full CMOS SRAM cell includes a pair of NMOS driving transistors, a pair of NMOS transfer transistors, and a pair of PMOS load transistors. In this case, either one of the pair of NMOS driving transistors and one of the pair of PMOS load transistors constitutes a first inverter, and the pair of the other of the pair of NMOS driving transistors. Another one of the PMOS load transistors constitutes a second inverter. The NMOS driving transistor and the PMOS load transistor of each of the inverters share one gate electrode. That is, a pair of dual gate electrodes are formed in one SRAM cell region. Here, each of the dual gate electrodes includes an N-type gate electrode and a P-type gate electrode connected to each other.

1 is a cross-sectional view showing a portion of a conventional fully CMOS SRAM cell. In Fig. 1, the region denoted by reference numeral "A" is an NMOS driving transistor region (hereinafter referred to as NMOS region), and the region denoted by "B" is a PMOS load transistor region adjacent to the NMOS driving transistor region (hereinafter referred to as "N"). PMOS region).

Referring to FIG. 1, an isolation layer 102 is disposed in a predetermined region of a semiconductor substrate 100. The device isolation layer 102 defines active regions in the NMOS region A and the PMOS region B. A gate oxide film 104 and a polysilicon film are sequentially formed on the semiconductor substrate having the device isolation film 102. The polysilicon layer is patterned to form dual gate electrodes 106 crossing the NMOS region and the PMOS regions A and B. The dual gate electrode 106 has a structure in which an N-type gate electrode 108 on the NMOS region A and a P-type gate electrode 110 on the PMOS region B are connected to each other. Thereafter, N-type impurity ions and P-type impurity ions are selectively implanted into the NMOS region A and the PMOS region B, respectively, to form a source and a drain in the active regions, respectively. N-type impurity ions and P-type impurity ions are implanted into the 108 and the P-type gate electrode 110, respectively. The diffusion depth of the impurity ions should be deep in the dual gate electrode 106 and shallow in the source and drain.

As described above, when impurity ions are simultaneously implanted into the source region and the drain region and the N-type gate electrode 108 or the P-type gate electrode 110, the diffusion depth of impurity ions in the source and drain is preferentially given. In consideration of this, the depth of the diffusion layer of the impurity ions in the N-type gate electrode 108 and the P-type gate electrode 110 is insufficient. As a result, a depletion region is generated under the N-type gate electrode 108 and the P-type gate electrode 110, thereby degrading the characteristics of the complete CMOS transistor. In addition, considering the diffusion depth of the impurity ions in the N-type gate electrode 108 and the P-type gate electrode 110, it is difficult to realize a shallow junction in the source and drain, and punch-write It is vulnerable to punch-through.

In order to overcome these disadvantages, a polysilicon film is formed on the semiconductor substrate 100 before the dual gate electrode 106 is formed, and then the NMOS region A and the PMOS region B on the polysilicon film are formed. ) Selectively inhibits the depletion phenomenon by adding a step of pre-doping the N-type and P-type impurity ions, respectively.

However, when the pre-doping process is added as described above, excess impurity ions may be implanted into the dual gate electrode 106 in a subsequent source and drain impurity ion implantation process. As a result, in the subsequent annealing process, each of the N-type and P-type impurities in the N-type gate electrode 108 and the P-type gate electrode 110 is an interface between the N-type gate electrode 108 and the P-type gate electrode 110. Through the diffusion 112, the threshold voltages of the NMOS driving transistors and the PMOS load transistors constituting the inverter may be changed to deteriorate characteristics of the complete CMOS SRAM device.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing an S-RAM device capable of suppressing interdiffusion of impurity ions at an N-type gate electrode and a P-type gate electrode interface constituting a dual gate electrode in an S-RAM device. There is.

Another object of the present invention is to provide an SRAM device manufactured by the method of manufacturing the SRAM device.

In order to achieve the above technical problem, the present invention provides a method for manufacturing the SRAM device. This method forms a gate conductive film on a semiconductor substrate having NMOS transistor regions and PMOS transistor regions adjacent to each other. The gate conductive layer is patterned to form an N-type gate electrode and a P-type gate electrode in the NMOS transistor region and the PMOS transistor region, respectively, wherein one end of the N-type gate electrode is adjacent to one end of the P-type gate electrode. Form. An insulating film is formed on the entire surface of the semiconductor substrate having the N-type gate electrode and the P-type gate electrode, wherein the insulating film is located on the boundary region between the NMOS transistor region and the PMOS transistor region. It is formed to fill the gap region between the type gate electrode. The insulating layer is etched back to form a spacer covering sidewalls of the gate patterns, and a gate separation layer remaining in the gap region between the N-type gate electrode and the P-type gate electrode is formed. Subsequently, a local wiring is formed to cover the gate separation layer and to contact upper surfaces of the N-type gate electrode and the P-type gate electrode.

In order to achieve the above another technical problem, the present invention provides an SRAM device manufactured by the method of manufacturing the SRAM device. The SRAM device includes a semiconductor substrate having an NMOS transistor region and an adjacent PMOS transistor region. An N-type gate electrode disposed on the semiconductor substrate in the NMOS transistor region and a P-type gate electrode disposed on the semiconductor substrate in the PMOS transistor region, one end of which is adjacent to one end of the N-type gate electrode; Include. Further, spacers covering sidewalls of the N-type gate electrode and the P-type gate electrode and a gap region between the N-type gate electrode and the P-type gate electrode positioned on the boundary region between the NMOS transistor region and the PMOS transistor region. And a gate separator remaining in the film. A local wiring covering the gate separation layer and contacting upper surfaces of the N-type gate electrode and the P-type gate electrode.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

2 is a unit cell circuit diagram of a typical complete CMOS SRAM device.

Referring to FIG. 2, the unit cell of the complete CMOS SRAM device includes a pair of CMOS transistors C1 and C2 provided as an inverter and two NMOS transistors provided as a transfer transistor. The CMOS transistors C1 and C2 may include a first CMOS transistor C1 including a first NMOS transistor Q3 and a first PMOS transistor, a second NMOS transistor Q4, and a second PMOS transistor. It consists of the 2nd CMOS transistor C2. The first and second NMOS transistors Q3 and Q4 are provided as driver transistors, and the first and second PMOS transistors Q5 and Q6 are provided as load transistors. Lose. A storage node N1 of the first CMOS transistor C1 is connected to a gate of the second NMOS transistor Q4 and the second PMOS transistor Q6, and the second CMOS transistor C2 is connected to the gate of the second NMOS transistor Q4. A storage node N2 is connected to the gates of the first NMOS transistor Q3 and the first PMOS transistor Q5. Sources of the transfer transistors Q1 and Q2 are connected to bit lines BL and / BL, gates are connected to word lines WL, and drains of the pair of CMOS transistors C1 and C2 are stored. Are connected to nodes N1 and N2, respectively. The sources of the load transistors Q5 and Q6 are connected to a power supply voltage Vcc, and the sources of the driving transistors Q3 and Q4 are connected to a ground power supply Vss.

3 is a partial plan view of a cell array of a fully CMOS SRAM device according to an embodiment of the present invention, Figures 4 to 11 illustrate a method of manufacturing a complete CMOS SRAM device according to an embodiment of the present invention. 3 are cross-sectional views taken along the lines I to I 'of FIG. 3 to 11, a region denoted by reference numeral 'A' is an NMOS transistor region (hereinafter referred to as NMOS region), and a region denoted by reference numeral 'B' 'is a PMOS transistor region adjacent to the NMOS transistor region. (Hereinafter referred to as PMOS region).

3 and 4, an isolation layer 302 is formed in a predetermined region of the semiconductor substrate 300. The isolation layer 302 defines active regions 301 in the NMOS region A ′ and the PMOS region B ′. Thereafter, a conventional well forming process is performed to form N type wells and P type wells in the semiconductor substrate 300, respectively. Subsequently, a gate oxide film 304 and a gate conductive film 306 are sequentially formed on the semiconductor substrate having the device isolation film 302. The gate oxide film 304 may be formed of a thermal oxide film. The gate conductive layer 306 may be formed of a polysilicon layer.

3 and 5, a first photoresist pattern 308 is formed on the gate conductive layer 306 of the PMOS region B ′. N-type impurity ions 310 are implanted into the gate conductive layer 306 of the NMOS region A ′ using the first photoresist pattern 308 as an ion implantation mask. Subsequently, the same process is performed on the PMOS region B 'to implant P-type impurity ions into the gate conductive layer 306 of the PMOS region B'. As a result, an N-type impurity diffusion layer 307 and a P-type impurity diffusion layer 309 are formed in the gate conductive film 306 of the NMOS region A 'and the PMOS region B', respectively.

3 and 6, the gate conductive layer 306 is patterned to form N-type gate electrodes 307a and P on the semiconductor substrates of the NMOS region A ′ and the PMOS region B ′, respectively. The type gate electrode 309a is formed. As shown in FIG. 3, the N-type gate electrode 307a and the P-type gate electrode 309a are formed in a direction crossing the NMOS region A 'and the PMOS region B'. In addition, the N-type gate electrode 307a and the P-type gate electrode 309a are patterned to have a gap region on the device isolation layer 302 of the boundary region between the NMOS region A 'and the PMOS region B'. .

3 and 7, a second photoresist pattern 312 is formed on the PMOS region B ′ of the semiconductor substrate having the N-type gate electrode 307a and the P-type gate electrode 309a. . N-type impurity ions 314 are implanted into the semiconductor substrate of the NMOS region A 'using the second photoresist pattern 312 as an ion implantation mask. Subsequently, the same process is performed on the PMOS region B 'to implant P-type impurity ions into the semiconductor substrate of the PMOS region B'. As a result, LDD sources and LDD drains are formed in the active regions 301 of the NMOS region A 'and the PMOS region B', respectively. At the same time, impurity ions are again implanted into the N-type gate electrode 307a and the P-type gate electrode 309a which are pre-doped in the process of implanting the impurity ions into the gate conductive layer 306 as described above.

3 and 8, an insulating film is formed on the entire surface of the semiconductor substrate 300 having the LDD source and the LDD drain. The insulating layer is formed to fill the gap region between the N-type gate electrode 307a and the P-type gate electrode 309a positioned on the boundary region between the NMOS region A 'and the PMOS region B'. . The insulating film may be formed of a silicon nitride film. Subsequently, the insulating layer is etched back to form a spacer 316 covering sidewalls of the N-type gate electrode 307a and the P-type gate electrode 309a. At the same time, a gate separation film 318 remaining in the gap region between the N-type gate electrode 307a and the P-type gate electrode 309a is formed. The gate isolation layer 318 is formed on the device isolation layer 302 at the boundary between the NMOS region A 'and the PMOS region B, and both sidewalls of the gate isolation layer 318 are formed on the N-type gate electrode 307a, respectively. And one side walls of the P-type gate electrode 309a.

3 and 9, a third photoresist pattern 320 is formed on the PMOS region B ′ of the semiconductor substrate having the spacer 316 and the gate isolation layer 318. N-type impurity ions 322 are implanted into the semiconductor substrate of the NMOS region A ′ using the third photoresist pattern 320 as an ion implantation mask. Subsequently, the same process is performed on the PMOS region B 'to implant P-type impurity ions into the semiconductor substrate of the PMOS region B'. As a result, sources and drains are formed in the active regions 301 of the NMOS region A 'and the PMOS region B, respectively. At the same time, N-type impurity ions and P-type impurity ions are selectively implanted into the N-type gate electrode 307a and the P-type gate electrode 309a of the NMOS region A 'and the PMOS region B', respectively. .

3 and 10, an interlayer insulating film 324 is formed on the entire surface of the semiconductor substrate 300 having the source and drain. Subsequently, an upper surface of the interlayer insulating film 324 is planarized. The interlayer insulating film 324 may be formed of a silicon oxide film. Subsequently, the interlayer insulating layer 324 is patterned so that the N-type gate electrode 307a and the P-type gate electrode 309a of both sides contact the upper surface of the gate isolation layer 318 and both sidewalls of the gate isolation layer 318. A wiring groove 326 is formed to expose the top surface of the substrate continuously.

3 and 11, a conductive material is deposited to fill the wiring groove 326 on the entire surface of the semiconductor substrate 300 having the wiring groove 326. Subsequently, a planarization process such as chemical mechanical polishing is performed to polish the conductive material until the top surface of the interlayer insulating layer 324 is exposed. As a result, a local wiring 328 made of the conductive material is formed in the wiring groove 326. The local wiring 328 is preferably formed of a metal wiring so as to form ohmic contact with the N-type gate electrode 307a and the P-type gate electrode 309a. The local wiring 328 may be formed of tungsten. The local wiring 328 electrically connects the N-type gate electrode 307a and the P-type gate electrode 309a on both sides of the gate isolation layer 318 electrically insulated by the gate separation layer 318.

In the above embodiment, a case of a fully CMOS SRAM device has been described as an example, but it is obvious that the spirit of the present invention can be applied to all semiconductor devices having a dual gate structure.

As described above, according to the present invention, an N-type gate electrode and a P-type gate electrode generated in a conventional dual gate electrode are formed by forming a gate separator made of an insulating film between an N-type gate electrode and a P-type gate electrode in an S-RAM device. By preventing the interdiffusion of impurity ions at the interface of the SRAM device it is possible to prevent the characteristics of the deterioration. In addition, since the device isolation layer is formed at the same time in the conventional spacer forming process, no additional process is required.

1 is a cross-sectional view showing a portion of a conventional fully CMOS SRAM cell.

2 is a unit cell circuit diagram of a typical complete CMOS SRAM device.

3 is a partial plan view of a cell array of a fully CMOS SRAM device according to an embodiment of the present invention.

4 to 11 are cross-sectional views taken along line I ′ of FIG. 3 to explain a method of manufacturing a complete CMOS SRAM device according to an embodiment of the present invention.

* Description of the main parts of the drawing *

100,300: semiconductor substrate 102,302: device isolation film

106: dual gate electrode 104,304: gate oxide film

108, 307a: N-type gate electrode 110, 309a: P-type gate electrode

306: gate conductive film 310,314,322: impurity ion implantation

316: spacer 318: gate separator

324: interlayer insulating film 326: wiring groove

328 local wiring

Claims (10)

Forming a gate conductive film on a semiconductor substrate having an NMOS transistor region and a PMOS transistor region adjacent to each other, The gate conductive layer is patterned to form an N-type gate electrode and a P-type gate electrode in the NMOS transistor region and the PMOS transistor region, respectively, wherein one end of the N-type gate electrode is adjacent to one end of the P-type gate electrode. Formed, An insulating film is formed on the entire surface of the semiconductor substrate having the N-type gate electrode and the P-type gate electrode, wherein the insulating film is located on the boundary region between the NMOS transistor region and the PMOS transistor region. Is formed to fill the gap region between the type gate electrodes, Etching back the insulating film to form a spacer covering sidewalls of the N-type gate electrode and the P-type gate electrode, and at the same time forming a gate separation layer remaining in the gap region between the N-type gate electrode and the P-type gate electrode; Forming a local wiring covering the gate separation layer and in contact with upper surfaces of the N-type gate electrode and the P-type gate electrode. The method of claim 1, Prior to forming the N-type gate electrode and the P-type gate electrode, N-type impurity ions and P-type impurity ions are selectively implanted into the gate conductive layer on the NMOS transistor region and the PMOS transistor region, respectively, to form the N-type gate electrode and the P-type gate electrode. A method for manufacturing an S-RAM device further comprising forming an N-type impurity diffusion layer and a P-type impurity diffusion layer, respectively. The method of claim 1, Prior to forming an insulating film on the semiconductor substrate, N-type impurity ions and P-type impurity ions are selectively implanted into the NMOS transistor region and the PMOS transistor region, respectively, to form active regions on both sides of the N-type gate electrode and the P-type gate electrode. And forming an LDD source and an LDD drain, respectively, in the SRAM device. The method of claim 1, Prior to forming the local wiring, N-type impurity ions and P-type impurity ions may be selectively implanted into the NMOS transistor region and the PMOS transistor region, respectively, and then sourced into active regions on both sides of the N-type gate electrode and the P-type gate electrode, respectively. And forming a drain. The method according to any one of claims 1 to 4, And the NMOS transistor region and the PMOS transistor region are driving transistor regions and load transistor regions of an SRAM cell, respectively. The method of claim 1, And said gate conductive film is a polysilicon film. The method of claim 1, And the insulating film is a silicon nitride film. The method of claim 1, The local wiring is a method of manufacturing an SRAM device, characterized in that formed by tungsten. The method of claim 1, Forming the local wiring, An interlayer insulating film is formed on the entire surface of the semiconductor substrate having the spacers and the gate separation film; Patterning the interlayer insulating film to form a wiring groove exposing predetermined regions of upper surfaces of the N-type gate electrode and the P-type gate electrode on both sides of the gate separator and the gate separator; Depositing a conductive material to fill the wiring groove, And polishing the conductive material until the interlayer insulating film is exposed. A semiconductor substrate having an NMOS transistor region and an adjacent PMOS transistor region; An N-type gate electrode disposed on the semiconductor substrate in the NMOS transistor region; A P-type gate electrode disposed on the semiconductor substrate in the PMOS transistor region, one end of which is disposed adjacent to one end of the N-type gate electrode; Spacers covering sidewalls of the N-type gate electrode and the P-type gate electrode; A gate separator remaining in the gap region between the N-type gate electrode and the P-type gate electrode positioned on the boundary region between the NMOS transistor region and the PMOS transistor region; And And a local wiring covering the gate separator and contacting upper surfaces of the N-type gate electrode and the P-type gate electrode.