KR20050002072A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to improve reliability of repairing by minimizing the electric field between a fuse guard ring and a fuse. CONSTITUTION: A plurality of first fuses(51) spaced apart from each other are formed on a substrate by using conductive impurities. An interlayer dielectric(53a,53b) is formed on the resultant structure. By selectively etching the interlayer dielectric(53a) to form holes, a first fuse guard ring(52) as a closed loop is formed in the holes. Contact plugs(54) are formed to contact the first fuse through the interlayer dielectric. A plurality of second fuses(54) are formed to contact the contact plugs. A second fuse guard ring is formed on the first fuse guard ring.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to fuses used in a repair process of semiconductor devices.

In the manufacture of a semiconductor device, especially a memory device, if any one of a number of fine cells is defective, the semiconductor device does not function as a memory and thus is treated as a defective product. However, despite the fact that only a few cells in the memory have failed, discarding the entire device as defective is an inefficient process in terms of yield.

Therefore, at present, the yield improvement is achieved by replacing the defective cell in which a defect has occurred by using a spare cell previously installed in the memory device.

A repair operation using a spare cell typically includes a reserved word line for replacing a normal word line and a normal word line including a defective cell in which defects are generated by installing a reserved bit line for replacing a normal bit line in advance. The normal bit line is replaced with a spare word line or a spare bit line.

In detail, when a defect cell is selected through a test after wafer processing is completed, a program is performed in an internal circuit to change an address corresponding to the defective cell into an address of a spare cell. Therefore, in actual use, when an address signal corresponding to a defective cell is input, data of a spare cell replaced in correspondence with the defective cell is accessed.

The most widely used method as described above is to blow a fuse with a laser beam to blow, thereby replacing a path of an address. Therefore, the conventional memory device includes a fuse unit capable of replacing the address path by blowing the laser onto the fuse to blow.

The fuse unit includes a plurality of fuse sets, and one fuse set may replace one address path. The number of fuse sets provided in the fuse part is determined according to the number of spare word lines or spare bit lines provided according to the free area of the memory device. One fuse set includes a plurality of address fuses and replaces an address path by selectively blowing the plurality of address fuses.

1 is a cross-sectional view showing a semiconductor memory device according to the prior art, in which a left region shows a cross section of a cell region and a right region shows a fuse region.

As shown in FIG. 1, a cell region of a semiconductor memory device may include a device isolation layer 11, an active region 13, a gate pattern 14, and first and second storage node contact plugs 15a on a substrate 10. 18, the bit line contact plug 15b, the bit line 16, the storage node contact plugs 19 forming the capacitors 12, 17, 22, and 25, the dielectric thin film 20, and the plate electrode. (23,24). The plate electrodes 23 and 24 are composed of a polysilicon film 23 and a TiN film 24.

The fuse region of the semiconductor device includes a fuse composed of interlayer insulating films 11 ', 17' and 22 'on a substrate, a polysilicon film 23' and a TiN film 24 ', and an interlayer insulating film formed on the fuse. 25 ') and a guard ring 27 for preventing water penetration. In addition, reference numeral 26 denotes a fuse box formed by removing the interlayer insulating layer 21 on the fuse by a predetermined thickness for fuse blowing during the repair process. The interlayer insulating films 11 ', 17' and 22 'and the fuses 23' and 24 'are not manufactured separately, but the interlayer insulating films 11, 17 and 22 in the cell region and the plate electrodes 23 and 24 of the capacitor. Are each formed together.

As described above, a fuse is used to repair a defective portion when a semiconductor device fails, and is not formed separately by an additional process, but is a bit line or a word line in a cell region. It is formed using a conductive layer (for example, polysilicon) forming a line.

However, in recent years, as the degree of integration of semiconductor devices has increased, the height of the structure of semiconductor devices has also increased. As a result, when a fuse is formed using a word line or a bit line, which is a relatively substructure, many interlayer insulating films are formed to form a fuse box. Difficulties have to be eliminated.

Therefore, in recent years, a conductive layer formed at a high position of a semiconductor device is used as a fuse line, and a conductive film for a plate electrode of a metal wiring or a capacitor is used as a fuse line. The fuses 23 'and 24' shown in Fig. 1 are also formed of a conductive film forming the plate electrodes 23 and 24 of the capacitor formed in the cell region.

Fig. 2 is a plan block diagram showing a conventional semiconductor memory device.

Referring to FIG. 2, a semiconductor memory device includes a cell array (cell array 0 to cell array 7) including a plurality of memory cells. One cell array (eg, cell array 3) includes a normal cell region including a plurality of normal cells, a spare cell region including a spare cell for replacing a normal cell found in a defect, and a normal cell in which a defect is found. A fuse unit 100 having a plurality of fuse sets for replacing an address path to replace a spare cell is provided.

The spare cell is a cell additionally provided to replace the normal cell when an error occurs. However, the number of spare cells cannot be made unconditionally due to the limitation of the area. Therefore, the number of spare cells is appropriately determined in consideration of the area after making normal cells. The number of fuse sets provided in the fuse unit is determined according to the number of spare cells included in one cell array.

3 is a plan view illustrating the fuse unit illustrated in FIG. 2.

Referring to FIG. 3, the fuse unit 100 includes 16 normal fuse sets to replace 16 addresses. The number of low addresses and column addresses that can be replaced is determined according to the number of spare cells included in one cell array, and the number of fuse sets provided in the fuse unit 100 is determined according to the number of addresses determined here. All. For example, if the normal fuse set shown in FIG. 3 substitutes only a low address, a total of 16 word lines in one cell array may be replaced with a spare word line.

FIG. 4 is a fuse set showing one of the sixteen normal fuse sets shown in FIG.

Referring to FIG. 4, one normal fuse set (eg, 110) may include a plurality of address fuses A0 to AA to correspond to an address, and an enable fuse to enable the normal fuse set 210. It is provided. Here, 30 denotes a fuse guard ring, and the four dummy fuses shown are used in actual repair because fuses formed close to the fuse guard ring due to the characteristics of the semiconductor manufacturing process are manufactured properly and reliably and are difficult to be used during the repair process. I decided not to.

Hereinafter, a process of relieving a cell in which a defect is found using a fuse in a memory device will be described. When an error is found in the normal cell included in the cell array after the semiconductor memory device is completed, the laser is selectively irradiated with the address fuses A0 to AC included in one normal fuse set according to the address where the error cell is found. And blow. By doing so, when an address corresponding to an error cell is input in actual operation, the reserved cell determined through the repaired normal fuse set is accessed, not the error cell in which the error occurs.

In the fuse set, a fuse guard ring 30 is formed around the fuse set to protect the fuse. The fuse and the fuse guard ring 30 are biased with different potentials during the repair process or while the memory device is operating. , The electric field is formed.

In general, when a fuse is applied with a ground power source or a power source voltage and blows during the repair process, one of the ground power source or the power source voltage is applied. In addition, since the guard ring is formed of a conductive film to prevent moisture penetration, etc., the guard ring is biased at a specific voltage.

If the fuse blows during the repair process, cracks are generated in the surrounding insulating layers, and the crack may cause damage to even the non-blowing fuses. It can also break.

However, an electric field is formed between the fuse and the guard ring. The electric field generated at this time causes electrolysis between the fuse guard ring and the fuse layer, and damages the surrounding fuse. The electrolysis phenomenon oxidizes the surrounding fuses through the aforementioned cracks.

The larger the electric field generated at this time, the greater the damage (oxidation of the fuse) to the surrounding fuses. In addition, when the conductor film used as the fuse is used as the capacitor plate electrode in the cell region, the fuse becomes a double structure of the polysilicon film / metal film, and the above-mentioned damage is further increased.

On the other hand, since the fuse set removes the interlayer insulating layer on the fuse with only a certain thickness for laser blowing, it is very vulnerable to moisture penetration.

Therefore, there is a need for a memory device capable of reducing the electric field between the guard ring and the fuse provided in the fuse set as much as possible.

An object of the present invention is to provide a memory device that can reduce the electric field between the guard ring and the fuse provided in the fuse set as much as possible.

1 is a cross-sectional view showing a fuse of a conventional semiconductor memory device.

Fig. 2 is a plan view showing a cell array of a conventional semiconductor memory device.

3 is a plan view of the fuse shown in FIG. 2; FIG.

Fig. 4 is a fuse set showing one of the sixteen normal fuse sets shown in Fig. 3;

5A through 5E are block diagrams illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

* Explanation of symbols on the main parts of the drawing

50: substrate 51: first fuse

52: first fuse guard ring 53a, 53b, 57: interlayer insulating film

54: contact plug for fuse 55: second fuse

56: second fuse guard ring

In order to achieve the above object, the present invention is formed by using a conductive impurity, forming a first fuse line and a second fuse line at regular intervals on a straight line on the substrate; Forming a first fuse guard ring formed at a predetermined interval on the first fuse line and the second fuse line, and intersecting with the first fuse line and the second fuse line, respectively, and forming a first fuse; ; Forming an interlayer insulating film to cover the first fuse guard ring; Forming first and second contact plugs formed through the interlayer insulating layer and formed inside and outside the first fuse guard ring, respectively, and connected to the first fuse line; penetrating the interlayer insulating layer to form the first and second contact plugs; Forming third and fourth contact plugs respectively formed at an inner side and an outer side of the fuse guard ring and connected to the second fuse line; first and second contact plugs formed at an inner side of the first fuse guard ring; Forming a second fuse line using a conductive material to connect the second fuse line; And forming a second fuse guard ring on the first fuse guard ring.

In another aspect, the present invention is the first fuse line and the second fuse line provided with a predetermined interval on a straight line on the substrate as a conductive impurity; A first fuse guard ring formed at regular intervals on the first fuse line and the second fuse line and intersecting the first fuse line and the second fuse line and provided in Peru; First and second contact plugs provided in inner and outer regions of the first fuse guard ring and connected to the first fuse lines, respectively; Third and fourth contact plugs provided in inner and outer regions of the first fuse guard ring and connected to the second fuse lines, respectively; A second fuse line formed of a conductive film and connected to the first and third contact plugs; And a second fuse guard ring provided on the first fuse guard ring.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. do.

5A through 5E are block diagrams illustrating a method of manufacturing a semiconductor memory device according to an exemplary embodiment of the present invention. For reference, in FIGS. 5A to 5E, the left side view is a sectional view of the fuse set according to the present embodiment, and the right side view is a plan view of the fuse set. In this embodiment, the conductive film for the bit line is used as a fuse, and the interlayer insulating film is not shown.

First, as illustrated in FIG. 5A, the semiconductor memory device according to the present exemplary embodiment forms the first fuse 51 using conductive impurities in a region where a fuse is to be formed on the substrate 50.

Subsequently, as shown in FIG. 5B, the interlayer insulating films 52a and 52b are formed, and the interlayer insulating film 52b is selectively removed to form a region where the guard ring is formed. Subsequently, the first fuse guard ring 52a is formed using the conductive film for the word line in the region where the interlayer insulating film 52b is removed.

Subsequently, as shown in FIG. 5C, the inner and outer interlayer insulating layers 51a and 51b of the first guard ring region 52 are selectively removed to form contact holes, and the contact holes are filled with a conductive material. A contact plug 54 for a fuse connected to the first fuse 51 is formed.

Subsequently, as illustrated in FIG. 5D, the conductive film is formed to connect the contact plug 54 to form the second fuse 55. Here, since the first and second fuses 51 and 55 form a constant space in both the inner region and the outer region of the first fuse guard ring 52 after the contact plug 54 is formed, the manufacture of the memory device is finished. In later operation, the electric field between the fuse and the guard ring is minimized.

Subsequently, as shown in FIG. 5E, the second fuse 55 may be covered by the interlayer insulating layer 57. Subsequently, the region in which the first guard ring 52 is located is exposed, and the conductive film is embedded in the exposed region to form the second guard ring 56. Here, reference numeral 57 denotes to remove a portion of the upper part of the fuse, leaving an interlayer insulating film in order to set the area to be irradiated with the laser during the repair process.

Therefore, according to the present invention, the fuse region except for the portion blown by the laser irradiation is formed in the lower portion of the fuse guard ring, so that a large space between the fuse guard ring and the fuse is formed, and the electric field between the fuse guard ring and the fuse is minimized. Therefore, there is no electrolysis between the fuse and the fuse guard ring, so the fuse is well protected.

As a result, since the fuse is not oxidized, the repair process can be performed reliably, thereby increasing the repair efficiency and improving the yield of the overall memory device manufacturing process.

As described above, when the fuse is formed using the conductive film for the bit line, the above process is performed. However, when the fuse is formed using the conductive film for the plate electrode of the capacitor, the fuse is formed inside and outside the fuse guard ring. What is necessary is just to form the contact plug which connects a fuse and a 2nd fuse longer.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

According to the present invention, the electric field between the fuse guard ring and the fuse can be reduced to the maximum, and damage due to cracks caused by the fuse blown onto the fuse during the repair process can be greatly reduced. Therefore, a more reliable repair process is possible, and thus, a yield improvement is expected in the manufacturing process of the memory device.

Claims (4)

Forming a first fuse line and a second fuse line at a predetermined interval on a straight line on the substrate by using conductive impurities; Forming a first fuse guard ring formed at a predetermined interval on the first fuse line and the second fuse line, and intersecting with the first fuse line and the second fuse line, respectively, and forming a first fuse; ; Forming an interlayer insulating film to cover the first fuse guard ring; Forming first and second contact plugs penetrating through the interlayer insulating layer and formed at inner and outer sides of the first fuse guard ring, respectively, and connected to the first fuse lines; Forming third and fourth contact plugs formed through the interlayer insulating layer and formed inside and outside the first fuse guard ring, respectively, and connected to the second fuse lines; Forming a second fuse line by using a conductive material to connect the first and second contact plugs formed inside the first fuse guard ring; And And forming a second fuse guard ring on the first fuse guard ring. The method of claim 1, The conductive impurity forming the first fuse line and the second fuse line uses a conductive impurity forming a source / drain region of a morph transistor of a cell region. The method of claim 1, The first fuse guard ring is A method of manufacturing a semiconductor memory device, comprising using a conductive material forming a word line of a MOS transistor in a cell region. A first fuse line and a second fuse line having conductive gaps in a straight line on the substrate with conductive impurities; A first fuse guard ring formed at regular intervals on the first fuse line and the second fuse line and intersecting the first fuse line and the second fuse line and provided in Peru; First and second contact plugs provided in inner and outer regions of the first fuse guard ring and connected to the first fuse lines, respectively; Third and fourth contact plugs provided in inner and outer regions of the first fuse guard ring and connected to the second fuse lines, respectively; A second fuse line formed of a conductive film and connected to the first and third contact plugs; And A second fuse guard ring provided on the first fuse guard ring; A semiconductor memory device having a.