KR20040090181A - Nickel salicide process and method of fabricating a MOS transistor using the same - Google Patents

Abstract

A nickel salicide process and a method of manufacturing a MOS transistor using the same are provided. The method includes forming a wiring layer doped with impurity ions in a predetermined region of the semiconductor substrate or on the predetermined region of the semiconductor substrate. A silicided blocking film exposing the wiring layer is formed on the semiconductor substrate. The semiconductor substrate having the silicided stop film is post-heated to activate impurity ions in the wiring layer. Subsequently, a nickel mono-silicide layer (NiSi layer) is selectively formed on the surface of the activated wiring layer. The nickel mono silicide film is formed at a low temperature of 400 ° C to 530 ° C. Accordingly, the resistance of the nickel silicide film on the wiring layer as well as the resistance of the wiring layer can be significantly reduced.

Description

Nickel salicide process and method of fabricating a MOS transistor using the same

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a nickel salicide process and a method of manufacturing a MOS transistor using the same.

Semiconductor devices are widely adopted as switching devices, such as discrete devices such as MOS transistors. As the degree of integration of the semiconductor device increases, the MOS transistor is gradually scaled down. As a result, the channel length of the MOS transistor is reduced to generate a short channel effect. The reduction in channel length leads to a narrow width of the gate electrode. Accordingly, the electrical resistance of the gate electrode is increased. In order to improve the short channel effect, it is required to reduce the thickness of the gate insulating layer as well as the junction depth of the source / drain regions of the MOS transistor. As a result, the gate capacitance C as well as the resistance R of the gate electrode increases. In this case, the transmission speed of the electrical signal applied to the gate electrode becomes slow due to the resistance-capacitance delay time.

In addition, the source / drain region has a shallow junction depth, so its sheet resistance increases. As a result, the drivability of the short channel MOS transistor is reduced. Accordingly, a salicide (self-aligned silicide) technology is widely used to realize a high performance MOS transistor suitable for the highly integrated semiconductor device.

The salicide technology is a process technology for lowering the electrical resistance of the gate electrode and the source / drain regions by selectively forming a metal silicide layer on the gate electrode and the source / drain regions. As the metal silicide film, a cobalt silicide film or a titanium silicide film is widely adopted. In particular, the resistance of the cobalt silicide film shows a very low dependency on the change in line width. Accordingly, a technique of forming a cobalt silicide film on the gate electrode of the short channel MOS transistor is widely used. However, when the width of the gate electrode is smaller than about 0.1 mu m, there is a limit to the application of the cobalt silicide film due to a phenomenon known as agglomeration. Accordingly, nickel salicide technology has recently been used in the manufacture of high performance MOS transistors.

A method of applying metal salicide technology to a MOS transistor is described in US Pat. No. 6,326,289 B1, "Method of forming a silicide layer using pre-amorphous implantation blocked from source / drain regions by a photoresist layer. silicide layer using a pre-amorphization implant which is blocked from source / drain regions by a layer of photoresist, as described by Rodder et al.

According to the loader or the like, gate electrodes and source / drain regions are formed on the semiconductor substrate, and a photoresist pattern selectively exposing only the gate electrode is formed. Subsequently, impurities are implanted into the surface of the exposed gate electrode using the photoresist pattern as an ion implantation mask. As a result, only the surface of the gate electrode is amorphous and no damage is done to the source / drain regions. A metal silicide layer is selectively formed on the amorphous gate electrode and the source / drain regions. Accordingly, even if the width of the gate electrode is narrow, it is possible to prevent the metal silicide film formed on the gate electrode from agglomerating. In addition, since the source / drain regions do not have any ion implantation damage, the junction leakage current characteristics of the source / drain regions may be prevented from deteriorating.

Nevertheless, research on nickel salicide technology is continuously required. This is because the nickel salicide technology is suitable for high performance MOS transistors of ultra-high density semiconductor devices. However, in the nickel salicide technology, the silicidation temperature and subsequent thermal process temperature for forming the nickel silicide film directly affect the phase transformation of the nickel silicide film. . Therefore, it is necessary to optimize the heat treatment process of the semiconductor device employing the nickel salicide technology.

In addition, when the metal salicide technology such as the nickel salicide technology is applied to the ultra-high density semiconductor device, the metal salicide technology is an input / output protection circuit such as an electro-static discharge circuit (ESD circuit). It is preferable not to apply to the (I / O protection circuit). This is because the metal salicide technology may cause an increase in junction leakage current of the input / output protection circuit and a decrease in resistance of gate electrodes and source / drain regions in the input / output protection circuit. The decrease in the resistance of the gate electrodes and the source / drain regions in the input / output protection circuit leads to the deterioration of the electrostatic discharge characteristic. As a result, the input / output protection circuit must be covered with a silicidation blocking layer before the metal salicide process. However, during the formation of the silicided stop layer, impurities in the source / drain regions and the gate electrode may be deactivated. In this case, the electrical characteristics of the MOS transistors constituting the internal circuit are degraded.

In conclusion, it is desired to optimize the salicide process for forming the nickel silicide film.

The technical problem to be achieved by the present invention is to provide a nickel salicide process that can reduce the deactivation of impurities in the silicon pattern or impurity layer as well as the resistivity of the nickel silicide film selectively formed on the silicon pattern or impurity layer. There is.

Another object of the present invention is to provide a method of manufacturing a MOS transistor which can obtain an improved electrical characteristic by using an optimized nickel salicide process.

1 is a process flowchart illustrating a manufacturing method of a MOS transistor according to an embodiment of the present invention.

2 to 8 are cross-sectional views illustrating a method of manufacturing a MOS transistor according to an embodiment of the present invention.

FIG. 9A is a graph showing threshold voltage characteristics of NMOS transistors fabricated using a typical cobalt salicide technique and threshold voltage characteristics of NMOS transistors fabricated using a conventional nickel salicide technique.

9B is a graph showing threshold voltage characteristics of PMOS transistors fabricated using a general cobalt salicide technique and threshold voltage characteristics of PMOS transistors fabricated using a conventional nickel salicide technique.

10A is a graph showing on / off current characteristics of NMOS transistors fabricated using a general cobalt salicide technique and on / off current characteristics of NMOS transistors fabricated using a conventional nickel salicide technique.

FIG. 10B is a graph showing on / off current characteristics of PMOS transistors fabricated using a general cobalt salicide technique and on / off current characteristics of PMOS transistors fabricated using a conventional nickel salicide technique.

FIG. 11A is a graph showing C-V characteristics of NMOS transistors fabricated using a general cobalt salicide technique and C-V characteristics of NMOS transistors fabricated using a conventional nickel salicide technique.

FIG. 11B is a graph showing C-V characteristics of PMOS transistors fabricated using a general cobalt salicide technique and C-V characteristics of PMOS transistors fabricated using a conventional nickel salicide technique.

12A is a graph showing resistance characteristics of source / drain regions of NMOS transistors formed in accordance with the prior art and resistance characteristics of source / drain regions of NMOS transistors formed in accordance with the present invention.

12B is a graph showing resistance characteristics of LED regions of NMOS transistors formed according to the related art and resistance regions of LED regions of NMOS transistors formed according to the present invention.

FIG. 13A is a graph illustrating threshold voltage characteristics of NMOS transistors fabricated using a general cobalt salicide technique and threshold voltage characteristics of NMOS transistors fabricated using a nickel salicide technique according to a modification of the present invention.

FIG. 13B is a graph showing threshold voltage characteristics of PMOS transistors fabricated using a general cobalt salicide technique and threshold voltage characteristics of PMOS transistors fabricated using a nickel salicide technique according to a modification of the present invention.

14A is a graph showing C-V characteristics of NMOS transistors fabricated using a general cobalt salicide technique and C-V characteristics of NMOS transistors fabricated using a nickel salicide technique according to a modification of the present invention.

FIG. 14B is a graph showing C-V characteristics of PMOS transistors fabricated using a general cobalt salicide technique and C-V characteristics of PMOS transistors fabricated using a nickel salicide technique according to a modification of the present invention.

15A is a graph showing on / off current characteristics of NMOS transistors fabricated using a general cobalt salicide technique and on / off current characteristics of NMOS transistors fabricated using a nickel salicide technique according to a modification of the present invention. .

15B is a graph showing on / off current characteristics of PMOS transistors fabricated using a general cobalt salicide technique and on / off current characteristics of PMOS transistors fabricated using a nickel salicide technique according to a modification of the present invention. .

16A is a graph showing C-V characteristics of NMOS transistors fabricated using the conventional nickel salicide technique and C-V characteristics of NMOS transistors fabricated using the nickel salicide technique according to the present invention.

16B is a graph showing C-V characteristics of PMOS transistors fabricated using the conventional nickel salicide technique and C-V characteristics of PMOS transistors fabricated using the nickel salicide technique according to the present invention.

17A is a graph showing on / off current characteristics of NMOS transistors fabricated using the conventional nickel salicide technique and on / off current characteristics of NMOS transistors fabricated using the nickel salicide technique according to the present invention.

17B is a graph showing on / off current characteristics of PMOS transistors fabricated using the conventional nickel salicide technique and on / off current characteristics of PMOS transistors fabricated using the nickel salicide technique according to the present invention.

In order to achieve the above technical problem, the present invention provides a novel nickel salicide process.

According to an aspect of the present invention, the nickel salicide process includes forming an impurity layer by implanting impurity ions into a predetermined region of a semiconductor substrate. A silicidation blocking layer pattern exposing the impurity layer is formed on the semiconductor substrate having the impurity layer. The semiconductor substrate having the silicided stop layer pattern is post-annealed to activate impurities in the impurity layer. Subsequently, a nickel silicide film is selectively formed on the surface of the activated impurity layer.

Before forming the silicided stop layer pattern, the semiconductor substrate having the impurity layer may be further pre-annealed. The pre-heat treatment step is carried out at a temperature of 830 ℃ to 1150 ℃. As a result, the impurities in the impurity layer are activated.

The silicided stop layer pattern may be formed of a silicon nitride layer. The silicon nitride film is generally formed at a temperature of 535 ° C to 825 ° C. The silicided stop layer pattern covers other impurity layers that do not require a salicide process. Even if the pre-heat treatment process is performed, most of the impurities in the impurity layer are deactivated while forming the silicided stopper film pattern. As a result, the resistance of the deactivated impurity layer is significantly increased.

The post-annealing process is preferably carried out at a temperature of 830 ℃ to 1150 ℃. The post heat treatment process reactivates the deactivated impurity layer to improve electrical characteristics of the impurity layer.

The nickel silicide layer may have various composition rates. For example, the nickel silicide layer may be a di-nickel mono-silicide layer (Ni).₂Si layer, nickel mono-silicide layer (NiSi layer) or nickel di-silicide layer (NiSi)₂ layer). Of these nickel silicide films, the nickel mono silicide film (NiSi layer) has the lowest resistivity. However, the nickel monosilicide layer (NiSi layer) is formed at a low temperature of 400 ° C to 530 ° C, while the nickel disilicide layer (NiSi)₂layer) is formed at temperatures higher than 550 ° C. Therefore, in order to form a low resistive nickel silicide film, the process of forming the nickel silicide film and subsequent steps thereof must be performed at a temperature lower than 550 ° C.

According to another aspect of the present invention, the nickel salicide process includes forming a silicon pattern doped with impurity ions on a semiconductor substrate. A silicided blocking layer pattern exposing the doped silicon pattern is formed on the semiconductor substrate having the doped silicon pattern. The semiconductor substrate having the silicided stop layer pattern is post-annealed to activate impurities in the doped silicon pattern. A nickel silicide layer is selectively formed on the surface of the activated silicon pattern.

Before forming the silicided stop layer pattern, the semiconductor substrate having the doped silicon pattern may be further pre-annealed. The pre-heat treatment step is carried out at a temperature of 830 ℃ to 1150 ℃. As a result, impurities in the doped silicon pattern are activated.

The silicided stop layer pattern may be formed of a silicon nitride layer. The silicon nitride film is generally formed at a temperature of 535 ° C to 825 ° C. As a result, the doped silicon pattern is deactivated.

The post-annealing process is preferably carried out at a temperature of 830 ℃ to 1150 ℃. The post heat treatment process reactivates the deactivated impurity layer to improve electrical characteristics of the impurity layer.

The nickel silicide film is formed at a low temperature of 400 ° C to 530 ° C.

In order to achieve the above another technical problem, the present invention provides a method of manufacturing a MOS transistor using a nickel salicide process. This method includes forming a gate insulating film on a semiconductor substrate. A gate pattern, that is, a gate electrode is formed on a predetermined region of the gate insulating film. An insulating spacer is formed on sidewalls of the gate pattern. Source / drain regions are formed by implanting impurity ions into the semiconductor substrate using the gate pattern and the spacer as an ion implantation mask. A silicided stop layer pattern exposing the gate pattern and the source / drain regions is formed on the semiconductor substrate having the source / drain regions. Subsequently, the semiconductor substrate having the silicided stop layer pattern is post-heated to activate impurities in the gate pattern and the source / drain regions. A nickel silicide layer is selectively formed on the surface of the activated gate pattern and the surfaces of the activated source / drain regions.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout.

1 is a process flow chart illustrating a method of manufacturing MOS transistors according to embodiments of the present invention, and FIGS. 2 to 7 illustrate a method of manufacturing MOS transistors according to embodiments of the present invention. Sections for doing so.

1 and 2, an isolation region 53 is formed in a predetermined region of the semiconductor substrate 51 to define an active region. A gate insulating layer 55 is formed on the active region. A gate conductive layer is formed on the entire surface of the semiconductor substrate having the gate insulating film 55. The gate conductive layer may be formed of a silicon layer doped with N type impurities or P type impurities. More specifically, the gate conductive film may be formed of an N-type doped polysilicon film or a P-type doped polysilicon film. In order to form an NMOS transistor, the gate conductive film is preferably formed of an N-type doped silicon film, and in order to form a PMOS transistor, the gate conductive film is preferably formed of a P-type doped silicon film.

The gate conductive layer is patterned to form a gate pattern 57, that is, a gate electrode on a predetermined region of the gate insulating layer (step 1 of FIG. 1). The gate pattern 57 is formed to cross the upper portion of the active region. Lightly doped drain regions 59 are formed by implanting first impurity ions into the active region using the gate pattern 57 and the device isolation layer 53 as ion implantation masks (step of FIG. 1). 3). The first impurity ions may be N-type impurity ions or P-type impurity ions. Specifically, the N-type impurity ions are arsenic ions or phosphorus ions, and the P-type impurity ions are boron ions or boron fluoride (BF ₂ ) ions.

1 and 3, an insulating spacer layer is formed on the entire surface of the semiconductor substrate having the LDD regions 59. The spacer film is preferably formed by stacking a silicon oxide film 61 and a silicon nitride film 63 in sequence. The process of forming the silicon oxide film 61 may be omitted.

1 and 4, the spacer layer is anisotropically etched to form an insulating spacer 64 on the sidewall of the gate pattern 57, that is, the silicon pattern (step 5 of FIG. 1). As a result, the spacer 64 includes a silicon oxide film spacer 61a and a silicon nitride film spacer 63a. However, when the process of forming the silicon oxide film 61 is omitted, the spacer 64 is composed of only the silicon nitride film spacer 63a. Subsequently, source / drain regions 65 may be formed by implanting second impurity ions into the active region using the gate pattern 57, the spacer 64, and the device isolation layer 53 as ion implantation masks ( Step 7 of FIG. 1). As a result, the LDD regions 59 remain under the spacer 64. The second impurity ions may also be N-type impurity ions or P-type impurity ions. As-implanted impurity ions immediately after the ion implantation process are positioned between the gate pattern 57 and silicon atoms in the active region, i.e., interstitial lattice sites. Located in These interstitial impurity ions do not serve as donors that provide free electrons or acceptors that provide holes. That is, impurity ions immediately after the ion implantation process are in deactivated states. Accordingly, as-implanted source / drain regions 65 immediately after the ion implantation process do not have metallurgical junctions and exhibit high electrical resistance.

Subsequently, the semiconductor substrate into which the second impurity ions are implanted is pre-annealed to activate impurities in the source / drain regions 65 and the gate pattern 57 (step 9 of FIG. 1). . The pre-heat treatment step may be omitted. The pre-heat treatment step is preferably carried out using a rapid heat treatment process at a temperature of 830 ℃ to 1150 ℃. In addition, the said pre-heat processing process can be performed using nitrogen gas as an atmospheric gas. During the pretreatment process, most of the interstitial impurity ions are swamped into substitutional lattice sites. Accordingly, the activated impurity ions act as donors or acceptors to reduce the electrical resistance of the source / drain regions 65.

1 and 5, a silicidation blocking layer (SBL) is formed on a semiconductor substrate on which the source / drain ion implantation process or the pre-heat treatment process is performed. It is preferable that the silicide formation stop film is formed by stacking a silicon oxide film and a silicon nitride film in order. However, the silicided stop film may be formed only of the silicon nitride film. In general, the silicided stop film is formed using a chemical vapor deposition (CVD) technique at a temperature of 535 ℃ to 825 ℃. For example, the CVD silicon nitride film may be formed at a temperature of about 700 ° C.

On the other hand, most of the dopants (impurity ions) have the property of easily inactivated within the temperature range of 535 ℃ to 825 ℃. Accordingly, the impurities in the gate pattern 57, the LDD regions 59, and the source / drain regions 65 are deactivated while the silicided stop layer is formed. The deactivated LDD regions 59a, the deactivated gate pattern 57a, and the deactivated source / drain regions 65a have a high resistance. In addition, the deactivated source / drain regions 65a exhibit a large junction leakage current. In addition, a depletion capacitor connected in series with the gate capacitor resulting from the gate insulating layer 55 due to depleted impurities in the deactivated gate pattern 57a adjacent to the gate insulating layer 55 is removed. Generate. As a result, the total gate capacitance is reduced. This reduction in gate capacitance results in an increase in the equivalent thickness of the gate insulating film.

Subsequently, the silicided stop layer is patterned to form a silicided stop layer pattern 70 exposing the gate pattern 57a and the source / drain regions 65a (step 11 of FIG. 1). As a result, the silicided stop layer pattern 70 includes a silicon oxide layer pattern 67 and a silicon nitride layer pattern 69 that are sequentially stacked. The silicided stop layer pattern 70 may be formed of only the silicon nitride layer pattern 69. The silicided blocking layer pattern 70 is formed to cover an input / output protection circuit (not shown). Accordingly, the active region shown in FIG. 5 corresponds to a region in which a MOS transistor of an internal circuit is formed.

1 and 6, the semiconductor substrate having the silicided stop layer pattern 70 is post-annealed to form the gate pattern 57a, LDD regions 59a, and source / drain regions. The impurities in 65a are reactivated (step 13 of FIG. 1). Accordingly, the depletion capacitor is removed and a reactivated gate pattern 57b is formed. In addition, the source / drain regions 65a and the LDD regions 59a are converted and reduced into reactivated source / drain regions 65b and reactivated LDD regions 59b. Has a reduced resistance. The post-heating process (poat-annealing process) is preferably carried out using a rapid heat treatment technique at a temperature of 830 ℃ to 1150 ℃. In addition, the said post-heat treatment process can be performed using nitrogen gas as an atmospheric gas.

1, 7 and 8, a metal salicide technique, that is, a nickel salicide technique, is applied to a semiconductor substrate on which the post-heat treatment process is completed (step 15 of FIG. 1). More specifically, a native oxide film remaining on the surface of the reactivated gate pattern 57b and the reactivated source / drain regions 65b by cleaning the surface of the semiconductor substrate on which the post-heat treatment process is completed. oxide layer and contaminated particles are removed. The nickel film 71 is formed on the entire surface of the cleaned semiconductor substrate. The nickel film 71 is formed of a pure nickel layer or a nickel alloy layer. The nickel alloy film has tantalum (Ta), zirconium (Zr), titanium (Ti), hafnium (Hf), tungsten (W), cobalt (Co), and platinum (Pt) having a mixing ratio of 20 atom% or less. ), Palladium (Pd), vanadium (V), niobium (Nb) or combinations thereof. In particular, when the nickel alloy film contains tantalum, the tantalum improves thermal stability of nickel mono silicide films formed in subsequent processes.

Subsequently, the semiconductor substrate having the nickel film 71 is heat-treated at a low temperature of 400 ° C to 530 ° C. As a result, the nickel layer 71 reacts with the silicon atoms of the gate pattern 57b and the silicon atoms of the source / drain regions 65b to react with the gate pattern 57b and the source / drain regions. First and second nickel mono silicide films (NiSi layers) 71a and 71b are selectively formed on the surfaces of 65b, respectively.

When the heat treatment temperature is higher than 550 ° C., a nickel die silicide layer (NiSi ₂ layer) having a higher resistance than the nickel mono silicide layer is formed instead of the nickel mono silicide layers. Accordingly, the heat treatment temperature, that is, the silicidation temperature (silicidation temperature) is preferably a low temperature of 400 ℃ to 530 ℃. Next, an unreacted nickel layer on the spacer 64, the device isolation layer 53, and the silicided stop layer pattern 70 is removed to form the first nickel monosilicide layer 71a. It is electrically disconnected from the 2 nickel mono silicide film 71b. The unreacted nickel film may be removed using a mixture of sulfuric acid solution (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ).

Subsequently, an interlayer insulating film 73 is formed on the entire surface of the semiconductor substrate where the nickel salicide process is completed. The interlayer insulating film 73 is preferably formed at a temperature lower than 550 ° C. This is to suppress phase transformation of the nickel mono silicide layers 71a and 71b.

Experimental Examples; examples>

Hereinafter, various measurement results of samples manufactured according to the above-described embodiments will be described.

9A-11A are graphs showing the electrical properties of NMOS transistors fabricated using conventional nickel salicide technology and typical cobalt salicide technology, and FIGS. 9B-11B are conventional nickel sally. Graphs showing the electrical characteristics of PMOS transistors fabricated using side technology and typical cobalt salicide technology. More specifically, FIGS. 9A and 9B are graphs showing threshold voltage characteristics of NMOS transistors and graphs showing threshold voltage characteristics of PMOS transistors, respectively. In the drawings of FIGS. 9A and 9B, abscissas represent channel lengths L _ch and ordinates represent threshold voltages V _th . In this case, the channel length L _ch corresponds to the width of the gate electrode.

Also, FIG. 10A is a graph showing on / off current characteristics (ie, correlation of on current and off current) of NMOS transistors having various channel lengths, and FIG. 10B is a PMOS transistor having various channel lengths. These graphs show their on / off current characteristics. The channel widths of the NMOS transistors and PMOS transistors were 10 μm. In the figures of FIGS. 10A and 10B, abscissas represent per unit channel width drain saturation current (Idsat), and ordinates represent drain off per unit channel width. Indicates a drain off current (Idoff). In this case, the drain saturation current Idsat grounds the source region and the bulk region and applies a voltage Vdd (+1 volt for NMOS transistors and -1 volt for PMOS transistors) to the drain region and the gate electrode. It is a current flowing through the drain region. In addition, the drain off current Idoff grounds the source region, the bulk region, and the gate electrode, and applies the voltage Vdd (+1 volt for NMOS transistors and -1 volt for PMOS transistors) to the drain region. In one case, the current flows through the drain region.

In addition, FIGS. 11A and 11B are the CV-capacitance-voltage plot of the NMOS transistor and the CV plot of the PMOS transistor, respectively. The CV plots were measured at a high frequency of 100 Hz. In this case, the NMOS transistors and the PMOS transistors were formed to have a channel area (gate area) of 50 × 50 μm ² . In addition, in the drawings of FIGS. 11A and 11B, the horizontal axes represent the gate voltage V _G and the vertical axes represent the gate capacitance C. In FIG. At this time, the source region and the drain region were grounded together with the bulk region. In this case, even when a gate voltage of an inversion mode is applied to the gate electrode, the majority carriers in the source region and the drain region are sufficiently supplied to the channel region to deplete the channel region. Prevents the formation of depletion regions. Accordingly, the CV plots exhibit the same characteristics as the CV plots measured at low frequencies.

Meanwhile, NMOS transistors showing the measurement results of FIGS. 9A to 11A were manufactured using key process conditions described in Table 1 below.

Process parameters NiSi Sample CoSi ₂ Sample Gate insulating film Silicon Oxynitite Film (SiON), 16Å 2. Gate pattern N-type polysilicon film 3. LDD ion implantation Arsenic, 2.5 × 10 ¹⁴ atoms / ㎠, 5KeV 4. S / D ion implantation Arsenic, 5 × 10 ¹⁵ atoms / ㎠, 40KeV 5. Pre-heat Treatment 1050 ° C, nitrogen atmosphere, rapid heat treatment (RTP) 6. Silicided Stop Film Silicon Nitride Film (SiN), 500Å, 700 ℃ (LPCVD) 7. Salicide process (silicidation heat treatment) 450 ℃ First Heat Treatment (450 ℃) Second Heat Treatment (830 ℃)

In addition, PMOS transistors showing the measurement results of FIGS. 9B to 11B were fabricated using the main process conditions described in Table 2 below.

Process parameters NiSi Sample CoSi ₂ Sample Gate insulating film Silicon Oxynitite Film (SiON), 16Å 2. Gate pattern P-type polysilicon film 3. LDD ion implantation Boron, 2 × 10 ¹⁴ atoms / ㎠, 0.6KeV 4. S / D ion implantation Boron, 3 × 10 ¹⁵ atoms / ㎠, 3KeV 5. Pre-heat Treatment 1050 ° C, nitrogen atmosphere, rapid heat treatment (RTP) 6. Silicided Stop Film Silicon Nitride Film (SiN), 500Å, 700 ℃ (LPCVD) 7. Salicide process (silicidation heat treatment) 450 ℃ First Heat Treatment (450 ℃) Second Heat Treatment (830 ℃)

9A and 9B, NMOS transistors fabricated using nickel salicide technology showed relatively high threshold voltages V _th compared to NMOS transistors fabricated using cobalt salicide technology. Similarly, PMOS transistors fabricated using the nickel salicide technique showed relatively higher threshold voltages than PMOS transistors fabricated using the cobalt salicide technique. As a result, the formation process of the cobalt silicide layer removes the depletion regions generated in the gate patterns while the silicide formation stop layer is formed, while the formation process of the nickel silicide layer is performed while the silicide formation stop layer is formed. It may be understood that the depletion regions generated in the gate patterns may not be removed. This is because the heat treatment temperature for forming the cobalt silicide film is higher than the heat treatment temperature for forming the nickel silicide film in the gate patterns. Nevertheless, it is not preferable to form the nickel silicide film at a temperature higher than 825 占 폚. This is because when the nickel silicide film is formed at a temperature higher than about 550 ° C., a phase transformation of the nickel silicide film occurs to increase its resistance.

10A and 10B, the drain saturation current Idsat of NMOS transistors employing nickel salicide technology is smaller than the drain saturation current Idsat of NMOS transistors employing cobalt salicide technology. For example, in NMOS transistors, when the drain off current (Idoff) was 10 mA / µm, the nickel salicide samples showed a drain saturation current (Idsat) of about 500 mA / µm and the cobalt salicide samples were about. A drain saturation current (Idsat) of 540 mA / µm was shown. This is because the nickel salicide samples have N-type source / drain regions deactivated while the cobalt salicide samples have N-type source / drain regions activated during the cobalt silicideation process. .

In contrast, the drain saturation current Idsat of the PMOS transistors employing the nickel salicide technology has a larger value than the drain saturation current Idsat of the PMOS transistors employing the cobalt salicide technology. For example, in PMOS transistors, when the drain off current (Idoff) was 1 mA / µm, the nickel salicide samples showed a drain saturation current (Idsat) of about 185 mA / µm and the cobalt salicide samples were about. A drain saturation current (Idsat) of 175 mA / µm was shown. This is because the contact resistance between the nickel silicide film and the P-type source / drain regions is smaller than the contact resistance between the cobalt silicide film and the P-type source / drain regions.

11A and 11B, in the accumulation mode of the NMOS transistor and the PMOS transistor, the nickel salicide samples showed the same gate capacitance as the cobalt salicide samples. However, in the inversion mode of the NMOS transistor, the gate capacitance of the nickel salicide samples was lower than the gate capacitance of the cobalt salicide samples (see region "A" in FIG. 11A). Likewise, in the inversion mode of the PMOS transistor, the gate capacitance of the nickel salicide samples was lower than the gate capacitance of the cobalt salicide samples (see region “A” in FIG. 11B). It may be understood that impurity depletion regions existed during the formation of the silicided stop layer in the gate patterns of the nickel salicide samples.

More specifically, an electron depletion layer is formed in the N-type gate pattern of the NMOS transistor due to deactivation of impurities while the silicide stop layer is formed. In the case of the nickel salicide samples, the electron depletion layer still remains after forming the nickel silicide film. In contrast, in the case of the cobalt salicide samples, the width of the electron depletion layer is reduced during formation of the cobalt silicide film. Nevertheless, in the accumulation mode, the NMOS transistor employing the nickel salicide technology exhibited the same gate capacitance as the NMOS transistor employing the cobalt salicide technology. This is because a negative gate voltage is applied to the gate pattern of the NMOS transistor. In other words, since a sufficient amount of electrons are supplied into the gate pattern of the NMOS transistor, the electron depletion layer is removed.

Meanwhile, in the inversion mode, a positive gate voltage is applied to the gate pattern of the NMOS transistor. Accordingly, the electron depletion layer formed in the N-type gate pattern of the nickel salicide samples still remains. As a result, the nickel salicide sample may be interpreted to have a relatively low gate capacitance as compared to the cobalt salicide sample.

It will be apparent to those skilled in the art that the C-V plot of the PMOS transistors shown in FIG. 11B can also be interpreted on the same principle as the description of the C-V plots of the NMOS transistors.

FIG. 12A is a graph showing resistance characteristics of source / drain regions of the NMOS transistors described in FIGS. 9A through 11A and source / drain regions of NMOS transistors manufactured according to an exemplary embodiment of the present invention, and FIG. 9A to 11A are graphs showing the resistance characteristics of the LED regions of the NMOS transistors and the LED regions of the NMOS transistor fabricated according to the preferred embodiment of the present invention. In the drawings of Figure 12a and 12b, the horizontal axis are the sheet resistance; represents (R _S resistance sheet), and the vertical axis represent the accumulation distribution ratio (cummulative distribution rate). Here, sheet resistances of the source / drain regions and LDD regions were measured before the salicide process. In addition, NMOS transistors according to a preferred embodiment of the present invention were fabricated using the main process conditions described in Table 3 below.

Process parameters NMOS transistor Gate insulating film Silicon Oxynitite Film (SiON), 16Å 2. Gate pattern N-type polysilicon film 3. LDD ion implantation Arsenic, 2.5 × 10 ¹⁴ atoms / ㎠, 5KeV 4. S / D ion implantation Arsenic, 5 × 10 ¹⁵ atoms / ㎠, 40KeV 5. Silicided Stop Film Silicon Nitride Film (SiN), 500Å, 700 ℃ (LPCVD) 6. After heat treatment 1050 ° C, nitrogen atmosphere, rapid heat treatment (RTP)

As can be seen from Table 3, according to a preferred embodiment of the present invention, no heat treatment process was applied before forming the silicided stopper film. Instead, a post-anneling process was performed after the silicided stop film was formed. As a result, the N-type source / drain regions of the NMOS transistors according to the preferred embodiment of the present invention exhibited sheet resistance of 100 Ω / square to 125 Ω / square as shown in FIG. 12A. However, the N-type source / drain regions of the NMOS transistors described in FIGS. 9A through 11A exhibited sheet resistances of 175 Ω / square to 210 Ω / square.

In addition, the N-type LDD regions of the NMOS transistors according to the preferred embodiment of the present invention exhibited sheet resistance of 200 Ω / square to 210 Ω / square as shown in FIG. 12B. However, the N-type LDD regions of the NMOS transistors described in FIGS. 9A to 11A exhibited sheet resistances of 360 Ω / square to 380 Ω / square.

As a result, it may be understood that the N-type source / drain regions and the N-type LDD regions are reactivated when the post-heat treatment process is performed after the silicided stop film is formed.

13B to 15B together with FIGS. 13A to 15A are graphs showing measurement results for directly determining the influence of the process of forming the silicided stopper film.

13A-15A are graphs showing electrical characteristics of NMOS transistors employing nickel salicide technology and cobalt salicide technology, and FIGS. 13B-15B are PMOS employing the nickel salicide technology and the cobalt salicide technology. These graphs show the electrical characteristics of the transistors. Specifically, FIGS. 13A and 13B are graphs showing threshold voltage characteristics of NMOS transistors and graphs showing threshold voltage characteristics of PMOS transistors, respectively. In the drawings of FIGS. 13A and 13B, abscissas represent channel lengths L _ch and ordinates represent threshold voltages V _th . In this case, the channel length L _ch corresponds to the width of the gate electrode.

14A and 14B are CV plots of NMOS transistors and CV plots of PMOS transistors, respectively. The CV plots were measured at a high frequency of 100 Hz as described in FIGS. 11A and 11B. In addition, the NMOS transistors and the PMOS transistors are formed to have a channel area (gate area) of 50 × 50 μm ² . In the figures of FIGS. 11A and 11B, the horizontal axes represent the gate voltage V _G , and the vertical axes represent the gate capacitance C. In FIG. At this time, the source region and the drain region are grounded together with the bulk region as described with reference to FIGS. 11A and 11B.

In addition, FIG. 15A is a graph showing on / off current characteristics of NMOS transistors having various channel lengths, and FIG. 15B is a graph showing on / off current characteristics of PMOS transistors having various channel lengths. In the figures of FIGS. 15A and 15B, abscissas represent per unit channel width drain saturation current (Idsat), and ordinates represent drain off per unit channel width. Indicates a drain off current (Idoff). Here, the drain saturation current Idsat and drain off current Idoff were measured using the same bias conditions as in FIGS. 10A and 10B.

NMOS transistors showing the measurement results of FIGS. 13A to 15A were fabricated using the main process conditions described in Table 4 below.

Process parameters NiSi Sample CoSi ₂ Sample Gate insulating film Silicon Oxynitite Film (SiON), 16Å 2. Gate pattern N-type polysilicon film 3. LDD ion implantation Arsenic, 2.5 × 10 ¹⁴ atoms / ㎠, 5KeV 4. S / D ion implantation Arsenic, 5 × 10 ¹⁵ atoms / ㎠, 40KeV 5. Pre-heat Treatment 1050 ° C, nitrogen atmosphere, rapid heat treatment (RTP) 6. Silicided Stop Film Skipped 7. Salicide process (silicidation heat treatment) 450 ℃ First Heat Treatment (450 ℃) Second Heat Treatment (830 ℃)

In addition, PMOS transistors showing the measurement results of FIGS. 13B to 15B were fabricated using the main process conditions described in Table 5 below.

Process parameters NiSi Sample CoSi ₂ Sample Gate insulating film Silicon Oxynitite Film (SiON), 16Å 2. Gate pattern P-type polysilicon film 3. LDD ion implantation Boron, 2 × 10 ¹⁴ atoms / ㎠, 0.6KeV 4. S / D ion implantation Boron, 3 × 10 ¹⁵ atoms / ㎠, 3KeV 5. Pre-heat Treatment 1050 ° C, nitrogen atmosphere, rapid heat treatment (RTP) 6. Silicided Stop Film Skipped 7. Salicide process (silicidation heat treatment) 450 ℃ First Heat Treatment (450 ℃) Second Heat Treatment (830 ℃)

13A and 13B, when omitting the formation of the silicide blocking layer, MOS transistors employing nickel salicide technology exhibited the same threshold voltage characteristics as that of MOS transistors employing cobalt salicide technology. As a result, it can be understood that the process of forming the silicided stop film serves as a factor for lowering the threshold voltage characteristic of the MOS transistors employing the nickel salicide technology.

14A and 14B, in both NMOS transistors and PMOS transistors, nickel salicide samples showed the same C-V characteristics as cobalt salicide samples. Therefore, it can be understood that these C-V properties are also affected by the process of forming the silicided stop film.

15A and 15B, NMOS transistors fabricated using nickel salicide technology exhibited the same on / off current characteristics as NMOS transistors fabricated using cobalt salicide technology. As a result, the N-type source / drain regions of the nickel salicide samples may be interpreted to have the same resistance as the N-type source / drain regions of the cobalt salicide samples. In other words, when the silicided stop film is not formed, it may be understood that the N-type source / drain regions of the nickel salicide samples maintain an activated state.

On the other hand, in the PMOS transistors, the on / off current characteristics of the nickel salicide samples were superior to the on / off current characteristics of the cobalt salicide samples. For example, when the drain off current (Idoff) was 10 mA / µm, the nickel salicide samples showed a drain saturation current (Idsat) of about 220 mA / µm and the cobalt salicide samples had a drain saturation of about 185 mA / µm. The current Idsat was shown. That is, the drain saturation current of the nickel salicide samples was increased by about 19% compared to the drain saturation current of the cobalt salicide samples. As a result, the on / off current characteristics of the nickel salicide samples shown in FIG. 15B are significantly improved compared to the on / off current characteristics of the nickel salicide samples shown in FIG. 10B. This is because the P-type gate electrode and the P-type source / drain regions of the nickel salicide samples remain activated when the silicide formation stop film is omitted. Specifically, the improvement of the on / off current characteristics is due to the fact that the impurity depletion layer in the activated P-type gate electrode is narrower than the impurity depletion layer in the inactivated P-type gate electrode. Accordingly, the on current of the MOS transistor having the activated P-type gate electrode is greater than that of the MOS transistor having the deactivated P-type gate electrode. In addition, the improvement of the on / off current characteristics may be achieved by the P-type source / drain regions in which contact resistance between the activated P-type source / drain regions and the nickel silicide layer thereon is inactivated and the nickel silicide layer thereon. This is due to the fact that it is significantly smaller than the contact resistance between.

16A and 17A are graphs showing electrical characteristics of NMOS transistors fabricated using nickel salicide technology, and FIGS. 16B and 17B are diagrams showing electrical characteristics of PMOS transistors fabricated using nickel salicide technology. It is a graph. Specifically, FIGS. 16A and 16B are CV plots of NMOS transistors and CV plots of PMOS transistors, respectively. The CV plots were measured under the same conditions as described in FIGS. 11A and 11B. In this case, the NMOS transistors and the PMOS transistors were also formed to have a channel area (gate area) of 50 × 50 μm ² . 17A and 17B are graphs showing on / off current characteristics of NMOS transistors and on / off current characteristics of PMOS transistors, respectively. The data shown in FIGS. 17A and 17B were measured under the same bias conditions as described in FIGS. 10A and 10B.

The gate insulating films of the NMOS transistors and the PMOS transistors are formed of a silicon oxynitride film having a thickness of 14 占 퐉. In addition, the gate patterns, the LDD regions, the source / drain regions, the silicided stop layers, and the silicide layers of the MOS transistors were formed using the same process conditions as those described in [Table 1] and [Table 2].

In the drawings of FIGS. 16A and 16B, data denoted by “○” are measurement results of samples subjected to a post-heat treatment process after forming a silicidation blocking layer (SBL). ), And the data denoted by "Δ" show measurement results of samples that adopt the pre-heat treatment process after the source / drain ion implantation process and exclude the formation of the silicided stopper film and the post-heat treatment process. In addition, the data indicated by " □ " represent measurement results of samples that adopted the pre-heat treatment step and exclude the post-heat treatment step before forming the silicided stopper film.

In the drawings of FIGS. 17A and 17B, data denoted by "Δ" represent measurement results of samples to which a post-heat treatment process is applied after forming a silicidation blocking layer (SBL) and refer to it. The data indicated by the symbol " □ " represent measurement results of samples that adopt the pre-heat treatment process after the source / drain ion implantation process and exclude the formation process of the silicided blocking film SBL and the post-heat treatment process. In addition, the data denoted by "i" represent the measurement results of the samples adopting the pre-heat treatment process and excluding the post-heat treatment process before forming the silicided blocking film SBL.

The pre-heat treatment step and the post-heat treatment step were carried out using a rapid heat treatment technique at a temperature of 1050 ℃. At this time, nitrogen gas was used as the atmosphere gas.

16A and 16B, when the pre-heat treatment process was performed and the post-heat treatment process was omitted, the gate capacitance in the inversion mode of the NMOS transistor was about 33 kW. In contrast, when the post-heat treatment step or the formation of the silicided stop film was omitted, the gate capacitance in the inversion mode of the NMOS transistor was about 36 kW.

Further, when the pre-heat treatment step was performed and the post-heat treatment step was omitted, the gate capacitance in the inversion mode of the PMOS transistor was about 30 kW. In contrast, when the post-heat treatment step or the silicide formation stop film formation step was omitted, the gate capacitance in the inversion mode of the PMOS transistor was about 33 kW.

In conclusion, the post-heat treatment process may be understood to improve C-V characteristics of the NMOS transistors and the PMOS transistors.

Referring to FIGS. 17A and 17B, on / off current characteristics of MOS transistors employing the post-heat treatment process or excluding the formation of the silicided stoppage film may include the pre-heat treatment process. The on / off current characteristics of MOS transistors excluding the heat treatment process are improved. For example, when the drain off current Idoff of the NMOS transistors is 10 mA / m, the drain saturation current of the NMOS transistors employing the post-heat treatment process or excluding the formation of the silicided stop film. (Idsat) was about 590 mA / μm, and the drain saturation current (Idsat) of the NMOS transistors adopting the pre-heat treatment process and excluding the post-heat treatment process was about 550 mA / μm. In addition, when the drain off current Idoff of the PMOS transistors is 10 ㎁ / µm, the drain saturation current Idsat of the PMOS transistors employing the post-heat treatment process or excluding the formation of the silicided stop layer is excluded. ) Was about 300 mA / μm and the drain saturation current (Idsat) of the PMOS transistors adopting the pre-annealed process and excluding the post-heat treatment process was about 270 mA / μm.

In conclusion, the post-heat treatment process may be understood to improve on / off current characteristics of the NMOS transistors and the PMOS transistors.

As described above, according to the present invention, high-performance MOS transistors having stable electrical characteristics may be implemented when heat-treating a semiconductor substrate having a silicided stop film before a nickel salicide process.

Claims (32)

Impurity ions are implanted into a predetermined region of the semiconductor substrate to form an impurity layer, Forming a silicidation blocking layer pattern exposing the impurity layer on the semiconductor substrate having the impurity layer, Post-annealing the semiconductor substrate having the silicided stop layer pattern to activate impurities in the impurity layer, Nickel salicide process comprising selectively forming a nickel silicide film on the surface of the activated impurity layer. The method of claim 1, And the impurity ions are N-type impurity ions or P-type impurity ions. The method of claim 1, And prior to forming the silicided stop layer pattern, pre-annealing the semiconductor substrate including the impurity layer to activate impurities in the impurity layer. The method of claim 3, wherein The pre-heat treatment step is nickel salicide process, characterized in that carried out at a temperature of 830 ℃ to 1150 ℃. The method of claim 4, wherein The pre-heat treatment step is a nickel salicide process, characterized in that carried out using nitrogen gas as an ambient gas (ambient gas). The method of claim 5, wherein The pre-heat treatment step is a nickel salicide process, characterized in that carried out using a rapid heat treatment process. The method of claim 1, The silicided blocking layer pattern (silicidation blocking layer pattern) is a nickel salicide process, characterized in that the silicon nitride film formed at a temperature of 535 ℃ to 825 ℃. The method of claim 1, Nickel salicide process, characterized in that the post-heat treatment step is carried out at a temperature of 830 ℃ to 1150 ℃. The method of claim 8, The post-heat treatment process is a nickel salicide process, characterized in that carried out using nitrogen gas as an ambient gas (ambient gas). Forming a silicon pattern doped with impurity ions on the semiconductor substrate, Forming a silicidation blocking layer pattern exposing the doped silicon pattern on the semiconductor substrate having the doped silicon pattern; Post-annealing the semiconductor substrate having the silicided stop layer pattern to activate impurities in the doped silicon pattern, Nickel salicide process comprising selectively forming a nickel silicide film on the surface of the activated silicon pattern. The method of claim 10, Nickel salicide process, characterized in that the silicon pattern is formed of a polysilicon film. The method of claim 10, And the impurity ions are N-type impurity ions or P-type impurity ions. The method of claim 10, And prior to forming the silicided stop layer pattern, pre-annealing the semiconductor substrate including the doped silicon pattern to activate impurities in the doped silicon pattern. Side process. The method of claim 13, The pre-heat treatment step is nickel salicide process, characterized in that carried out at a temperature of 830 ℃ to 1150 ℃. The method of claim 14, The pre-heat treatment step is a nickel salicide process, characterized in that carried out using nitrogen gas as the atmosphere gas. The method of claim 15, The pre-heat treatment step is a nickel salicide process, characterized in that carried out using a rapid heat treatment process. The method of claim 10, The silicided blocking layer pattern (silicidation blocking layer pattern) is a nickel salicide process, characterized in that the silicon nitride film formed at a temperature of 535 ℃ to 825 ℃. The method of claim 10, Nickel salicide process, characterized in that the post-heat treatment step is carried out at a temperature of 830 ℃ to 1150 ℃. The method of claim 18, The post-heat treatment step is a nickel salicide process, characterized in that carried out using nitrogen gas as the atmosphere gas. Forming a gate insulating film on the semiconductor substrate, Forming a gate pattern on a predetermined region of the gate insulating film, Forming an insulating spacer on the sidewall of the gate pattern, Source / drain regions are formed by implanting impurity ions into the semiconductor substrate using the gate pattern and the spacer as an ion implantation mask; Forming a silicided stop layer pattern exposing the gate pattern and the source / drain region on a semiconductor substrate having the source / drain regions, Thermally treating the semiconductor substrate having the silicided stop layer pattern to activate impurities in the gate pattern and the source / drain regions, And selectively forming a nickel silicide film on the surface of the activated gate pattern and the surfaces of the activated source / drain regions. The method of claim 20, And the gate pattern is formed of a polysilicon film. The method of claim 20, And the impurity ions are N-type impurity ions or P-type impurity ions. The method of claim 20, Before forming the silicided stop layer pattern, the MOS transistor further comprises preheating a semiconductor substrate including the source / drain regions to activate impurities in the gate pattern and the source / drain regions. Manufacturing method. The method of claim 20, The pre-heat treatment step is a method of manufacturing a MOS transistor, characterized in that carried out at a temperature of 830 ℃ to 1150 ℃. The method of claim 24, The pre-heat treatment step is a manufacturing method of the MOS transistor, characterized in that carried out using nitrogen gas as the atmosphere gas. The method of claim 25, The preheating step is a method of manufacturing a MOS transistor, characterized in that carried out using a rapid heat treatment step. The method of claim 20, Forming the silicided blocking layer pattern comprises forming a silicon nitride film at a temperature of 535 ℃ to 825 ℃. The method of claim 20, The post-heat treatment process is a method of manufacturing a MOS transistor, characterized in that carried out at a temperature of 830 ℃ to 1150 ℃. The method of claim 28, The post-heat treatment step is a method of manufacturing a MOS transistor, characterized in that carried out using nitrogen gas as the atmosphere gas. The method of claim 20, Selectively forming the nickel silicide film Cleaning the surface of the semiconductor substrate on which the post-heat treatment process is completed to expose the surface of the activated gate pattern and the surface of the activated source / drain regions, Forming a nickel film on the entire surface of the cleaned semiconductor substrate, Heat treating the semiconductor substrate having the nickel film at a temperature of 400 ° C. to 530 ° C. to form a nickel mono-silicide layer (NiSi layer) on the gate pattern and the source / drain region; Removing an unreacted nickel layer remaining on the spacer. The method of claim 30, The nickel film is a method of manufacturing a MOS transistor, characterized in that formed of a pure nickel layer (pure nickel layer) or a nickel alloy layer (nickel alloy layer). The method of claim 31, wherein The nickel alloy film is tantalum (Ta), zirconium (Zr), titanium (Ti), hafnium (Hf), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), vanadium (V), Niobium (Nb) or a combination thereof.