KR20040073645A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
- Publication number
- KR20040073645A KR20040073645A KR1020030009298A KR20030009298A KR20040073645A KR 20040073645 A KR20040073645 A KR 20040073645A KR 1020030009298 A KR1020030009298 A KR 1020030009298A KR 20030009298 A KR20030009298 A KR 20030009298A KR 20040073645 A KR20040073645 A KR 20040073645A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- cobalt
- semiconductor device
- manufacturing
- gate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract description 42
- 239000010941 cobalt Substances 0.000 claims abstract description 40
- 229910017052 cobalt Inorganic materials 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 22
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 22
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000010936 titanium Substances 0.000 claims abstract description 18
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 17
- 125000006850 spacer group Chemical group 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 239000005001 laminate film Substances 0.000 claims abstract description 3
- 238000010438 heat treatment Methods 0.000 claims description 10
- 238000004544 sputter deposition Methods 0.000 claims description 7
- 238000009835 boiling Methods 0.000 claims description 3
- 238000001552 radio frequency sputter deposition Methods 0.000 claims description 3
- 239000000725 suspension Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 229910019001 CoSi Inorganic materials 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 코발트실리사이드층과 소오스/드레인 영역 사이의 계면 거칠기를 완화시켜 얕은 접합에서의 누설전류 특성을 향상시킬 수 있는 반도체 소자의 제조방법을 제공한다.The present invention provides a method for manufacturing a semiconductor device capable of improving the leakage current characteristics in a shallow junction by reducing the interface roughness between the cobalt silicide layer and the source / drain regions.
본 발명은 그 상부에는 소자분리막, 게이트 절연막, 게이트 및 게이트 스페이서가 형성되고, 그 내부에는 소오스 및 드레인 영역이 형성된 반도체 기판을 준비하는 단계; 기판 전체 표면 상에 탄소층, 코발트층 및 티타늄층을 순차적으로 증착하여 티타늄/코발트/탄소의 적층막을 형성하는 단계; 적층막이 형성된 기판을 열처리하여 소오스 및 드레인 영역 상부에는 에피택셜 코발트 실리사이드층을 형성하고 게이트 상부에는 다결정 코발트 실리사이드층을 형성하는 단계; 및 미반응된 적층막을 제거하는 단계를 포함하는 반도체 소자의 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention, there is provided a semiconductor substrate including a device isolation layer, a gate insulating layer, a gate, and a gate spacer formed thereon, and a source and drain regions formed therein; Sequentially depositing a carbon layer, a cobalt layer, and a titanium layer on the entire surface of the substrate to form a laminate film of titanium / cobalt / carbon; Heat-treating the substrate on which the laminated film is formed to form an epitaxial cobalt silicide layer on the source and drain regions and a polycrystalline cobalt silicide layer on the gate; And it may be achieved by a method for manufacturing a semiconductor device comprising the step of removing the unreacted laminated film.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 코발트실리사이드층을 적용한 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device to which a cobalt silicide layer is applied.
반도체 소자의 고집적화에 따른 동작 속도 저하를 방지하기 위하여, 실리콘 (Si)층으로 이루어진 게이트 및 소오스/드레인 영역 상부에 자기정렬실리사이드 (self-aligned silicide; 이하 샐리사이드(salicide)) 공정에 의해 비저항이 낮은 금속 실리사이드층을 적용하고 있으며, 금속 실리사이드층의 금속으로서는 텅스텐 (W), 코발트(Co), 티타늄(Ti) 또는 니켈(Ni) 등을 사용한다.In order to prevent a decrease in operating speed due to high integration of semiconductor devices, a resistivity is increased by a self-aligned silicide process on the gate and source / drain regions of silicon (Si) layers. A low metal silicide layer is applied, and tungsten (W), cobalt (Co), titanium (Ti), nickel (Ni), or the like is used as the metal of the metal silicide layer.
여기서, 코발트실리사이드(CoSi2)층은 일반적으로 스퍼터링(sputtering) 방식에 의해 코발트층을 증착하고 열처리에 의해 코발트와 게이트 및 소오스/드레인의 실리콘을 반응시켜 형성한다. 그러나, 코발트실리사이드층의 형성 후 코발트실리사이드층과 실리콘층의 계면 거칠기(roughness)가 심하게 발생하게 되고, 이러한 심한 계면 거칠기는 소오스/드레인 영역의 접합깊이가 얕은 경우 접합 누설전류 특성을 취약하게 하여 결국 소자의 특성을 저하시키게 된다.Here, the cobalt silicide (CoSi 2 ) layer is generally formed by depositing a cobalt layer by a sputtering method and reacting cobalt with silicon of a gate and a source / drain by heat treatment. However, after the formation of the cobalt silicide layer, the interface roughness of the cobalt silicide layer and the silicon layer is severely generated, and this severe interface roughness weakens the junction leakage current characteristic when the junction depth of the source / drain region is shallow. The characteristics of the device are deteriorated.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 코발트실리사이드층과 소오스/드레인 영역 사이의 계면 거칠기를 완화시켜 얕은 접합에서의 누설전류 특성을 향상시킬 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention is proposed to solve the above problems of the prior art, a method of manufacturing a semiconductor device that can improve the leakage current characteristics in the shallow junction by reducing the interface roughness between the cobalt silicide layer and the source / drain region The purpose is to provide.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
※ 도면의 주요부분에 대한 부호의 설명※ Explanation of code for main part of drawing
10 : 반도체 기판 11 : 소자분리막10 semiconductor substrate 11 device isolation film
12 : 게이트 절연막 13 : 게이트12 gate insulating film 13 gate
14 : 게이트 스페이서 15A1, 15A2 : 소오스 및 드레인 영역14: gate spacer 15A1, 15A2: source and drain regions
16 : 탄소층 17 : 코발트층16: carbon layer 17: cobalt layer
18 : 티타늄층 19A1, 19A2 : 에피택셜 코발트실리사이드층18: titanium layer 19A1, 19A2: epitaxial cobalt silicide layer
19B : 다결정 코발트실리사이드층19B: polycrystalline cobalt silicide layer
100 : 적층막100: laminated film
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 그 상부에는 소자분리막, 게이트 절연막, 게이트 및 게이트 스페이서가 형성되고, 그 내부에는 소오스 및 드레인 영역이 형성된 반도체 기판을 준비하는 단계; 기판 전체 표면 상에 탄소층, 코발트층 및 티타늄층을 순차적으로 증착하여 티타늄/코발트/탄소의 적층막을 형성하는 단계; 적층막이 형성된 기판을 열처리하여 소오스 및 드레인 영역 상부에는 에피택셜 코발트실리사이드층을 형성하고 게이트 상부에는 다결정 코발트실리사이드층을 형성하는 단계; 및 미반응된 적층막을 제거하는 단계를 포함하는 반도체 소자의 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, an object isolation film, a gate insulating film, a gate and a gate spacer are formed on the upper portion, the semiconductor having a source and a drain region formed therein Preparing a substrate; Sequentially depositing a carbon layer, a cobalt layer, and a titanium layer on the entire surface of the substrate to form a laminate film of titanium / cobalt / carbon; Heat-treating the substrate on which the stacked film is formed to form an epitaxial cobalt silicide layer on the source and drain regions and a polycrystalline cobalt silicide layer on the gate; And it may be achieved by a method for manufacturing a semiconductor device comprising the step of removing the unreacted laminated film.
여기서, 탄소층의 두께는 50 내지 150Å이고, 코발트층의 두께는 100 내지 150Å이며, 티타늄층의 두께는 150 내지 250Å이다. 또한, 적층막의 형성은 스퍼터링 방식으로 수행하는데, 바람직하게 탄소층의 증착은 RF 스퍼터링 방식으로 수행하고, 코발트층 및 티타늄층은 RF 또는 DC 스퍼터링 방식으로 수행한다.Here, the thickness of the carbon layer is 50 to 150 kPa, the thickness of the cobalt layer is 100 to 150 kPa, and the thickness of the titanium layer is 150 to 250 kPa. In addition, the formation of the laminated film is performed by a sputtering method. Preferably, the deposition of the carbon layer is performed by the RF sputtering method, and the cobalt layer and the titanium layer are performed by the RF or DC sputtering method.
또한, 열처리는 급속열처리 공정으로 600 내지 800℃의 온도에서 30초 내지 1분 동안 수행하고, 미반응된 적층막의 제거는 끓는 H2SO4/HNO3용액 속에 KClO4를 현탁액으로 녹인 용액을 사용하여 수행한다.In addition, the heat treatment is a rapid heat treatment process is carried out for 30 seconds to 1 minute at a temperature of 600 to 800 ℃, removal of the unreacted laminated film using a solution of KClO 4 as a suspension in boiling H 2 SO 4 / HNO 3 solution Do it.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 1a를 참조하면, 소자 분리막(11)이 형성된 반도체 기판(10) 상에 게이트 절연막(12)과 게이트(13)를 순차적으로 형성한다. 여기서, 기판(10)은 단결정 실리콘 기판이며, 게이트(13)는 폴리실리콘막으로 이루어진다. 그 다음, 게이트(13) 양측의 기판으로 LDD(Lightly Doped Drain) 이온을 주입하고, 게이트(13)의 측벽에 절연막의 게이트 스페이서(14)를 형성한 후, 다시 게이트 스페이서(14) 양측의 기판으로 고농도 불순물 이온을 주입하여 소오스 및 드레인 영역(15A1, 15A2)을 형성한다. 그 다음, HF 용액으로 기판 표면을 세정하여 자연산화막 등을 제거한 후, 기판 전체 표면 상에 스퍼터링 방식으로 탄소층(16), 코발트층(17) 및 티타늄층(18)을 순차적으로 증착하여 티타늄/코발트/탄소의 적층막(100)을 형성한다. 여기서, 탄소층(16)은 후속 코발트실리사이드 형성을 위한 열처리 공정시 코발트에 대한 확산배리어로서 작용하고, 티타늄층(18)은 상기 열처리 공정시 코발트의 산화를 방지한다. 바람직하게, 탄소층(16)은 50 내지 150Å의 두께로 증착하고, 코발트층(17)은 100 내지 150Å의 두께로 증착하며, 티타늄층(18)은 150 내지 250Å의 두께로 증착하며, 더욱 바람직하게 탄소층(16)은 RF 스퍼터링 방식으로 증착하고, 코발트층(17) 및 티타늄층(18)은 RF 또는 DC 스퍼터링 방식으로 증착한다.Referring to FIG. 1A, the gate insulating layer 12 and the gate 13 are sequentially formed on the semiconductor substrate 10 on which the device isolation layer 11 is formed. Here, the substrate 10 is a single crystal silicon substrate, and the gate 13 is made of a polysilicon film. Next, LDD (Lightly Doped Drain) ions are implanted into the substrates on both sides of the gate 13, the gate spacers 14 of the insulating film are formed on the sidewalls of the gate 13, and then, the substrates on both sides of the gate spacers 14 are formed again. High concentration impurity ions are implanted to form source and drain regions 15A1 and 15A2. Then, the surface of the substrate is cleaned by HF solution to remove the native oxide film, and the like, and then the carbon layer 16, the cobalt layer 17, and the titanium layer 18 are sequentially deposited by sputtering on the entire surface of the substrate to form titanium / A cobalt / carbon laminated film 100 is formed. Here, the carbon layer 16 acts as a diffusion barrier for cobalt during the heat treatment process for subsequent cobalt silicide formation, and the titanium layer 18 prevents cobalt oxidation during the heat treatment process. Preferably, the carbon layer 16 is deposited to a thickness of 50 to 150 kPa, the cobalt layer 17 is deposited to a thickness of 100 to 150 kPa, the titanium layer 18 is deposited to a thickness of 150 to 250 kPa, and more preferably. The carbon layer 16 is deposited by RF sputtering, and the cobalt layer 17 and titanium layer 18 are deposited by RF or DC sputtering.
도 1b를 참조하면, 급속열처리(Rapid Thermal Annealing; RTA) 공정에 의해 적층막(100)이 형성된 기판을 열처리하여 소오스 및 드레인 영역(15A1, 15A2) 상에는 에피택셜 코발트실리사이드층(epitaxial CoSi2; 19A1, 19A2)를 형성하고 게이트 (13) 상에는 다결정 코발트실리사이드층(polycrystal CoSi2; 19B)을 형성한다. 바람직하게, 급속열처리 공정은 600 내지 800℃의 온도에서 30초 내지 1분 동안 수행한다. 즉, 급속열처리 공정시 탄소층(16)이 확산배리어로서 작용하여 코발트 원자의 확산속도를 저하시켜 CoSi2의 형성온도를 증가시킬 뿐만 아니라 단위면적당 코발트 원자가 확산되는 비율을 감소시켜 단결정 실리콘층인 소오스 및 드레인 영역(15A1, 15A2) 상에서 Co2Si 상(phase)이나 CoSi 상을 형성하는 것 없이 CoSi2상의 에피택셜 CoSi2층(19A1, 19A2)을 형성하는 것을 가능하게 한다. 이러한 에피택셜 CoSi2층(19A1, 19A2)은 소오스 및 드레인 영역(15A1, 15A2)과의 계면 거칠기가 완만하여 평탄한 계면을 이루기 때문에 소오스 및 드레인 영역(15A1, 15A2)의 접합깊이에 관계없이 접합 누설전류 증가를 방지할 수 있다.Referring to FIG. 1B, an epitaxial cobalt silicide layer (epitaxial CoSi 2 ; 19A1) is formed on the source and drain regions 15A1 and 15A2 by heat-treating the substrate on which the laminated film 100 is formed by a rapid thermal annealing (RTA) process. , 19A2), and a polycrystal Cobalt silicide layer (polycrystal CoSi 2 ; 19B) is formed on the gate 13. Preferably, the rapid heat treatment process is carried out for 30 seconds to 1 minute at a temperature of 600 to 800 ℃. That is, during the rapid heat treatment process, the carbon layer 16 acts as a diffusion barrier to decrease the diffusion rate of cobalt atoms, thereby increasing the formation temperature of CoSi 2 and reducing the diffusion rate of cobalt atoms per unit area. And it is possible to form the epitaxial CoSi 2 layers 19A1 and 19A2 on CoSi 2 without forming a Co 2 Si phase or a CoSi phase on the drain regions 15A1 and 15A2. Since the epitaxial CoSi 2 layers 19A1 and 19A2 have a smooth interface roughness with the source and drain regions 15A1 and 15A2, they form a flat interface, regardless of the junction depth of the source and drain regions 15A1 and 15A2. Current increase can be prevented.
도 1c를 참조하면, 소자분리막(11) 및 게이트 스페이서(14) 상의 미반응된 적층막(100)과 CoSi2층(19A1, 19A2, 19B) 상의 미반응된 적층막(100')을 끓는 H2SO4/HNO3용액 속에 KClO4를 현탁액으로 녹인 용액을 사용하여 제거한다.Referring to FIG. 1C, H of boiling the unreacted laminated film 100 on the device isolation layer 11 and the gate spacer 14 and the unreacted laminated film 100 'on the CoSi 2 layers 19A1, 19A2, and 19B are heated. 2 KClO 4 is dissolved in a SO 4 / HNO 3 solution using a solution dissolved in suspension.
상기 실시예에 의하면, 코발트층 하부에 탄소층을 적용하여 단결정 실리콘층인 소오스 및 드레인 영역 상에서 평탄한 계면 특성을 가지는 에피택셜 코발트실리사이드층을 형성함으로써 접합깊이에 관계없이 우수한 접합 누설전류 특성을 얻을 수 있게 된다.According to the above embodiment, an excellent junction leakage current property can be obtained regardless of the junction depth by forming an epitaxial cobalt silicide layer having a flat interfacial property on the source and drain regions of the single crystal silicon layer by applying a carbon layer under the cobalt layer. Will be.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은 소오스/드레인 영역 상에 에피택셜 코발트실리사이드층을 적용하여 이들 사이의 계면 거칠기를 완화시켜 평탄한 계면 특성을 갖도록 함으로써 얕은 접합에서의 누설전류 특성을 향상시킬 수 있다.According to the present invention, an epitaxial cobalt silicide layer is applied on a source / drain region to mitigate interfacial roughness therebetween so as to have a flat interfacial characteristic, thereby improving leakage current characteristics in shallow junctions.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030009298A KR100541149B1 (en) | 2003-02-14 | 2003-02-14 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030009298A KR100541149B1 (en) | 2003-02-14 | 2003-02-14 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20040073645A true KR20040073645A (en) | 2004-08-21 |
| KR100541149B1 KR100541149B1 (en) | 2006-01-11 |
Family
ID=37360632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020030009298A KR100541149B1 (en) | 2003-02-14 | 2003-02-14 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100541149B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100779394B1 (en) * | 2006-11-13 | 2007-11-23 | 동부일렉트로닉스 주식회사 | Semiconductor device manufacturing method |
| US7365010B2 (en) | 2004-12-08 | 2008-04-29 | Samsung Electronics Co., Ltd. | Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same |
-
2003
- 2003-02-14 KR KR1020030009298A patent/KR100541149B1/en active IP Right Grant
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7365010B2 (en) | 2004-12-08 | 2008-04-29 | Samsung Electronics Co., Ltd. | Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same |
| KR100779394B1 (en) * | 2006-11-13 | 2007-11-23 | 동부일렉트로닉스 주식회사 | Semiconductor device manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100541149B1 (en) | 2006-01-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6562718B1 (en) | Process for forming fully silicided gates | |
| KR100196598B1 (en) | Semiconductor device manufacturing method | |
| JPH07321065A (en) | Semiconductor device having silicide contact and manufacturing method | |
| US6380057B1 (en) | Enhancement of nickel silicide formation by use of nickel pre-amorphizing implant | |
| KR100276388B1 (en) | Silicide Forming Method Using Cobalt / Niobium Double Metal Layer Structure | |
| US6432805B1 (en) | Co-deposition of nitrogen and metal for metal silicide formation | |
| US6294415B1 (en) | Method of fabricating a MOS transistor | |
| US7056796B2 (en) | Method for fabricating silicide by heating an epitaxial layer and a metal layer formed thereon | |
| KR100541149B1 (en) | Manufacturing method of semiconductor device | |
| US20020111021A1 (en) | Ozone oxide as a mediating layer in nickel silicide formation | |
| JP2001053027A (en) | Method for manufacturing semiconductor device | |
| JP2733082B2 (en) | MOS device manufacturing method | |
| JPWO2008139815A1 (en) | Semiconductor device and manufacturing method thereof | |
| US6372673B1 (en) | Silicon-starved nitride spacer deposition | |
| KR100620235B1 (en) | Titanium Silicide Manufacturing Method | |
| KR100486649B1 (en) | Method for forming salicide of a semiconductor device | |
| KR100510442B1 (en) | A method for forming double layered-silicide and a mos transistor having self-aligned silicide | |
| JP3334692B2 (en) | Method for manufacturing semiconductor device | |
| TW434711B (en) | Method for making silicide | |
| KR19990001016A (en) | Method of manufacturing transistor of semiconductor device | |
| KR100334866B1 (en) | Transistor Formation Method of Semiconductor Device | |
| JP3537273B2 (en) | Method for manufacturing semiconductor device | |
| KR100348310B1 (en) | method for manufacturing of semiconductor device | |
| CN1862779A (en) | Method for producing metal silicide | |
| KR100309137B1 (en) | Semiconductor device manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20030214 |
|
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20031001 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 20030214 Comment text: Patent Application |
|
| PG1501 | Laying open of application | ||
| N231 | Notification of change of applicant | ||
| PN2301 | Change of applicant |
Patent event date: 20041006 Comment text: Notification of Change of Applicant Patent event code: PN23011R01D |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20050423 Patent event code: PE09021S01D |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20051220 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20051228 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 20051228 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| PR1001 | Payment of annual fee |
Payment date: 20081114 Start annual number: 4 End annual number: 4 |
|
| PR1001 | Payment of annual fee |
Payment date: 20091117 Start annual number: 5 End annual number: 5 |
|
| PR1001 | Payment of annual fee |
Payment date: 20101122 Start annual number: 6 End annual number: 6 |
|
| PR1001 | Payment of annual fee |
Payment date: 20111124 Start annual number: 7 End annual number: 7 |
|
| FPAY | Annual fee payment |
Payment date: 20121121 Year of fee payment: 8 |
|
| PR1001 | Payment of annual fee |
Payment date: 20121121 Start annual number: 8 End annual number: 8 |
|
| FPAY | Annual fee payment |
Payment date: 20131118 Year of fee payment: 9 |
|
| PR1001 | Payment of annual fee |
Payment date: 20131118 Start annual number: 9 End annual number: 9 |
|
| FPAY | Annual fee payment |
Payment date: 20141119 Year of fee payment: 10 |
|
| PR1001 | Payment of annual fee |
Payment date: 20141119 Start annual number: 10 End annual number: 10 |
|
| FPAY | Annual fee payment |
Payment date: 20151118 Year of fee payment: 11 |
|
| PR1001 | Payment of annual fee |
Payment date: 20151118 Start annual number: 11 End annual number: 11 |
|
| FPAY | Annual fee payment |
Payment date: 20161118 Year of fee payment: 12 |
|
| PR1001 | Payment of annual fee |
Payment date: 20161118 Start annual number: 12 End annual number: 12 |
|
| FPAY | Annual fee payment |
Payment date: 20171117 Year of fee payment: 13 |
|
| PR1001 | Payment of annual fee |
Payment date: 20171117 Start annual number: 13 End annual number: 13 |
|
| FPAY | Annual fee payment |
Payment date: 20181120 Year of fee payment: 14 |
|
| PR1001 | Payment of annual fee |
Payment date: 20181120 Start annual number: 14 End annual number: 14 |
|
| FPAY | Annual fee payment |
Payment date: 20191119 Year of fee payment: 15 |
|
| PR1001 | Payment of annual fee |
Payment date: 20191119 Start annual number: 15 End annual number: 15 |
|
| PC1903 | Unpaid annual fee |
Termination category: Default of registration fee Termination date: 20211008 |