KR20040066268A - Method for manufacturing array substrate - Google Patents

Abstract

PURPOSE: A fabrication method of an array substrate is provided to form the first organic insulating film having the first contact hole and the second organic insulating film having the second contact hole, and to form a drain electrode and a pixel electrode on the second organic insulating film. CONSTITUTION: A poly-Si layer(121) is deposited on the first substrate(110). A gate insulating film(122) is on the poly-Si layer(121), and a gate electrode(123) is on the gate insulating film(122). An 'n' or a 'p' channel is formed by doping the poly-Si layer(121). An interlayer insulating film(124) consisting of the first and second contact holes is accumulated on the gate insulating film(122). A source electrode(125) is electrically connected with the poly-Si layer(121) through the first contact hole, and a drain electrode(126) is electrically connected with the poly-Si layer(121) through the second contact hole.

Description

Manufacturing Method of Array Substrate {METHOD FOR MANUFACTURING ARRAY SUBSTRATE}

The present invention relates to a method of manufacturing an array substrate, and more particularly, to a method of manufacturing an array substrate capable of increasing productivity while improving display characteristics.

The liquid crystal display device includes an array substrate on which a thin film transistor (TFT) and a pixel electrode are formed, a color filter substrate facing the array substrate, and a liquid crystal layer interposed between the array substrate and the color filter substrate. .

According to the structure of the TFT, the liquid crystal display includes an amorphous-silicon liquid crystal display (a-si LCD) and a polycrystalline-silicon liquid crystal display (hereinafter, poly-si LCD). Separated by. Specifically, the a-si LCD is made of TFT made of a-si, and the poly-si LCD is made of TFT made of poly-si.

The poly-si TFT has a disadvantage in that the manufacturing process is more complicated than that of the a-si LCD. However, the poly-si TFT has a faster charge transfer rate than the a-si TFT. Therefore, the poly-si LCD can realize a cost reduction effect, a thinner and lighter weight due to the built-in circuit than the a-si LCD. In addition, there is an advantage that it is suitable as a switching element used to implement a large screen and a high resolution screen has been recently developed a lot.

In general, an array substrate used in an a-si liquid crystal display device and a poly-si liquid crystal display device has an organic insulating film interposed between a drain electrode and a pixel electrode of a TFT. A contact hole for exposing the drain electrode is formed in the organic insulating layer, and the pixel electrode is electrically connected to the drain electrode through the contact hole.

Here, since the organic insulating film has a lower dielectric constant than the inorganic film, the thickness of the organic insulating film is thicker than that of the inorganic film. As the thickness of the organic insulating layer is increased, the inclination of the sidewall of the organic insulating layer defining the contact hole is rapidly increased. Due to the steep inclination of the sidewalls, the pixel electrodes formed on the organic insulating layer may not be normally stacked. That is, a poor contact occurs between the pixel electrode and the drain electrode.

In addition, due to the thickness of the organic insulating layer, the organic insulating layer may not be in normal contact with the drain electrode at a portion corresponding to the drain electrode, thereby causing a phenomenon of lifting from the drain electrode.

Accordingly, it is an object of the present invention to provide a method of manufacturing an array substrate for increasing productivity while improving display characteristics.

1 is a cross-sectional view of a poly-si liquid crystal display device according to an exemplary embodiment of the present invention.

FIG. 2 is a plan view specifically illustrating a pixel included in the array substrate illustrated in FIG. 1.

3 is an enlarged cross-sectional view illustrating an enlarged portion A shown in FIG. 1.

4A to 4E are enlarged cross-sectional views illustrating in detail a manufacturing process of the array substrate illustrated in FIG. 1.

<Explanation of symbols for the main parts of the drawings>

100: array substrate 120: TFT

130: first organic insulating layer 131: third contact hole

135: first photosensitive film 137: mask

140: second organic insulating film 141: fourth contact hole

145: second photosensitive film 150: pixel electrode

200: color filter substrate 300: liquid crystal layer

400: liquid crystal display

Method of manufacturing an array substrate according to the present invention for achieving the above object of the present invention, forming a conductive pattern on the substrate; Forming a first photosensitive organic layer on the substrate on which the conductive pattern is formed; Patterning the first photosensitive organic layer to form a first organic insulating layer having a first contact hole for exposing the conductive pattern; Forming a second photosensitive organic layer on the conductive pattern exposed by the first organic insulating layer and the first contact hole; Forming a second organic insulating layer having a second contact hole for exposing the conductive pattern by patterning the second photosensitive organic layer, the sidewalls defining the second contact hole having a stepped shape; And forming a conductive film on the conductive pattern exposed by the second contact hole and the second organic insulating film.

According to the method of manufacturing the array substrate, after the first organic insulating film having the first contact hole is formed on the substrate, the second organic insulating film having the second contact hole defined by the sidewall having a step shape is formed. Next, a conductive film is formed on the conductive pattern exposed by the second contact hole and the second organic insulating film. Therefore, the conductive film can be normally connected to the conductive pattern, thereby increasing the productivity of the array substrate.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a cross-sectional view illustrating a poly-si liquid crystal display device according to an exemplary embodiment of the present invention, and FIG. 2 is a plan view specifically illustrating a pixel included in the array substrate of FIG. 1.

1 and 2, a poly-si liquid crystal display device 400 according to an exemplary embodiment of the present invention includes an array substrate 100, a color filter substrate 200, and the array substrate 100 and a color filter substrate. It consists of the liquid crystal layer 300 interposed between 200 and.

A plurality of pixels is formed in the array substrate 100 in a matrix form. Each of the plurality of pixels is provided in a region partitioned by a gate line GL extending in a first direction and a data line DL extending in a second direction perpendicular to the first direction. Each of the plurality of pixels includes a TFT 120 connected to the gate line GL and the data line DL, and a pixel electrode 150 coupled to the TFT 120.

Specifically, the gate electrode 123 of the TFT 120 is connected to the gate line GL, the source electrode 125 of the TFT 120 is connected to the data line DL, and the TFT ( The drain electrode 126 of the 120 is coupled to the pixel electrode 150.

As shown in FIG. 1, a poly-si layer 121 is disposed on the first substrate 110, a gate insulating layer 122 and a gate electrode 123 are disposed on the gate insulating layer 122. Thereafter, the poly-si layer 121 is doped with boron (B) or phosphorus (P) to form an n or p channel. In addition, an interlayer insulating layer 124 having first and second contact holes for exposing a portion of the poly-si layer 121 is formed on the gate insulating layer 122 on which the gate electrode 123 is formed. The interlayer insulating layer 124 is electrically connected to the poly-si layer 121 through the source electrode 125 and the second contact hole, which are electrically connected to the poly-si layer 121 through the first contact hole. The drain electrode 126 connected to is formed.

Thereafter, a passivation layer is formed on the first substrate 110 on which the source and drain electrodes 125 and 126 are formed. The passivation layer includes a first organic insulating layer 130 and a second organic insulating layer 140. A third contact hole 131 is formed in the first organic insulating layer 130 to expose the drain electrode 126, and an agent is formed to expose the drain electrode 126 in the second organic insulating layer 140. Four contact holes 141 are formed.

3 is an enlarged cross-sectional view illustrating an enlarged portion A shown in FIG. 1.

1 and 3, the first organic insulating layer 130 includes a first sidewall 130a for defining the third contact hole 131. The first sidewall 130a is inclined at a first inclination angle to define the third contact hole 131 having a first diameter d1 on average. Meanwhile, the second organic insulating layer 140 has a second sidewall 140c for defining the fourth contact hole 141. The second sidewall 140c is inclined at a first inclined surface 140a having the same shape as the first sidewall 130a and a second inclined angle different from the first inclined angle at a position corresponding to the first sidewall 130a. The second inclined surface 140b is formed. The second sidewall 140c has a step shape by the first and second inclined surfaces 140a and 140b, and the fourth contact hole 141 defined by the second inclined surface 140b has the average value. It has a second diameter d2 smaller than the first diameter d1.

The pixel electrode 150 is formed on the second organic insulating layer 140 to be electrically connected to the drain electrode 126 through the fourth contact hole 131. The pixel electrode 150 is made of indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material. The pixel electrode 150 defines the fourth contact hole 141 and is formed on the second sidewall 140c having a step shape by the first and second inclined surfaces 140a and 140b. The drain electrode 126 may be normally connected to a region where the fourth contact hole 141 is formed.

Referring back to FIG. 1, the color filter substrate 200 includes a second substrate 210, R, G, and B color pixels, and the color filter 220 and the color filter formed on the second substrate 210. The common electrode 230 is formed to have a uniform thickness on the 220.

When the array substrate 100 and the color filter substrate 200 are completed, the array substrate 100 and the color filter substrate 200 face each other so that the pixel electrode 140 and the common electrode 230 face each other. Combined. Thereafter, the liquid crystal layer 300 is interposed between the array substrate 100 and the color filter substrate 200. Thus, the poly-si liquid crystal display device 400 is completed.

4A to 4E are enlarged cross-sectional views illustrating in detail a manufacturing process of the array substrate illustrated in FIG. 1.

Referring to FIG. 4A, an a-si layer is deposited on a first substrate 110 by a low plasma chemical vapor deposition (LPCVD) method. Thereafter, the a-si layer is crystallized through heat treatment to form a poly-si layer. In order to increase crystallinity, silicon ion implantation may be performed before crystallization. Subsequently, the poly-si layer 121 is patterned through a dry etching process.

Next, the poly-si layer 121 is reacted with oxygen to form an oxide film. The oxide film is used as the gate insulating film 122. Thereafter, a gate electrode layer is formed on the gate insulating layer 122, and then patterned to form a gate electrode 123.

An ion implantation process for doping the poly-si layer 121 is performed on the first substrate 110 on which the gate electrode 123 is formed. In other words, it is doped with boron (B) to make a p-type TFT, and doped with phosphorus (P) to make an n-type TFT. When boron (B) or phosphorus (P) is injected to determine an n channel or a p channel, an interlayer insulating layer 124 is deposited on the first substrate 110. First and second contact holes exposing the n channel layer or the p channel layer are formed in the interlayer insulating layer 124.

A source electrode electrically connected to the poly-si layer 121 doped through the first contact hole is formed in the first substrate 110, and the poly-si layer doped through the second contact hole ( A drain electrode electrically connected to 121 is formed.

Referring to FIG. 4B, on the interlayer insulating layer 124, the source electrode 125, and the drain electrode 126, a first photosensitive layer 135 made of photosensitive acrylic resin is stacked to a first thickness t1. Here, the first thickness t1 is about one third of the overall thickness t2 of the protective film shown in FIG. 1. As illustrated in FIG. 4C, a mask 137 having a first opening 137a having a diameter corresponding to the third contact hole 131 is formed on the first photoresist layer 135. After exposing the first photoresist layer 135 for a first time while the mask 137 is provided, the exposed first photoresist layer 135 is reacted with a developer. Then, the first organic insulating layer 130 on which the third contact hole 131 is formed is completed.

Thereafter, the first organic insulating layer 130 is cured by being heat treated at about 230 ° C. As a result, the first sidewall 130a of the first organic insulating layer 130 defining the third contact hole 131 becomes smooth. That is, the first sidewall 130a is inclined with the first inclination angle.

Referring to FIG. 4D, on the drain electrode 126 exposed by the first organic insulating layer 130 and the third contact hole 131, the second photosensitive layer 145 made of photosensitive acrylic resin has a second thickness ( t3). Here, the second thickness t3 is about 2/3 of the overall thickness t2 of the protective film shown in FIG. 1. The second photoresist layer 145 includes a first inclined surface 140a having the same profile as that of the first sidewall 130a of the first organic insulating layer 130.

As shown in FIG. 4E, the mask 137 having the first opening 137a is provided on the second photosensitive layer 145. That is, the mask 137 was used to expose the first photosensitive film 135.

The second photosensitive film 145 is exposed for a second time while the mask 137 is provided. In general, the exposure time increases in proportion to the thickness of the film to be exposed. Here, although the second photoresist layer 145 has twice the thickness of the first photoresist layer 135, the second time of exposing the second photoresist layer 145 is the first photoresist layer 135. Is less than twice the first time for exposing. Therefore, the second organic insulating layer 140 completed after developing the second photoresist layer 145 exposed for the second time period has a smaller diameter than the first diameter d1 of the third contact hole 131. A fourth contact hole 141 having two diameters d2 is formed.

That is, the fourth contact hole 141 has a step shape formed by the shape of the first sidewall 130a of the first organic insulating layer 130 and the second sidewall 140c of the second organic insulating layer 140. Is defined by That is, the second sidewall 140c is formed by the first inclined surface 140a having the same profile as the first sidewall 130a and the second inclined surface 140b having a steeper slope than the first inclined surface 140a. It is formed in a step shape.

As a result, a passivation layer including the first organic insulating layer 130 and the second organic insulating layer 140 is completed on the first substrate 110. The passivation layer is divided into an opening area OA exposing the drain electrode 126 and a contact area CA in contact with the drain electrode 126. The passivation layer is primarily in contact with the drain electrode 126 through the first organic insulating layer 130 in the contact region CA. Here, since the first organic insulating layer 130 has a thickness t1 that is thinner than the overall thickness t2 of the passivation layer, adhesion to the drain electrode 126 is increased. Therefore, a phenomenon in which the first organic insulating layer 130 is peeled off from the drain electrode 126 may be reduced.

In addition, since the first organic insulating layer 130 is provided below the second organic insulating layer 140, the second organic insulating layer 140 may be formed of the first organic insulating layer 130 and the drain electrode 126. Is in contact with each. Here, since the first and second organic insulating layers 130 and 140 are made of the same material, the adhesion between the first and second organic insulating layers 130 and 140 is excellent. Since the first organic insulating layer 130 is interposed between the second organic insulating layer 140 and the drain electrode 126, the second organic insulating layer 140 is drained in the contact area CA. The area directly contacting the electrode 126 is smaller than that of the first organic insulating layer 130. Therefore, even if the second organic insulating layer 140 is stacked thicker than the first organic insulating layer 130, the peeling from the drain electrode 126 can be prevented.

That is, when the protective film is formed by dividing the first and second organic insulating layers 130 and 140 into the protective film, the lifting phenomenon from the drain electrode 126 is reduced.

In the above, the protective film is formed by performing the organic film forming process twice in the display area in which the plurality of pixels are formed to display an image. However, the method of forming the passivation layer through two organic layer formation processes may be applied to the case where the passivation layer is provided in a pad region formed by extending one end of the gate line GL and the data line DL. have.

In addition, although only the poly-si liquid crystal display device 400 has been described above, a method of forming a protective film having a step shape on an array substrate in a region where a contact hole is formed through two organic film forming processes may be performed. The present invention can also be sufficiently applied to a-si liquid crystal display devices.

According to the method of manufacturing the array substrate, after the first organic insulating film having the first contact hole is formed on the substrate, the second organic insulating film having the second contact hole defined by the sidewall having a step shape is formed. Next, a pixel electrode is formed on the drain electrode and the second organic insulating layer exposed by the second contact hole.

Therefore, the pixel electrode is normally connected to the drain electrode, thereby preventing the defects occurring in the manufacturing process of the array substrate, thereby increasing the productivity of the array substrate.

In addition, since the pixel electrode is normally connected to the drain electrode, the voltage output from the drain electrode is normally applied to the pixel electrode. Therefore, the array substrate can be driven normally, thereby improving the display characteristics of the liquid crystal display device.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (8)

Forming a conductive pattern on the substrate; Forming a first photosensitive organic layer on the substrate on which the conductive pattern is formed; Patterning the first photosensitive organic layer to form a first organic insulating layer having a first contact hole for exposing the conductive pattern; Forming a second photosensitive organic layer on the conductive pattern exposed through the first organic insulating layer and the first contact hole; Forming a second organic insulating layer having a second contact hole for exposing the conductive pattern by patterning the second photosensitive organic layer, the sidewalls defining the second contact hole having a stepped shape; And Forming a conductive film on the conductive pattern exposed by the second contact hole and the second organic insulating film. The method of claim 1, wherein the first photosensitive organic layer has a first thickness, and the second photosensitive organic layer has a second thickness that is greater than the first thickness. The method of claim 2, wherein the second thickness is twice the first thickness. The method of claim 1, wherein the first contact hole has a first diameter, and the second contact hole has a second diameter smaller than the first diameter. The method of claim 1, wherein the second photosensitive organic layer is patterned by using a mask used to pattern the first photosensitive organic layer. 6. The method of claim 5, wherein the second time of exposing the second photosensitive organic film in the patterning of the second photosensitive organic film is from the first time of exposing the first photosensitive organic film in the step of patterning the first photosensitive organic film. The increased ratio is less than a ratio wherein the first thickness of the second photosensitive organic film is increased from the second thickness of the first photosensitive organic film. The method of claim 1, wherein a plurality of TFTs are provided in a matrix form on the substrate, and the conductive pattern is a drain electrode of each of the plurality of TFTs. The method of claim 1, wherein the conductive film is made of a transparent conductive material.