KR20040011245A - Semiconductor device and fabrication method of thereof - Google Patents
Semiconductor device and fabrication method of thereof Download PDFInfo
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- KR20040011245A KR20040011245A KR1020020045017A KR20020045017A KR20040011245A KR 20040011245 A KR20040011245 A KR 20040011245A KR 1020020045017 A KR1020020045017 A KR 1020020045017A KR 20020045017 A KR20020045017 A KR 20020045017A KR 20040011245 A KR20040011245 A KR 20040011245A
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- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 title claims description 24
- 239000002184 metal Substances 0.000 claims abstract description 65
- 229910052751 metal Inorganic materials 0.000 claims abstract description 65
- 239000010410 layer Substances 0.000 claims abstract description 51
- 239000011229 interlayer Substances 0.000 claims abstract description 32
- 239000003990 capacitor Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 238000009832 plasma treatment Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 67
- 239000012212 insulator Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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Abstract
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 금속/ 절연체/ 금속 (MIM) 구조의 커패시터를 포함하는 반도체 소자 및 그 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device comprising a capacitor of a metal / insulator / metal (MIM) structure and a method of manufacturing the same.
최근 등장하는 복합 반도체장치(MML:Merged Memory Logic)는 하나의 칩 내에 메모리 셀 어레이부, 예컨대 디램(DRAM :dynamic random access memory)과 아날로그 또는 주변회로가 함께 집적화된 소자이다. 이러한 복합 반도체장치의 등장으로 인해 멀티미디어 기능이 크게 향상되어 종전보다 반도체장치의 고집적화 및 고속화를 효과적으로 달성할 수 있게 되었다.BACKGROUND ART Recently, a merged memory logic (MML) is a device in which a memory cell array unit such as dynamic random access memory (DRAM) and an analog or peripheral circuit are integrated together in one chip. Due to the emergence of such composite semiconductor devices, multimedia functions have been greatly improved, and high integration and speed of semiconductor devices can be effectively achieved.
한편, 고속 동작을 요구하는 아날로그 회로에서는 고용량의 커패시터를 구현하기 위한 반도체소자 개발이 진행 중에 있다. 일반적으로, 커패시터가 다결정실리콘(polysilicon)/ 절연체(insulator)/ 다결정실리콘(polysilicon)의 PIP 구조일 경우에는 상부전극 및 하부전극을 도전성 다결정실리콘으로 사용하기 때문에 상,하부전극과 유전체 박막 계면에서 산화반응이 일어나 자연산화막이 형성되어 전체커패시턴스의 크기가 줄어들게 되는 단점이 있다.Meanwhile, in an analog circuit requiring high speed operation, development of a semiconductor device for implementing a high capacitance capacitor is underway. In general, when the capacitor is a PIP structure of polysilicon / insulator / polysilicon, the upper electrode and the lower electrode are used as the conductive polysilicon, so that the oxides are oxidized at the upper and lower electrodes and the dielectric thin film interface. The reaction occurs to form a natural oxide film has the disadvantage that the size of the total capacitance is reduced.
이를 해결하기 위해 커패시터의 구조를 금속/절연체/실리콘 (metal/insulator/silicon : MIS) 또는 금속/절연체/금속(metal/insulator/metal : MIM)으로 변경하게 되었는데, 그 중에서도 MIM 구조의 커패시터는 비저항이 작고 내부에 공핍(deplection)에 의한 기생 커패시턴스가 없기 때문에 고성능 반도체 장치에 주로 이용되고 있다.To solve this problem, the structure of the capacitor was changed to metal / insulator / silicon (MIS) or metal / insulator / metal (MIM). Because of its small size and no parasitic capacitance due to depletion inside, it is mainly used for high performance semiconductor devices.
그런데, MIM형 아날로그 커패시터는 다른 반도체 소자와 동시에 구현되어야 하므로 상호 연결배선(interconnection line)인 금속배선을 통해서 반도체소자와 전기적으로 연결되어 있다.However, since the MIM type analog capacitor should be implemented at the same time as other semiconductor devices, the MIM type analog capacitor is electrically connected to the semiconductor device through a metal wiring, which is an interconnection line.
그러면, 종래 반도체 소자 제조방법에 따라 MIM 구조의 커패시터를 제조하는 방법을 첨부된 도면을 참조하여 설명한다. 도 1은 종래 방법에 따라 형성된 반도체 소자를 도시한 단면도이다.Next, a method of manufacturing a capacitor having a MIM structure according to a conventional semiconductor device manufacturing method will be described with reference to the accompanying drawings. 1 is a cross-sectional view showing a semiconductor device formed according to a conventional method.
먼저, 반도체 기판(1)의 상부에 통상의 반도체 소자 공정을 진행하고 층간절연막(미도시)을 형성한 다음, 층간절연막 상에 하부금속배선(2) 및 하부전극(3)을 차례로 형성한다.First, a normal semiconductor device process is performed on the semiconductor substrate 1, an interlayer insulating film (not shown) is formed, and then a lower metal wiring 2 and a lower electrode 3 are sequentially formed on the interlayer insulating film.
다음, 하부전극(3) 상에 유전체층(4) 및 상부전극(5)을 차례로 증착한 다음,상부전극(5) 상에 감광막 패턴을 형성하고 감광막 패턴을 마스크로 하여 상부전극(5) 및 유전체층(4)을 식각하여 소정폭의 상부전극(5) 및 유전체층(4)을 남긴다. 여기서 하부전극(3), 유전체층(4), 및 상부전극(5)이 MIM 구조의 커패시터에 해당된다.Next, a dielectric layer 4 and an upper electrode 5 are sequentially deposited on the lower electrode 3, and then a photoresist pattern is formed on the upper electrode 5, and the upper electrode 5 and the dielectric layer are formed using the photoresist pattern as a mask. (4) is etched to leave the upper electrode 5 and the dielectric layer 4 of a predetermined width. Here, the lower electrode 3, the dielectric layer 4, and the upper electrode 5 correspond to a capacitor of the MIM structure.
다음, 상부전극(5) 및 하부전극(3)의 상부 전면에 산화막(6)을 증착하고 상면을 평탄화한 후, 감광막 패턴을 마스크로 하고 하부전극(3) 및 상부전극(5) 상의 산화막(6)을 소정영역 식각하여, 하부전극(3) 및 상부전극(5)의 표면을 개방하는 소정폭의 비아홀(100A, 100B)을 형성한다. 이 때, 하부전극(3) 표면을 개방하는 비아홀(100A)은 상부전극(5) 표면을 개방하는 비아홀(100B)에 비해 더 깊기 때문에, 상부전극(5) 표면을 개방하는 비아홀(100B)이 먼저 형성된 후 산화막(6)을 C 만큼 더 식각하여 하부전극(3) 표면을 개방하는 비아홀(100A)을 형성한다.Next, an oxide film 6 is deposited on the upper surface of the upper electrode 5 and the lower electrode 3 and the top surface is planarized. Then, the photoresist pattern is used as a mask and the oxide film on the lower electrode 3 and the upper electrode 5 ( 6) is etched into a predetermined region to form via holes 100A and 100B having predetermined widths that open the surfaces of the lower electrode 3 and the upper electrode 5. At this time, since the via hole 100A that opens the surface of the lower electrode 3 is deeper than the via hole 100B that opens the surface of the upper electrode 5, the via hole 100B that opens the surface of the upper electrode 5 is formed. After the first formation, the oxide film 6 is further etched by C to form a via hole 100A that opens the lower electrode 3 surface.
그러나, 산화막(6)을 C 만큼 더 식각하는 동안에 이미 형성이 완료된 상부전극(5) 표면을 개방하는 비아홀(100B)의 하부에서는 과도한 식각이 이루어지게 되고, 특히 비아홀(100B) 바닥의 모서리 부분인 D 부분에서 손상이 발생한다.However, while etching the oxide film 6 further by C, excessive etching is performed in the lower part of the via hole 100B that opens the surface of the upper electrode 5 which has already been formed, in particular, the edge portion of the bottom of the via hole 100B. Damage occurs in part D.
다음, 비아홀을 통해 노출된 하부전극(3)과 상부전극(5)을 포함하여 산화막(6)의 상부 전면에, 비아홀(100A, 100B)을 충분히 매립하도록 금속막(7)을 증착한 후, 산화막(6)의 상면이 노출될 때까지 평탄화하며 평탄화된 상면에 금속물질을 형성하고 이를 패터닝하여 상부금속배선(8)을 형성한다.Next, after the metal film 7 is deposited to sufficiently fill the via holes 100A and 100B on the entire upper surface of the oxide film 6 including the lower electrode 3 and the upper electrode 5 exposed through the via holes, The upper surface of the oxide film 6 is flattened and a metal material is formed on the flattened upper surface and patterned to form the upper metal wiring 8.
그러나, 상기한 바와 같은 종래 방법에서는 비아홀(100A, 100B)의 깊이가 서로 다르기 때문에 깊이가 얕은 비아홀인 상부전극(5) 표면을 개방하는비아홀(100B)의 하부 및 모서리 D 부분에 과도 식각 및 손상이 발생하여 여기에는 비아홀(100B)을 매립하는 금속막(7)이 균일하게 형성되지 않는다.However, in the conventional method as described above, since the depths of the via holes 100A and 100B are different from each other, excessive etching and damage to the lower portion and the corner D portion of the via hole 100B opening the surface of the upper electrode 5, which are shallow via holes, are performed. This occurs and the metal film 7 which fills the via hole 100B is not formed uniformly.
따라서, 상부금속배선(8)을 통해 흘러온 전류가 상부전극(5)으로 일정하게 흐를 수 없게 되며, 이로 인해 커패시터의 안정적인 동작이 방해되고 반도체 소자의 오동작이 유발되는 등 소자의 신뢰성이 저하되는 문제점이 있었다.Therefore, the current flowing through the upper metal wiring 8 cannot flow uniformly to the upper electrode 5, thereby preventing the stable operation of the capacitor and causing malfunction of the semiconductor device. There was this.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 비아 단차에 기인한 금속막의 불균일성을 방지하여 반도체 소자의 신뢰성을 향상시키는 데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to improve the reliability of a semiconductor device by preventing the nonuniformity of the metal film due to the via step.
도 1은 종래 반도체 소자를 도시한 단면도이다.1 is a cross-sectional view showing a conventional semiconductor device.
도 2a 내지 도 2c는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 커패시터의 상부전극 상에 희생절연막을 증착하여 비아홀 식각시 상부전극의 손상을 방지하는 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized by preventing the damage of the upper electrode during the via hole etching by depositing a sacrificial insulating film on the upper electrode of the capacitor.
이하, 본 발명에 따른 반도체 소자 및 그 제조 방법에 대해 상세히 설명한다. 도 2a 내지 도 2c는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail. 2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
본 발명에 따라 제조된 반도체 소자는 도 2c에 도시되어 있으며, 이에 도시된 바와 같이, 본 발명에 따른 반도체 소자에서는, 반도체 기판의 구조물 상에 하부금속배선이 형성되어 있고, 하부금속배선 상에는 하부전극, 유전체층, 및 상부전극이 소정폭으로 하부로부터 차례로 적층된 구조의 커패시터가 형성되어 있으며,커패시터 상에는 비아홀이 형성되어 있고, 비아홀의 내부에는 비아금속막이 매립되어 있으며, 비아홀의 외측방, 커패시터의 외부 및 하부금속배선 상에는 층간절연막이 형성되어 있으며, 비아금속막 및 층간절연막 상에는 상부금속배선이 형성되어 있는데, 이 때, 상부전극에서 비아홀과 접촉하는 부분을 제외한 나머지 영역 상에는 희생절연막이 형성되어 있고, 상부전극에서 비아홀과 접촉하는 부분은 소정두께 식각되어 있다.The semiconductor device manufactured according to the present invention is illustrated in FIG. 2C. As shown in the drawing, in the semiconductor device according to the present invention, a lower metal wiring is formed on a structure of a semiconductor substrate, and a lower electrode is formed on the lower metal wiring. The capacitor has a structure in which a dielectric layer and an upper electrode are sequentially stacked from the bottom to a predetermined width, a via hole is formed on the capacitor, a via metal film is embedded in the via hole, and an outer side of the via hole and the outside of the capacitor. And an interlayer insulating film is formed on the lower metal wiring, and an upper metal wiring is formed on the via metal film and the interlayer insulating film. At this time, a sacrificial insulating film is formed on the remaining regions of the upper electrode except for the portion in contact with the via hole. A portion of the upper electrode that contacts the via hole is etched by a predetermined thickness.
이 때, 희생절연막은 층간절연막에 비해 식각률이 낮은 물질로 이루어지는 것이 바람직하며, 상부전극에서 비아홀과 접촉하는 부분이 식각된 소정 두께란 상부전극 총 두께의 1/5 이하인 것이 바람직하다.In this case, the sacrificial insulating film is preferably made of a material having a lower etching rate than the interlayer insulating film, and the predetermined thickness where the portion of the upper electrode contacts the via hole is preferably 1/5 or less of the total thickness of the upper electrode.
또한, 비아홀의 내벽에는 제1베리어금속막이 형성될 수 있고, 비아금속막 및 층간절연막 상에는 제2베리어금속막이 형성될 수 있다.In addition, a first barrier metal film may be formed on an inner wall of the via hole, and a second barrier metal film may be formed on the via metal film and the interlayer insulating film.
유전체층은 하부전극으로부터 희생절연막까지의 총 두께에 대해 1/2 이하인 것이 바람직하며, 실리콘나이트라이드, 실리콘옥시나이트라이드, 및 실리콘카본나이트라이드 중의 어느 한 물질로 이루어질 수도 있고, 실리콘나이트라이드층, 실리콘옥시나이트라이드층, 및 실리콘카본나이트라이드층 중에서 선택된 2종 이상의 층이 적층된 구조로 이루어질 수도 있으며, 유전체층으로서 실리콘옥시나이트라이드를 사용할 때에는, 실리콘옥시나이트라이드 상에 100Å 이하의 두께로 산화막을 형성하는 것이 바람직하다.The dielectric layer is preferably 1/2 or less of the total thickness from the lower electrode to the sacrificial insulating film, and may be made of any one of silicon nitride, silicon oxynitride, and silicon carbon nitride, and may be formed of a silicon nitride layer or silicon. Two or more layers selected from an oxynitride layer and a silicon carbon nitride layer may be laminated. When an silicon oxynitride is used as the dielectric layer, an oxide film is formed on the silicon oxynitride to a thickness of 100 kPa or less. It is desirable to.
비아금속막은 텅스텐으로 이루어지는 것이 바람직하다.The via metal film is preferably made of tungsten.
그러면, 상기한 바와 같은 본 발명의 반도체 소자를 제조하는 방법에 대해상세히 설명한다.Then, the method of manufacturing the semiconductor device of the present invention as described above will be described in detail.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판(11)의 상부에 통상의 반도체 소자 공정을 진행하고 제1층간절연막(12)을 형성한 다음, 제1층간절연막(12) 상에 하부금속배선(13), 하부전극(14), 유전체층(15), 상부전극(16), 및 희생절연막(17)을 차례로 형성한다.First, as shown in FIG. 2A, a conventional semiconductor device process is performed on the semiconductor substrate 11 to form a first interlayer insulating film 12, and then a lower metal wiring on the first interlayer insulating film 12. (13), the lower electrode 14, the dielectric layer 15, the upper electrode 16, and the sacrificial insulating film 17 are sequentially formed.
이 때, 상부전극 형성 전에 플라즈마 처리를 수행하여 유전체층 표면의 이물질을 제거할 수 있다. 또한, 유전체층은 하부전극으로부터 희생절연막까지의 총 두께에 대해 1/2 이하의 두께로 형성하는 것이 바람직하며, 이러한 유전체층은 실리콘나이트라이드, 실리콘옥시나이트라이드, 및 실리콘카본나이트라이드 중의 어느 한 물질을 사용하여 형성하거나, 또는 실리콘나이트라이드층, 실리콘옥시나이트라이드층, 및 실리콘카본나이트라이드층 중에서 선택된 2종 이상의 층이 적층된 구조로 형성할 수 있는데, 실리콘옥시나이트라이드를 사용할 경우에는, 실리콘옥시나이트라이드 상에 100Å 이하의 두께로 산화막을 형성하는 것이 바람직하다.At this time, the plasma treatment may be performed before the upper electrode is formed to remove foreign substances on the surface of the dielectric layer. In addition, the dielectric layer is preferably formed to a thickness of 1/2 or less of the total thickness from the lower electrode to the sacrificial insulating film, and the dielectric layer may be formed of any one of silicon nitride, silicon oxynitride, and silicon carbon nitride. It can be formed by using or a structure in which two or more layers selected from a silicon nitride layer, a silicon oxynitride layer, and a silicon carbon nitride layer are laminated. In the case of using silicon oxynitride, It is preferable to form an oxide film on the nitride with a thickness of 100 GPa or less.
상기한 구조에서, 하부전극(14), 유전체층(15), 및 상부전극(16)은 MIM 구조의 커패시터에 해당된다.In the above structure, the lower electrode 14, the dielectric layer 15, and the upper electrode 16 correspond to a capacitor of the MIM structure.
이어서, 희생절연막(17)의 상부 전면에 감광막을 도포하고 노광 및 현상하여 소정폭의 감광막만을 남기고 나머지를 식각함으로써 감광막 패턴(18)을 형성한다.Subsequently, a photoresist film is coated on the entire upper surface of the sacrificial insulation film 17, and the photoresist pattern 18 is formed by etching and exposing the photoresist film, leaving only the photoresist film having a predetermined width.
다음, 감광막 패턴(18)을 마스크로 하여 상면이 노출된 희생절연막(17), 상부전극(16), 및 유전체층(15) 소정부분을 식각하여, 도 2b에 도시된 바와 같이 희생절연막(17), 상부전극(16) 및 유전체층(15)을 소정폭으로 남긴 후, 감광막패턴(18)을 제거하고 세정공정을 수행한다.Next, by using the photoresist pattern 18 as a mask, predetermined portions of the sacrificial insulating layer 17, the upper electrode 16, and the dielectric layer 15 having the upper surface exposed are etched, and as shown in FIG. 2B, the sacrificial insulating layer 17 is etched. After leaving the upper electrode 16 and the dielectric layer 15 at a predetermined width, the photoresist pattern 18 is removed and a cleaning process is performed.
이어서, 희생절연막(17)을 포함하여 하부전극(14)의 상부 전면에 산화막 등으로 이루어진 제2층간절연막(19)을 두껍게 증착한다. 제2층간절연막(19)의 증착 후에는 화학기계적 연마하여 그 상면을 평탄화할 수 있으며, 평탄화 후에는 400~600℃의 온도로 열처리할 수 있다.Subsequently, the second interlayer insulating film 19 made of an oxide film or the like is thickly deposited on the entire upper surface of the lower electrode 14 including the sacrificial insulating film 17. After the deposition of the second interlayer insulating film 19, the upper surface of the second interlayer insulating film 19 may be flattened by chemical mechanical polishing, and after the planarization, the second interlayer insulating film 19 may be heat treated at a temperature of 400 to 600 ° C.
이어서, 평탄화된 제2층간절연막(19)의 상면에 감광막을 도포하고 노광 및 현상하여 비아로 예정된 부분의 제2층간절연막(19) 상면을 노출시키는 감광막 패턴(20)을 형성한다.Subsequently, a photosensitive film is coated on the top surface of the planarized second interlayer insulating film 19, and the photosensitive film pattern 20 is formed to expose and expose the top surface of the second interlayer insulating film 19 in a portion intended as a via.
다음, 감광막 패턴(20)을 마스크로 하여 상면이 노출된 제2층간절연막(19) 부분을 건식식각하여 하부전극(14)의 표면을 개방하는 소정폭의 비아홀(200A) 및 희생절연막(17)의 표면을 개방하는 소정폭의 비아홀(200B)을 형성한다.Next, a portion of the second interlayer insulating film 19 having the upper surface exposed is dry-etched using the photoresist pattern 20 as a mask to open the surface of the lower electrode 14 and the sacrificial insulating film 17 having a predetermined width. A via hole 200B having a predetermined width to open the surface of the semiconductor device is formed.
이 때, 하부전극(14) 표면을 개방하는 비아홀(200A)은 희생절연막(17) 표면을 개방하는 비아홀(200B)에 비해 더 깊기 때문에, 희생절연막(17) 표면을 개방하는 비아홀(200B)이 먼저 형성된 후 두 비아홀 간의 단차인 C'만큼 제2층간절연막(19)을 더 식각하여 희생절연막(17) 표면을 개방하는 비아홀(200B)을 형성하는데, 제2층간절연막(19)을 C'만큼 더 식각하는 동안에 희생절연막(17)도 식각된다.In this case, since the via hole 200A opening the surface of the lower electrode 14 is deeper than the via hole 200B opening the surface of the sacrificial insulating film 17, the via hole 200B opening the surface of the sacrificial insulating film 17 is formed. First, the second interlayer insulating film 19 is further etched by C ', which is a step between two via holes, to form a via hole 200B that opens the surface of the sacrificial insulating film 17. The second interlayer insulating film 19 is formed by C'. During further etching, the sacrificial insulating film 17 is also etched.
그러나, 희생절연막(17)은 제2층간절연막(19)에 비해 식각률이 낮은 물질로 이루어지기 때문에, 제2층간절연막(19)을 C'만큼 더 식각하는 동안에 희생절연막(17) 및 그 하부의 상부전극(16) 최상층이 얇게, 즉 C'보다 얇은 두께로식각되어, 최종적인 비아홀(200B)의 바닥에 상부전극(16)의 표면이 노출된다. 여기서, 상부전극(16)이 식각되는 두께는 상부전극 총 두께의 1/5 이하로 하는 것이 바람직하다.However, since the sacrificial insulating film 17 is made of a material having a lower etching rate than that of the second interlayer insulating film 19, the sacrificial insulating film 17 and the lower portion of the sacrificial insulating film 17 may be further etched by C ′. The uppermost layer of the upper electrode 16 is etched thinner, that is, thinner than C ', so that the surface of the upper electrode 16 is exposed at the bottom of the final via hole 200B. Here, the thickness of the upper electrode 16 to be etched is preferably 1/5 or less of the total thickness of the upper electrode.
다음, 감광막 패턴(20)을 제거하고 세정공정을 수행한 다음, 비아홀(200A, 200B)의 내벽에 제1베리어금속막(21)을 증착하고, 제1베리어금속막(21) 상에 텅스텐 등의 비아금속막(22)을 증착하여 비아홀(200A, 200B)의 내부를 완전히 매립한다. 비아금속막(22)의 증착 후에는 제2층간절연막(19)의 상면이 노출될 때까지 화학기계적 연마하여 상면을 평탄화시킬 수 있으며, 평탄화 후에는 400~600℃의 온도로 열처리할 수 있다.Next, the photoresist layer pattern 20 is removed and a cleaning process is performed. Then, the first barrier metal layer 21 is deposited on the inner walls of the via holes 200A and 200B, and tungsten or the like is formed on the first barrier metal layer 21. The via metal film 22 is deposited to completely fill the inside of the via holes 200A and 200B. After the deposition of the via metal film 22, the upper surface of the second interlayer insulating film 19 may be chemically polished until the upper surface of the second interlayer insulating film 19 is exposed, and the upper surface may be planarized. After the planarization, the heat treatment may be performed at a temperature of 400 to 600 ° C.
이어서, 평탄화된 상면에 제2베리어금속막(23) 및 금속배선막(24)을 차례로 증착하고 이들을 패터닝하여 상부금속배선(23, 24)을 형성한다. 이 때 제2베리어금속막(23) 형성 이전에, 플라즈마 식각을 수행하여 비아금속막(22) 표면의 이물질을 제거할 수 있다. 이로써, 상부금속배선(23, 24)이 비아금속막(22)을 통해 커패시터의 상부전극(16)과 연결된다.Subsequently, the second barrier metal film 23 and the metal wiring film 24 are sequentially deposited on the flattened top surface and patterned to form the upper metal wirings 23 and 24. In this case, before the formation of the second barrier metal layer 23, plasma etching may be performed to remove foreign substances on the surface of the via metal layer 22. Thus, the upper metal wirings 23 and 24 are connected to the upper electrode 16 of the capacitor through the via metal film 22.
상술한 바와 같이, 본 발명에서는 커패시터의 상부전극 상에 희생절연막을 증착하기 때문에, 종래 비아홀 식각시 비아홀의 바닥과 접촉하는 MIM 구조 커패시터의 상부전극이 소정영역 손상되어 손상된 영역에 증착되는 비아홀 매립 금속막이 균일하게 형성되지 못하던 것을 방지하는 효과가 있다.As described above, in the present invention, since the sacrificial insulating film is deposited on the upper electrode of the capacitor, the via hole buried metal in which the upper electrode of the MIM structure capacitor contacting the bottom of the via hole during the conventional via hole etching is damaged and deposited in the damaged area. There is an effect of preventing the film from being formed uniformly.
따라서, 커패시터의 안정적인 동작을 가능하게 하고, 이로써 소자의 신뢰성을 향상시키는 효과가 있다.Therefore, the stable operation of the capacitor is possible, thereby improving the reliability of the device.
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| US7554146B2 (en) | 2004-12-27 | 2009-06-30 | Samsung Electronics Co., Ltd. | Metal-insulator-metal capacitor and method of fabricating the same |
| KR100684705B1 (en) * | 2005-06-07 | 2007-02-20 | 후지쯔 가부시끼가이샤 | Semiconductor device having capacitor with upper electrode of conductive oxide and its manufacture method |
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