KR20040008723A - Method for fabricating capacitor of semiconductor device - Google Patents
Method for fabricating capacitor of semiconductor device Download PDFInfo
- Publication number
- KR20040008723A KR20040008723A KR1020020042397A KR20020042397A KR20040008723A KR 20040008723 A KR20040008723 A KR 20040008723A KR 1020020042397 A KR1020020042397 A KR 1020020042397A KR 20020042397 A KR20020042397 A KR 20020042397A KR 20040008723 A KR20040008723 A KR 20040008723A
- Authority
- KR
- South Korea
- Prior art keywords
- upper electrode
- doped silicon
- concentration
- capacitor
- electrode
- Prior art date
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 28
- 239000010703 silicon Substances 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 230000009977 dual effect Effects 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 5
- 238000011065 in-situ storage Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 230000007423 decrease Effects 0.000 description 10
- 238000005137 deposition process Methods 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 5
- 230000008021 deposition Effects 0.000 description 2
- 238000011982 device technology Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체소자의 캐패시터 제조방법에 관한 것으로서, 보다 상세하게는 PH3샤워(shower) 및 이중 증착을 이용한 캐패시터의 상부전극을 형성하는 반도체소자의 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device for forming an upper electrode of a capacitor using a PH 3 shower and double deposition.
현재 양산중인 캐패시터 구조는 MPS(meta-stable poly silicon)을 하부전극으로, 고농도 도핑된 Si을 상부전극으로 사용하고 있다. 이때, 상부전극과 하부전극의 P 농도를 높일수록 셀 캐패시턴스와 파괴전압(breakdown voltage)은 증가하기에 하부전극은 P 농도를 최대한 높게 사용한다.Currently, the capacitor structure in mass production uses meta-stable poly silicon (MPS) as a lower electrode and highly doped Si as an upper electrode. In this case, as the P concentration of the upper electrode and the lower electrode is increased, the cell capacitance and breakdown voltage increase, so the lower electrode uses the P concentration as high as possible.
그러나, 상부전극의 경우에는 캐패시터의 플레이트 노드로 사용하고 있어 디바이스 기술에 따라 일정 값 이하의 폴리실리콘 Rs(sheet resistance)를 요구하고 있어 상대적으로 하부전극보다 낮은 P 농도로 상부전극을 증착한다.However, the upper electrode is used as a plate node of the capacitor, and according to the device technology, polysilicon Rs (sheet resistance) of a predetermined value or less is required, so that the upper electrode is deposited at a lower P concentration than the lower electrode.
이러한 이유로 플레이트 노드에 네거티브 바이어스를 인가할 때보다 포지티브 바이어스를 인가할 때 P농도 차이에 의해 셀캐패시턴스가 감소하고 파괴전압이감소한다. 이때, 하부전극의 농도를 낮추어 상부전극과 동일한 P 농도로 조정하면 포지티브 바이어스 인가시 발생하는 셀 캐패시턴스 및 파괴전압 감소는 해결되지만 절대값이 감소하는 문제가 있다.For this reason, when the positive bias is applied to the plate node, the cell capacitance decreases and the breakdown voltage decreases due to the P concentration difference. At this time, if the concentration of the lower electrode is lowered and adjusted to the same P concentration as the upper electrode, the decrease in cell capacitance and breakdown voltage generated when the positive bias is applied is solved, but the absolute value decreases.
한편, 동일한 온도와 동일한 압력조건하에서의 도프된 폴리실리콘의 Rs 특성에 대해 도 1을 참조하여 설명하면, 첫째로 폴리실리콘의 두께 증가와 반비례하고, 두번째로 P농도와의 관계는 도 1에서와 같이 일정농도까지는 Rs가 감소하지만, 과포화 이후는 다시 Rs가 증가한다.On the other hand, the Rs characteristics of the doped polysilicon under the same temperature and the same pressure condition will be described with reference to FIG. 1, firstly inversely proportional to the increase in thickness of the polysilicon, and secondly, the relationship between the P concentration and Rs decreases until a certain concentration, but increases again after supersaturation.
여기서, 두 번째 특성에서 폴리실리콘 특성으로 P 농도를 증가하면 상부전극의 Rs가 증가하기에 단일층을 증착할 경우 P 농도를 낮추어야 한다. 이러한 현상은 셀크기가 감소함에 따라 단위 셀에서 상부전극으로 작용되는 폴리실리콘의 두께가 감소하기에 더 심화되고 있다.Here, if the P concentration is increased by the polysilicon characteristic in the second characteristic, the P concentration should be lowered when the single layer is deposited because the Rs of the upper electrode is increased. This phenomenon is further exacerbated as the thickness of the polysilicon acting as the upper electrode in the unit cell decreases as the cell size decreases.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 상부전극/유전체 계면의 P 농도를 증가하여 캐패시터에 포지티브 바이어스를 인가할 때 상부전극의 디플리션(depletion)으로 발생하는 셀 캐패시턴스 감소를 방지하고 홀전류(hole current)를 억제하여 파괴전압을 증가시킬 수 있는 반도체소자의 캐패시터 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, a cell caused by depletion of the upper electrode when applying a positive bias to the capacitor by increasing the P concentration of the upper electrode / dielectric interface It is an object of the present invention to provide a method of manufacturing a capacitor of a semiconductor device capable of preventing a decrease in capacitance and increasing a breakdown voltage by suppressing a hole current.
또한, 본 발명의 다른 목적은, 전극/유전체 계면사이의 P농도만 증가하고 상부전극 벌크의 P농도는 저농도 도핑된 실리콘으로 증착하여 고집적 소자에서 요구하는 낮은 플레이트 노드 Rs를 구현할 수 있는 반도체소자의 캐패시터 제조방법을 제공함에 있다.In addition, another object of the present invention is to increase the P concentration between the electrode / dielectric interface, and the P concentration of the bulk of the upper electrode is deposited with low concentration doped silicon to implement the low plate node Rs required for the highly integrated device. It is to provide a capacitor manufacturing method.
도 1은 일반적인 도프트 폴리실리콘의 P 농도에 따른 Rs 특성을 도시한 그래프.1 is a graph showing the Rs characteristics according to the P concentration of a typical doped polysilicon.
도 2 내지 도 4는 본 발명의 일실시예에 따른 반도체소자의 캐패시터 제조방법을 설명하기 위한 공정단면도.2 to 4 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.
도 5는 본 발명의 다른 실시예에 따른 반도체소자의 캐패시터 제조방법을 설명하기 위한 공정단면도.5 is a cross-sectional view illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with another embodiment of the present invention.
도 6은 본 발명에 따른 플레이트전극 형성시에 이중 증착공정을 적용함에 따른 △Cs 변화를 도시한 그래프.Figure 6 is a graph showing the change in ΔCs by applying a dual deposition process when forming a plate electrode according to the present invention.
도 7은 본 발명에 따른 플레이트전극 형성시에 이중 증착공정을 적용함에 따른 포지티브 바이어스 증가 및 캐패시턴스의 변화를 나타낸 그래프.7 is a graph showing a positive bias increase and a change in capacitance by applying a dual deposition process in forming a plate electrode according to the present invention.
도 8은 본 발명에 따른 플레이트 전극 형성시에 이중 증착공정을 적용함에 따른 Rs 변화를 나타낸 그래프.8 is a graph showing a change in Rs by applying a dual deposition process when forming a plate electrode according to the present invention.
도 9는 본 발명에 따른 플레이트 전극 형성시에 이중 증착공정을 적용함에 따른 P농도 프로파일을 나타낸 그래프.9 is a graph showing a P concentration profile according to applying a dual deposition process in forming a plate electrode according to the present invention.
[도면부호의설명][Description of Drawing Reference]
11, 21 : 하부전극 13, 23 : 유전체막11, 21: lower electrode 13, 23: dielectric film
15 : 고농도 도핑 실리콘막17 : 저농도 도핑 실리콘막15: high concentration doped silicon film 17: low concentration doped silicon film
19, 27 : 상부전극25 : PH3샤워막19, 27: upper electrode 25: PH 3 shower film
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 캐패시터 제조 방법은, 반도체기판상에 하부전극을 형성하는 단계; 상기 하부전극상에 유전체막을 형성하는 단계; 및 상기 유전체막상에 고농도 도핑 실리콘막과 저농도 도핑 실리콘 막을 적층하여 이중 구조의 상부전극을 형성하는 단계;를 포함하여 구성되는 것을 특징으로한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: forming a lower electrode on a semiconductor substrate; Forming a dielectric film on the lower electrode; And stacking a high concentration doped silicon film and a low concentration doped silicon film on the dielectric film to form an upper electrode having a dual structure.
(실시예)(Example)
이하, 본 발명에 따른 반도체소자의 캐패시터 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2 내지 도 4는 본 발명의 일실시예에 따른 반도체소자의 캐패시터 제조방법을 설명하기 위한 공정단면도이고, 도 5는 본 발명의 다른 실시예에 따른 반도체소자의 캐패시터 제조방법을 설명하기 위한 공정단면도이다.2 to 4 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention, and FIG. 5 is a process illustrating a method of manufacturing a capacitor of a semiconductor device according to another embodiment of the present invention. It is a cross section.
도 6은 본 발명에 따른 플레이트전극 형성시에 이중 증착공정을 적용함에 따른 △Cs 변화를 도시한 그래프이다.6 is a graph illustrating a change in ΔCs by applying a dual deposition process when forming a plate electrode according to the present invention.
도 7은 본 발명에 따른 플레이트전극 형성시에 이중 증착공정을 적용함에 따른 포지티브 바이어스 증가 및 캐패시턴스의 변화를 나타낸 그래프이다.7 is a graph showing a positive bias increase and a change in capacitance according to the dual deposition process in forming a plate electrode according to the present invention.
도 8은 본 발명에 따른 플레이트 전극 형성시에 이중 증착공정을 적용함에 따른 Rs 변화를 나타낸 그래프이다.8 is a graph showing a change in Rs by applying a dual deposition process when forming a plate electrode according to the present invention.
도 9는 본 발명에 따른 플레이트 전극 형성시에 이중 증착공정을 적용함에 따른 P농도 프로파일을 나타낸 그래프이다.9 is a graph showing a P concentration profile according to applying a dual deposition process when forming a plate electrode according to the present invention.
본 발명에 따른 반도체소자의 캐패시터 제조방법은, 도 2에 도시된 바와같이, 반도체기판(미도시)상에 폴리실리콘 또는 MPS 전극을 이용한 3차원, 예를들어 실린더, 오목형 등의 캐패시터 구조의 하부전극(11)을 형성한다.As shown in FIG. 2, a method of manufacturing a capacitor of a semiconductor device according to the present invention includes a capacitor structure of three-dimensional, for example, cylinder, concave, etc. using polysilicon or MPS electrode on a semiconductor substrate (not shown). The lower electrode 11 is formed.
그다음, 도 3에 도시된 바와같이, 세정공정을 진행하고 이어 상기 하부전극(11)상에 유전체막(13)을 증착한다.Next, as shown in FIG. 3, the cleaning process is performed, and then a dielectric film 13 is deposited on the lower electrode 11.
이어서, 도 4에 도시된 바와같이, 상기 유전체막(13)상에 고농도 도핑된 실리콘층(15)과 저농도 도핑된 실리콘층(17)을 적층한다. 이때, 상기 고농도 도핑된 실리콘층(15)과 저농도 도핑된 실리콘층(17)은 이중 구조의 상부전극(19)을 구성한다.Subsequently, as shown in FIG. 4, a heavily doped silicon layer 15 and a lightly doped silicon layer 17 are stacked on the dielectric film 13. In this case, the heavily doped silicon layer 15 and the lightly doped silicon layer 17 constitute an upper electrode 19 having a dual structure.
또한, 일반적으로 하부전극의 P 농도를 1E21 원자/cc 이상으로 사용하고, 상부전극의 고농도 도핑된 실리콘은 1E21 원자/cc이상으로 증착하며, 저농도 도핑된 실리콘은 폴리실리콘의 시트저항(Rs)을 최적화시키기 위하여 P 농도를 1E21 원자 /cc 미만으로 증착한다.In general, the P concentration of the lower electrode is used at 1E21 atoms / cc or more, the heavily doped silicon of the upper electrode is deposited at 1E21 atoms / cc or more, and the low concentration doped silicon is used to increase the sheet resistance (Rs) of polysilicon. P concentrations are deposited below 1E21 atoms / cc for optimization.
이렇게 하면, 도 6에서와 같이, 플레이트 형성시에 이중 증착공정을 적용한 결과 그에 따른 △Cs 변화 즉, 네거티브 바이어스-포지티브 바이어스 바이어스 인가시 셀 캐패시턴스 차를 비교해 본 결과 포지티브 바이어스에서의 디플리션 (depletion) 억제효과가 있음을 알 수 있다.In this case, as shown in FIG. 6, when the dual deposition process is applied to form the plate, the difference in ΔCs, that is, the cell capacitance difference when applying the negative bias-positive bias bias is compared, and as a result, the depletion in the positive bias It can be seen that there is an inhibitory effect.
또한, 플레이트 형성시에 이중 증착공정을 적용한 결과 포지티브 바이어스가 증가되어 홀전류(hole current)의 억제로 바이어스가 0.3 V 증가함을 알 수 있다.In addition, as a result of applying the dual deposition process at the time of plate formation, it can be seen that the positive bias is increased and the bias is increased by 0.3 V due to the suppression of hole current.
그리고, 도 8에서와 같이, 벌크 농도가 동일한 상태에서 상부전극의 하부층만을 고농도 도핑된 실리콘으로 증착하면 Rs가 증가하기 때문에, 도 9에 도시된 바와같이, 벌크 농도를 감소시켜야 한다.In addition, as shown in FIG. 8, when only the lower layer of the upper electrode is deposited with highly doped silicon in the same bulk concentration, Rs increases, so that the bulk concentration should be reduced.
이때, 고농도 도핑된 실리콘층(15)의 두께는 약 30 내지 1000 Å으로 증착한다. 고농도 도핑된 실리콘층(15)이 너무 두꺼울 경우 플레이트 Rs 증가 문제가 있으며, 디램의 단위 셀내에서의 상부전극은 고집적 디바이스로 갈수록 셀크기가 작아지기에 300 Å 이하이면 충분하다.At this time, the thickness of the heavily doped silicon layer 15 is deposited to about 30 to 1000 kPa. If the heavily doped silicon layer 15 is too thick, there is a problem of increasing the plate Rs, and the upper electrode in the unit cell of the DRAM is 300 Å or less enough to decrease the cell size toward the highly integrated device.
또한, 상부전극(19)의 총 두께는 금속과의 콘택 등으로 약 1000 Å 이상으로 증착한다.In addition, the total thickness of the upper electrode 19 is deposited at about 1000 kPa or more by contact with a metal.
한편, 본 발명의 다른 실시예로서, 상부전극을 증착하기 전에 PH3샤워층(shower layer)을 유전체막(23)상에 형성한후 상부전극(27)을 증착한다. 이때, 본 발명의 다른 실시예에서 유전체막과 상부전극을 형성하는 공정은 상기에서 설명한 본 발명의 일실시예와 동일한 공정을 이용한다.Meanwhile, as another embodiment of the present invention, before depositing the upper electrode, a PH 3 shower layer is formed on the dielectric layer 23 and then the upper electrode 27 is deposited. In this case, the process of forming the dielectric film and the upper electrode in another embodiment of the present invention uses the same process as the embodiment of the present invention described above.
이때, 계면 P 농도를 증가하기 위하여 PH3가스만을 이용하여 샤워를 먼저 진행하므로써 도프트 폴리실리콘층보다 높은 P 농도를 계면에 형성할 수 있다. 도핑 폴리실리콘은 SiH4와 PH3을 동시에 주입하여 실리콘(Si)을 증착시키면서 P가 흡착되기에 P 농도의 한계가 있다. 그리고, PH3샤워후 상부전극 증착시에 본 발명의 일실시예와 같이, 고농도 도핑된 실리콘층과 저농도 도핑된 실리콘층의 이중 구조로 증착한다. 또한, PH3샤워와 도프트 실리콘(Si) 증착을 인-시튜로 동일 시스템에서 순차적으로 진행할 수도 있다.At this time, in order to increase the interfacial P concentration, a shower may be first formed using only PH 3 gas to form a higher P concentration at the interface than the doped polysilicon layer. Doped polysilicon has a limit of P concentration because P is adsorbed while depositing silicon (Si) by injecting SiH 4 and PH 3 simultaneously. When the upper electrode is deposited after the PH 3 shower, as in the embodiment of the present invention, the semiconductor layer is deposited in a double structure of a high concentration doped silicon layer and a low concentration doped silicon layer. In addition, the PH 3 shower and doped silicon (Si) deposition may be sequentially performed in-situ in the same system.
그리고, PH3샤워후 상부전극 증착시에 본 발명의 일실시예와 같이, 고농도 도핑된 실리콘층과 저농도 도핑된 실리콘층의 이중 구조로 증착할 수도 있다. 이는 PH3샤워에 의한 계면의 높은 P 농도가 후속 열적 공정에 상부전극으로 확산되는 것을 최소화하여 계면 P 농도 손실을 방지한다.In addition, when the upper electrode is deposited after the PH 3 shower, as in an embodiment of the present invention, a high concentration doped silicon layer and a low concentration doped silicon layer may be deposited in a dual structure. This minimizes the diffusion of the high P concentration at the interface by the PH 3 shower to the upper electrode in subsequent thermal processes to prevent loss of the interface P concentration.
상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 캐패시터 제조방법에 의하면, 상부전극/유전체 계면의 P농도를 증가시켜 캐패시터에 포지티브 바이어스를 인가할 때 상부전극의 디플레이션으로 발생하는 셀 캐패시턴스 감소를 방지할 수 있다.As described above, according to the method of fabricating a capacitor of a semiconductor device according to the present invention, the P concentration of the upper electrode / dielectric interface is increased to prevent a decrease in cell capacitance caused by deflation of the upper electrode when a positive bias is applied to the capacitor. can do.
또한, 본 발명에 의하면, 홀전류(hole current)을 억제하여 파괴전압 (breakdown voltage)을 증가시킬 수 있다.Further, according to the present invention, the breakdown voltage can be increased by suppressing the hole current.
그리고, 본 발명에 의하면, 전극/유전체 계면사이의 P농도만 증가시키고 상부전극 벌크의 P농도는 저도핑된 Si으로 증착하기에 디바이스 기술에서 요구하는 낮은 플레이트 노드 Rs를 구현할 수 있다.In addition, according to the present invention, it is possible to implement the low plate node Rs required by the device technology to increase only the P concentration between the electrode / dielectric interface and the P concentration of the upper electrode bulk with low-doped Si.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0042397A KR100451517B1 (en) | 2002-07-19 | 2002-07-19 | Method for fabricating capacitor of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0042397A KR100451517B1 (en) | 2002-07-19 | 2002-07-19 | Method for fabricating capacitor of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20040008723A true KR20040008723A (en) | 2004-01-31 |
| KR100451517B1 KR100451517B1 (en) | 2004-10-06 |
Family
ID=37317751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2002-0042397A KR100451517B1 (en) | 2002-07-19 | 2002-07-19 | Method for fabricating capacitor of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100451517B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101033470B1 (en) * | 2010-07-26 | 2011-05-09 | 태성전기(주) | Heat exchange pipe manufacturing equipment for freezing cycle |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980068062A (en) * | 1997-02-14 | 1998-10-15 | 김광호 | Capacitor Manufacturing Method of Semiconductor Device |
| KR100252058B1 (en) * | 1997-12-30 | 2000-04-15 | 윤종용 | A capacitor having storage node with rugged surface and method for fabricating thereof |
| KR20010010579A (en) * | 1999-07-21 | 2001-02-15 | 김영환 | Alarm monitoring apparatus and method of channel decording circuit pack of base station |
| KR20010038768A (en) * | 1999-10-27 | 2001-05-15 | 박종섭 | Method for forming capacitor of semiconductor device |
| US6507063B2 (en) * | 2000-04-17 | 2003-01-14 | International Business Machines Corporation | Poly-poly/MOS capacitor having a gate encapsulating first electrode layer |
| KR20010105797A (en) * | 2000-05-18 | 2001-11-29 | 윤종용 | Capacitor in semiconductor device and method for manufacturing thereof |
-
2002
- 2002-07-19 KR KR10-2002-0042397A patent/KR100451517B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101033470B1 (en) * | 2010-07-26 | 2011-05-09 | 태성전기(주) | Heat exchange pipe manufacturing equipment for freezing cycle |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100451517B1 (en) | 2004-10-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4931897A (en) | Method of manufacturing semiconductor capacitive element | |
| KR100207444B1 (en) | Capacitor fabrication method and its device having high dielectronic layer and electrode | |
| KR20000052343A (en) | Hemispherical grain capacitor and forming method thereof | |
| JP2601022B2 (en) | Method for manufacturing semiconductor device | |
| KR0186069B1 (en) | Method of manufacturing capacitor of stacked dram cell | |
| KR100451517B1 (en) | Method for fabricating capacitor of semiconductor device | |
| GB2285338A (en) | Method for fabricating capacitor | |
| KR100376979B1 (en) | Method for forming capacitor electrode | |
| KR20040061815A (en) | Method for fabricating capacitor of semiconductor device | |
| KR100250750B1 (en) | Method for fabricating a capacitor of semiconductor device | |
| KR100448238B1 (en) | Semiconductor device manufacturing method | |
| KR100413755B1 (en) | Method for fabricating capacitor of semiconductor device and capacitor fabricated thereby | |
| KR101061169B1 (en) | Capacitor Formation Method of Semiconductor Device | |
| KR100261212B1 (en) | Method for manufacturing capacitor of semiconductor device | |
| KR100447107B1 (en) | The structure of plug poly silicon layer in semiconductor device | |
| KR100506873B1 (en) | Method for fabricating capacitor of semiconductor device | |
| JPH04209570A (en) | Manufacture of semiconductor element | |
| JPH0246756A (en) | Manufacture of semiconductor capacitor | |
| KR940010333A (en) | Semiconductor memory device and manufacturing method thereof | |
| KR20020017834A (en) | Method for manufacturing capacitor in semiconductor device | |
| CN117832204A (en) | Method for manufacturing semiconductor element | |
| KR20010005040A (en) | Method of fabricating storage node of capacitor in semiconductor device | |
| KR19990058613A (en) | Capacitor Manufacturing Method of Semiconductor Device | |
| KR20010005086A (en) | A method for fabricating capacitor in semiconductor device | |
| KR20000027844A (en) | Method for forming electrode of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100825 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |