KR20040004855A - A method for manufacturing a thin film transistor array panel - Google Patents

Abstract

PURPOSE: A method of manufacturing a thin film transistor array substrate is provided to improve contact characteristic of a thin film transistor and a pixel electrode. CONSTITUTION: A conductive material is deposited on a substrate(110) and patterned, to form gate lines. A gate insulating layer(140) is formed on the substrate. An amorphous semiconductor layer(150) having a channel is formed on the gate insulating layer. Doped amorphous resistant contact layer patterns(163,165) are formed on the semiconductor layer at both sides of the channel of the semiconductor layer. A conductive material is deposited on the gate insulating layer and semiconductor layer and patterned, to form data lines. The semiconductor layer and resistant contact layer are formed through photolithography using a photoresist pattern having the first part corresponding to the channel and the second part that corresponds to the semiconductor layer and thicker than the first part.

Description

A manufacturing method of a thin film transistor array substrate {A METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR ARRAY PANEL}

The present invention relates to a method for manufacturing a thin film transistor array substrate, and more particularly, to a method for manufacturing a thin film transistor array substrate using amorphous silicon as a semiconductor layer.

As one of the flat panel display devices which are widely used at present, a liquid crystal display device has two substrates on which a plurality of electrodes for generating an electric field are formed, a liquid crystal layer injected between the two substrates, and is attached to the outer surface of each substrate to emit light. 2. A display device including two polarizing plates for polarizing and controlling the amount of light transmitted by rearranging liquid crystal molecules of a liquid crystal layer by applying a voltage to an electrode. This is because the arrangement of molecules changes when a voltage is applied among various properties of the liquid crystal. In a liquid crystal display device using light transmission or reflection, the liquid crystal does not emit light and thus requires a light source on its own or externally.

In this case, a thin firm transistor array panel is used as a circuit board for driving each pixel independently in a liquid crystal display. The thin film transistor array substrate includes a scan signal line or a gate line for transmitting a scan signal and an image signal line or data line for transferring an image signal, and a thin film transistor and a thin film transistor connected to the gate line and the data line. And a pixel electrode used to display an image.

In this case, the thin film transistor has a semiconductor layer made of amorphous silicon or polycrystalline silicon, and may be divided into a top gate method and a bottom gate method according to a relative position of the gate electrode and the semiconductor layer. In this case, in the case of the amorphous silicon thin film transistor substrate, a bottom gate method in which the gate electrode is positioned below the semiconductor layer is mainly used, and in the case of the polysilicon thin film transistor substrate, the gate electrode is the semiconductor around the gate insulating film. The top gate method located above the layer is mainly used. In the bottom gate type thin film transistor, an n-type or p-type is formed between the semiconductor layer and the source and drain electrodes to minimize contact resistance between the semiconductor layer and the source and drain electrodes. Interfering with the ohmic contact layer doped with a high concentration of impurities.

However, in the process of manufacturing a bottom gate type thin film transistor, the resistive contact layer is etched by dry etching using a data line as an etch mask to form a channel portion of the semiconductor layer, thereby exposing the semiconductor layer between the source and drain electrodes. The problem arises in that the data wiring is damaged and the contact characteristics with the pixel electrodes formed later are degraded.

On the other hand, in the manufacturing method of the liquid crystal display device, the substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, it is preferable to reduce the number of etching processes in order to reduce the production cost.

An object of the present invention is to provide a method of manufacturing a thin film transistor array substrate that can improve the contact characteristics of the thin film transistor and the pixel electrode.

In addition, another object of the present invention is to simplify the manufacturing method of the thin film transistor array substrate.

1 is a layout view of a thin film transistor array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II ',

3A, 5A, 7A, and 8A are layout views of a thin film transistor substrate illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, according to a process sequence thereof.

3B is a cross-sectional view taken along the line IIIb-IIIb ′ in FIG. 3A;

FIG. 4 is a cross-sectional view taken along line IIIb-IIIb 'of FIG. 3A and illustrates the next step of FIG. 3B;

FIG. 5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A and illustrating the next step of FIG. 4;

FIG. 6 is a cross-sectional view taken along the line Vb-Vb 'of FIG. 5A and illustrating the next step of FIG. 5B;

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A and illustrating the next step of FIG. 6;

FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb 'of FIG. 8A and illustrates the next step of FIG. 7B.

In order to solve this problem, in the present invention, in the etching process of patterning the semiconductor layer, the portion corresponding to the channel portion is etched using a photosensitive film pattern having a thickness smaller than that corresponding to the semiconductor layer, The photosensitive film is removed to expose the channel portion of the semiconductor layer.

More specifically, a conductive material is stacked and patterned on the substrate to form a gate wiring including a gate line and a gate electrode, and a gate insulating film is stacked. Next, an ohmic contact layer of amorphous silicon having a channel portion and a doped amorphous silicon separated around the channel portion is formed on the gate insulating layer. Next, a conductive material is stacked and patterned on the gate insulating layer or the semiconductor layer to form a data line including a data line, a source electrode, and a drain electrode. In this case, the semiconductor layer and the ohmic contact layer are formed by a photolithography process using a photoresist pattern having a first portion corresponding to the channel portion and a semiconductor layer except the channel portion and having a second portion thicker than the first portion.

At this time, the photosensitive film pattern is preferably formed by exposure using one mask.

In order to form the semiconductor layer and the ohmic contact layer, first, an amorphous silicon layer and a doped amorphous silicon layer are sequentially stacked on the gate insulating layer, and a photoresist pattern is formed on the doped amorphous silicon layer. Subsequently, the first silicon layer and the doped amorphous silicon layer under the first portion are etched while the amorphous silicon layer and the doped amorphous silicon layer are etched using the photoresist pattern as an etching mask.

A pixel electrode connected to the data line may be further formed, and a passivation layer may be further formed between the data line and the pixel electrode.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A method of manufacturing a thin film transistor array substrate for a liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, the structure of a thin film transistor array substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II ′.

On the insulating substrate 110, a gate wiring made of a single film having a low resistance, such as silver or a silver alloy, aluminum or an aluminum alloy, or a multilayer film including the same is formed. The gate wire is connected to the gate line 121 and the gate line 121 extending in the horizontal direction and connected to the gate pad 125 and the gate line 121 which receive a gate signal from the outside and transfer the gate signal to the gate line. A gate electrode 123 of the thin film transistor. Here, when the gate wirings 121. 125. 123 are a multilayer film, the gate material 121. 125. 123 may include a pad material having excellent contact properties with other materials.

On the substrate 110, a gate insulating layer 140 made of silicon nitride (SiN _x ) covers the gate lines 121, 125, and 123.

A semiconductor layer 150 made of an amorphous silicon or polysilicon semiconductor is formed on the gate insulating layer 140 of the gate electrode 125, and silicide or n-type impurities are heavily doped on the semiconductor layer 150. Resistive contact layers 163 and 165 made of a material such as n + hydrogenated amorphous silicon are formed, respectively.

On the ohmic contact layers 163 and 165 and the gate insulating layer 140, a data line including a single layer having a low resistance, such as silver or a silver alloy, aluminum, or an aluminum alloy, or a multilayer film including the same is formed. The data line is formed in the vertical direction and crosses the gate line 121 to define a pixel, which is a branch of the data line 171 and the data line 171 and extends to the upper portion of the ohmic contact layer 163. ), Which is connected to one end of the data line 171 and is separated from the data pad 179 and the source electrode 173 for receiving an image signal from the outside, and is opposite to the source electrode 173 with respect to the gate electrode 123. The drain electrode 175 is formed on the ohmic contact layer 165. In addition, the data line may include an organic capacitor conductor pattern 177 overlapping the gate line 121 to improve the storage capacitance.

A passivation layer 180 made of silicon oxide, silicon nitride, or an organic material is formed on the data lines 171, 173, 175, 177, and 179 and the semiconductor layer 150 that is not covered.

In the passivation layer 180, contact holes 185, 187, and 189 are formed to expose the drain electrode 175, the conductive pattern 177 for the organic capacitor, and the data pad 179, respectively, and together with the gate insulating layer 140. A contact hole 182 is formed to expose the gate pad 125.

A pixel electrode 190 is formed on the passivation layer 180 and is electrically connected to the conductive pattern 177 for the storage capacitor and the drain electrode 175 through the contact holes 185 and 187. In addition, an auxiliary gate pad 92 and an auxiliary data pad 97 connected to the gate pad 125 and the data pad 179 are formed on the passivation layer 180 through the contact holes 182 and 189, respectively. The pixel electrode 190, the auxiliary gates, and the data pads 92 and 97 are made of indium tin oxide (ITO) or indium zinc oxide (IZO), which are transparent conductive materials. However, in the case of a reflective liquid crystal display device, the pixel electrode 190 may be made of a conductive material having reflectivity, such as silver, a silver alloy, aluminum, or an aluminum alloy. In the semi-transmissive case, the pixel electrode may have a conductivity. It may be made of a reflective film of a material and a transparent electrode of a transparent conductive material. In the reflective or semi-transmissive type, the surface of the passivation layer 180 may have a concave-convex pattern in order to induce a concave-convex pattern to the pixel electrode to maximize the reflectance of the reflecting electrode.

Here, the conductive capacitor pattern 177 connected to the pixel electrode 190 overlaps the gate line 121 to form a storage capacitor, and when the storage capacitor is insufficient, the same layer as the gate lines 121, 125, and 123. It is also possible to add a storage capacitor wiring.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3A to 8B.

First, as shown in FIGS. 3A and 3B, a single film made of silver or a silver alloy or aluminum or an aluminum alloy having a low resistance on the insulating substrate 110 or including such a single film is formed of chromium, molybdenum, molybdenum alloy, titanium Alternatively, a multi-layered film including a conductive material having excellent contact properties with other materials, such as tantalum, may be stacked and patterned to form a horizontal gate line including the gate line 121, the gate electrode 123, and the gate pad 125. .

Next, as shown in FIG. 4, the gate insulating layer 140 made of silicon nitride, the semiconductor layer 150 of undoped amorphous silicon, and the intermediate layer 160 of doped amorphous silicon are each fabricated by chemical vapor deposition. Continuous deposition was carried out at a thickness of Å to 5,000 Å, 500 Å to 2,000 Å, 1400 Å to 600 Å, and then the photosensitive film 210 was applied thereon at a thickness of 1 μm to 2 μm.

Thereafter, the photosensitive film 210 is irradiated with light through a mask and then developed to form photosensitive film patterns 212 and 214 as shown in FIG. 5B. In this case, among the photoresist patterns 212 and 214, the channel portion C of the thin film transistor, that is, the first portion 214 disposed between the source electrode 173 and the drain electrode 175 may have a semiconductor layer excluding the channel portion C. The thickness of the second portion 212 is smaller than that of the second portion 212 located at the portion where the 150 is to be formed, and the photosensitive film of the other portion B is removed. At this time, the ratio of the thickness of the photoresist film 214 remaining in the channel portion C and the thickness of the photoresist film 212 to the A portion should be different depending on the process conditions in the etching process, which will be described later. ) Is preferably 1/2 or less of the thickness of the second portion 212, for example, 4,000 kPa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin photoresist 214 may be exposed to light using a photoresist film made of a reflowable material, and then exposed and exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot completely transmit light. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 214 and the underlying layers, that is, the intermediate layer 160 and the semiconductor layer 150. In this case, the semiconductor layer and the intermediate layer remain in the A portion, only the semiconductor layer should remain in the C portion, and the two insulating layers 160 and 150 should be removed in the remaining portion B to expose the gate insulating layer 140. .

First, as shown in FIG. 5B, the intermediate layer 160 and the semiconductor layer 150 of the portion B are removed using the photoresist patterns 212 and 214 as an etching mask. In this case, the semiconductor layer 150 may be formed along the data line 171 formed later.

Subsequently, as the etching proceeds, the thickness of the photoresist film becomes thinner, and as shown in FIG. 6, only the photoresist film 212 of the A portion remains, and the photoresist film is removed from the C portion, and the intermediate layer 160 is etched to remove the semiconductor layer 150. The intermediate layer is separated into two portions 163 and 165 around the channel portion, and the semiconductor layer 150 is exposed between them. As described above, according to the exemplary embodiment of the present invention, the process of patterning the semiconductor layer 150 and the process of exposing the channel portion of the semiconductor layer 150 by etching the intermediate layer 160 may be performed in a single etching process.

Next, as shown in FIGS. 7A to 7B, after the conductive film of a wiring conductive material such as silver or silver alloy or chromium or aluminum or aluminum alloy or molybdenum or molybdenum alloy is laminated on the substrate 110, a mask is applied. The data line 171 intersecting the gate line 121 and the source electrode 173 and the data line 171 which are connected to the data line 171 and extend to the upper portion of the gate electrode 123 by patterning by using a photo process are used. It is separated from the data pad 179 and the source electrode 173 connected to one end and overlaps the drain electrode 175 and the gate line 121 facing the source electrode 173 with respect to the gate electrode 123. A data line including the conductor pattern 177 for the storage capacitor is formed.

Subsequently, as shown in FIGS. 8A and 8B, a protective film 180 is formed by stacking an insulating material such as silicon nitride or silicon oxide or an organic material having a low dielectric constant. Subsequently, the gate pad 125, the drain electrode 175, the conductive capacitor pattern 177 and the data pad 179 are patterned by dry etching together with the gate insulating layer 140 in a photolithography process using a photoresist pattern. Contact holes 183, 185, 187, and 189 to reveal the contact holes.

Next, as shown in FIGS. 1 and 2, the ITO or IZO film is laminated and patterned using a mask to conduct the drain electrode 175 and the conductor pattern 175 for the storage capacitor through the contact holes 185 and 187. ) And an auxiliary gate pad 92 and an auxiliary data pad 97 respectively connected to the gate pad 125 and the data pad 179 through the pixel electrode 190 and the contact holes 182 and 189, respectively. do.

In the method of manufacturing a thin film transistor array substrate according to the exemplary embodiment of the present invention, since the data lines 171, 173, 175, 177, and 179 are formed, the intermediate layer 160 is not etched using the etching mask, and thus the data lines are not formed. It can prevent damage.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, in the present invention, the semiconductor layer and the ohmic contact layer may be patterned in one etching process to simplify the manufacturing process. In addition, it is possible to prevent the data wiring from being damaged during the manufacturing process, thereby improving contact characteristics with the pixel electrode formed later.

Claims (5)

Stacking and patterning a conductive material on the substrate to form a gate wiring including a gate line and a gate electrode; Stacking a gate insulating film on the substrate; Forming a semiconductor layer of amorphous silicon having a channel portion over the gate insulating film, Forming an ohmic contact layer of doped amorphous silicon, which is separated around the channel part, on the semiconductor layer; A method of manufacturing a thin film transistor array substrate, comprising: forming a data line including a data line, a source electrode, and a drain electrode by stacking and patterning a conductive material on the gate insulating layer or a semiconductor layer, The forming of the semiconductor layer and the ohmic contact layer may be performed by a photolithography process using a photoresist pattern having a first portion corresponding to the channel portion and a second portion thicker than the first portion corresponding to the semiconductor layer except for the channel portion. The manufacturing method of a thin film transistor array board | substrate performed. In claim 1, And the photosensitive film pattern is formed by exposure using one mask. In claim 1, The semiconductor layer and the ohmic contact layer forming step, Sequentially depositing an amorphous silicon layer and a doped amorphous silicon layer on the gate insulating layer; Forming the photoresist pattern on the doped amorphous silicon layer; Etching the doped amorphous silicon layer under the first portion and the first portion while etching the amorphous silicon layer and the doped amorphous silicon layer using the photoresist pattern as an etch mask. Method of manufacturing a substrate. In claim 1, And forming a pixel electrode connected to the data line. In claim 3, And forming a passivation layer between the data line and the pixel electrode.