KR20040003285A - Shift register and liquid crystal display with the same - Google Patents

Abstract

PURPOSE: A shift register and a liquid crystal display device provided with the same are provided to reduce the power consumption by receiving the reset signal of the dummy stage from the pull-down driver to invert although the blanking period of the display becomes long. CONSTITUTION: A shift register includes a plurality of stages. Each of the stages includes a pull-up circuit(171), a pull-down circuit(172), a pull-up driver(173) and a pull-down driver(174). The pull-up circuit(171) supplies a clock corresponding to one of a first and a second clocks to the output terminal. The pull-down circuit(172) supplies a first power voltage to the output terminal. The pull-up driver(173) connected to the input node of the pull-up circuit(171) turns on the pull-up circuit(171) in response to the front end of the output signal of the previous stage and turns off the pull-up circuit(171) in response to the front ends of a first control signal and a second control signal. The pull-down driver(174) connected to the input node of the pull-down circuit(172) turns off the pull-down circuit(172) in response to the front end of the input signal and turns on the pull-down circuit(172) in response to the front ends of the first control signal and the second control signal.

Description

SHIFT REGISTER AND LIQUID CRYSTAL DISPLAY WITH THE SAME}

The present invention relates to a shift register and a liquid crystal display device having the same, and more particularly, to a shift register suitable for a high definition and large screen and a liquid crystal display device having the same.

Recently, information processing devices have been rapidly developed to have various forms, various functions, and faster information processing speeds. Information processed in such an information processing device has an electrical signal form. In order for the user to visually check the information processed by the information processing apparatus, a display apparatus that serves as an interface is required.

Recently, a liquid crystal display device has a light weight, a small size, high resolution, low power, and an environment-friendly advantage compared to a typical CRT display device, and is capable of full color and is emerging as a next generation display device.

A liquid crystal display device applies voltage to a specific molecular array of a liquid crystal and converts it into another molecular array, and visually changes the optical properties such as birefringence, photoreactivity, dichroism, and light scattering characteristics of the liquid crystal cell that emit light by the molecular arrangement. It is a display using the modulation of the light by a liquid crystal cell by converting into.

The liquid crystal display device is largely divided into twisted nematic (TN) and super-twisted nematic (STN) methods, and the active matrix display method using a switching element and TN liquid crystal and a passive matrix using STN liquid crystal due to the difference in driving method. There is a passive matrix display method.

The big difference between these two methods is that the active matrix display method is used for TFT-LCD, which drives the LCD using the TFT as a switch, and the passive matrix display method does not use transistors, thus requiring a complicated circuit. Do not

TFT-LCD is divided into a-Si TFT LCD and poly-Si TFT LCD. Poly-Si TFT LCD has low power consumption and low price, but has a disadvantage of complicated TFT manufacturing process compared to a-Si TFT. Thus, poly-Si TFT LCDs are mainly applied to small display devices such as those of IMT-2000 phones.

The a-Si TFT LCD has large area and high yield, and is mainly applied to large screen display devices such as notebook PCs, LCD monitors, and HDTVs.

1 is a schematic view showing the configuration of a TFT substrate of a poly-TFT LCD, and FIG. 2 is a schematic view showing the configuration of a TFT substrate of a conventional a-Si LCD.

As shown in Fig. 1, a poly-Si TFT LCD forms a data driving circuit 12 and a gate driving circuit 14 on a glass substrate 10 on which a pixel array is formed, and a terminal portion 16 and an integrated printed circuit. The substrate 20 is connected with the film cable 18. Such a structure can reduce manufacturing cost and minimize power loss by integrating a driving circuit.

However, as shown in FIG. 2, the a-Si TFT LCD forms the data driving chip 34 on the flexible printed circuit board 32 by a COF (CHIP ON FILM) method, and the flexible printed circuit board 32. The data printed circuit board 36 is connected to the data line terminal portion of the pixel array through the data printed circuit board 36. In addition, the gate driving chip 40 is formed on the flexible printed circuit board 38 by the above-described COF method, and the gate printed circuit board 42 and the gate line terminal portion of the pixel array are formed through the flexible printed circuit board 40. Connect.

That is, in the a-Si TFT LCD, despite the high productivity, which is an advantage of the a-Si process, the poly Si-TFT LCD has a disadvantage in terms of cost and slim structure.

Accordingly, the technical and problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a shift register for reducing the layout space while reducing power consumption and suitable for high-definition and large screens.

Another object of the present invention is to provide a liquid crystal display device having the above shift register.

1 is a schematic view showing the configuration of a TFT substrate of a poly-TFT LCD.

2 is a schematic view showing the structure of a TFT substrate of a conventional a-Si LCD.

3 is an exploded perspective view of the a-Si TFT liquid crystal display device according to the present invention.

4 is a view showing the configuration of a TFT substrate of an a-Si TFT LCD according to the present invention.

5 is a block diagram of a shift register of the data driving circuit of FIG. 4 described above.

FIG. 6 is a block diagram for describing a shift register employed in the gate driving circuit of FIG. 4.

FIG. 7 shows a detailed circuit configuration of each stage of the shift register shown in FIG.

8 is an output waveform diagram according to FIG. 7 described above.

FIG. 9 is a waveform diagram illustrating the driving waveform shown in FIG. 6 described above.

FIG. 10 is a diagram for explaining the shift register according to FIG. 7 described above.

FIG. 11 is a waveform diagram for explaining a simulation result by a shift register having five stages disclosed in FIG. 7 described above and one dummy stage at the end.

12 illustrates a shift register according to an embodiment of the present invention.

FIG. 13 is a diagram for explaining a simulation result according to FIG. 12.

14 is a diagram for explaining a shift register according to another exemplary embodiment of the present invention.

FIG. 15 is a diagram for explaining a simulation result of FIG. 14 described above. FIG.

<Description of the symbols for the main parts of the drawings>

110: liquid crystal display panel assembly 120: backlight assembly

130: chassis 140: cover

150: display cell array circuit 160: data driving circuit

162, 163, 169: external connection terminal 170: gate driving circuit

171: pull-up unit 172: pull-down unit

173: pull-up driving unit 174: pull-down driving unit

According to one aspect of the present invention, a shift register includes a plurality of stages, a first stage of which a start signal is coupled to an input terminal, and a shift for sequentially outputting output signals of each stage. In the register, odd-numbered stages of the shift register are provided with a first clock and a first control signal for removing an output of the first clock, and even-numbered stages are phase-inverted with respect to the first clock. A second control signal for removing an output of the second clock and the second clock, and each stage includes: a pull-up unit configured to provide a corresponding one of the first and second clocks to an output terminal; A pull-down unit providing a first power supply voltage to the output terminal; A pull-up unit connected to an input node of the pull-up unit and turning on the pull-up unit in response to the leading end of the output signal of the previous stage, and turning off the pull-up unit in response to the leading end of the first control signal or the second control signal; A drive unit; And a pull-down driving unit connected to an input node of the pull-down unit and turning off the pull-down unit in response to the leading end of the input signal, and turning on the pull-down unit in response to the leading end of the first control signal or the second control signal. And at least one dummy stage for resetting the last stage of the plurality of stages, wherein the dummy stage is reset in response to an output signal of the dummy stage.

In addition, a shift register according to another aspect for realizing the object of the present invention described above, a plurality of stages are arranged, the start signal is coupled to the input terminal in the first stage, the output signal of each stage sequentially In the shift register for outputting, odd-numbered stages of the shift register are provided with a first clock, and a first control signal for removing the output of the first clock, and even-numbered stages are phased with the first clock. A second inverted clock and a second control signal for removing an output of the second clock are provided, and each stage includes: a pull-up unit configured to provide an output terminal with a corresponding clock among the first and second clocks; A pull-down unit providing a first power supply voltage to the output terminal; A pull-up unit connected to an input node of the pull-up unit and turning on the pull-up unit in response to the leading end of the output signal of the previous stage, and turning off the pull-up unit in response to the leading end of the first control signal or the second control signal; A drive unit; And a pull-down driving part connected to an input node of the pull-down part and turning off the pull-down part in response to the leading end of the input signal, and turning on the pull-down part in response to the leading end of the first control signal or the second control signal. And at least one dummy stage subordinate to the last stage for resetting the last stage, wherein the dummy stage is reset in response to a control signal provided from the last stage.

In addition, a liquid crystal display device according to another aspect for realizing the above object of the present invention includes a display cell array circuit, a data driving circuit, and a gate driving circuit formed on a transparent substrate. A liquid crystal display device comprising a plurality of data lines and a plurality of gate lines, each display cell circuit connected to a corresponding data and gate line pair, wherein the gate driving circuit includes a plurality of stages, A start signal is coupled to an input terminal, and comprises a shift register that sequentially selects the plurality of gate lines by an output signal of each stage, wherein odd-numbered stages of the shift register are included in odd-numbered stages of the shift register. A first control and a first control for removing the output of the first clock A call is provided, and even-numbered stages are provided with a second clock phase-inverted to the first clock and a second control signal for removing the output of the second clock, wherein each stage is provided with an output terminal. A pull-up unit which provides a corresponding clock among the first and second clocks; A pull-down unit providing a first power supply voltage to the output terminal; A pull-up unit connected to an input node of the pull-up unit and turning on the pull-up unit in response to the leading end of the output signal of the previous stage, and turning off the pull-up unit in response to the leading end of the first control signal or the second control signal; A drive unit; And a pull-down driving part connected to an input node of the pull-down part and turning off the pull-down part in response to the leading end of the input signal, and turning on the pull-down part in response to the leading end of the first control signal or the second control signal. And at least one dummy stage for resetting the last stage of the plurality of stages, wherein the dummy stage is reset in response to an output signal of the dummy stage.

In addition, a liquid crystal display device according to another aspect for realizing the above object of the present invention includes a display cell array circuit, a data driving circuit, a gate driving circuit formed on a transparent substrate, and the display cell array circuit. And a plurality of data lines and a plurality of gate lines, wherein each display cell circuit is connected to a corresponding data and gate line pair, wherein the gate driving circuit includes a plurality of stages, and a first stage. The shift signal includes a shift register coupled to an input terminal and sequentially selecting the plurality of gate lines by an output signal of each stage, and odd-numbered stages of the shift register include odd-numbered stages of the shift register. The first clock and a first for removing the output of the first clock A control signal is provided, and even-numbered stages are provided with a second clock phase-inverted to the first clock and a second control signal for removing the output of the second clock, wherein each stage is provided to an output terminal. A pull-up unit configured to provide a corresponding clock among the first and second clocks; A pull-down unit providing a first power supply voltage to the output terminal; A pull-up unit connected to an input node of the pull-up unit and turning on the pull-up unit in response to the leading end of the output signal of the previous stage, and turning off the pull-up unit in response to the leading end of the first control signal or the second control signal; A drive unit; And a pull-down driving part connected to an input node of the pull-down part and turning off the pull-down part in response to the leading end of the input signal, and turning on the pull-down part in response to the leading end of the first control signal or the second control signal. And at least one dummy stage subordinate to the last stage for resetting the last stage, wherein the dummy stage is reset in response to a control signal provided from the last stage.

According to such a shift register and a liquid crystal display device having the same, the display blanking period is reset by resetting the reset signal of the dummy stage for resetting the last stage based on the control signal provided from the last stage or the output signal provided from the dummy stage. Even longer, power consumption can be reduced, and wiring space can be saved.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

3 is an exploded perspective view of the a-Si TFT liquid crystal display device according to the present invention.

Referring to FIG. 3, the liquid crystal display 100 largely includes a liquid crystal display panel assembly 110, a backlight assembly 120, a chassis 130, and a cover 140.

The liquid crystal display panel assembly 110 includes a liquid crystal display panel 112, a flexible printed circuit board 116, an integrated control and data driving chip 118. The liquid crystal display panel 112 includes a TFT substrate 112a and a color filter substrate 112b. In the TFT substrate 112a, a display cell array circuit, a data driving circuit, a gate driving circuit, and external connection terminals are formed by an a-Si TFT process. Color filters and transparent common electrodes are formed on the color filter substrate 112b. The TFT substrate 112a and the color filter substrate 112b are opposed to each other and liquid crystal is injected therebetween and then encapsulated.

The integrated control and data driver chip 118 and the circuits of the TFT substrate 112a installed in the flexible printed circuit board 116 are electrically connected by the flexible printed circuit board 116. The flexible printed circuit board 116 provides data signals, data timing signals, gate timing signals, and gate driving voltages to the data driving circuit and gate driving circuit of the TFT substrate 112a.

The backlight assembly 120 includes a lamp assembly 122, a light guide plate 124, optical sheets 126, a reflector plate 128, and a mold frame 129.

4 is a view showing the configuration of a TFT substrate of an a-Si TFT LCD according to the present invention.

Referring to FIG. 4, the display cell array circuit 150, the data driver circuit 160, the gate driver circuit 170, the data driver circuit external connection terminals 162 and 163 and the gate are disposed on the TFT substrate 112a of the present invention. The driving circuit external connection terminal portion 169 is formed together in the TFT process.

The display cell array circuit 150 includes m data lines DL1 to DLm extending in a column direction and n gate lines GL1 to GLn extending in a row direction.

In the exemplary embodiment of the present invention, the number of data lines and gate lines in the 2-inch liquid crystal display panel has a resolution of 525 (ie, 176 × 3) × 192.

At each intersection of the data lines and the gate lines, a switching transistor ST is formed. The drain of the switching transistor STi is connected to the data line DLi, and the gate is connected to the gate line GLi. The source of the switching transistor STi is connected to the transparent pixel electrode PE. The liquid crystal LC is positioned between the transparent pixel electrode PE and the transparent common electrode CE formed on the color filter substrate 112b.

Therefore, the liquid crystal array is controlled by the voltage applied between the transparent pixel electrode PE and the transparent common electrode CE, thereby controlling the amount of light passing through to display the gray level of each pixel.

The data driving circuit 160 includes a shift register 164 and 528 switching transistors SWT. The 528 switching transistors SWT form eight data line blocks BL1 to BL8 for 66 units.

Each data line block BLi has 66 input terminals commonly connected to the external input terminal 163 composed of 66 data input terminals, and 66 output terminals are connected to the corresponding 66 data lines. In addition, a block select terminal is connected to a corresponding one of the eight output terminals of the shift register 164.

Each of the 528 switching transistors SWT has a source connected to a corresponding data line, a drain connected to a corresponding input terminal of 66 data input terminals, and an a-Si TFT MOS transistor connected to a block selection terminal at a gate thereof. It consists of.

Accordingly, the 528 data lines are divided into eight blocks of 66 pieces, and each block is sequentially selected by the eight block selection signals of the shift register 164.

The shift register 164 receives a first clock CKH, a second clock CKHB, and a block selection start signal STH through an external connection terminal 162 of three terminals. The output terminals of the shift register 164 are connected to block select terminals of the corresponding line blocks, respectively.

5 is a block diagram of a shift register of the data driving circuit of FIG. 4 described above.

Referring to FIG. 5, in the shift register 164 according to the present invention, nine stages SRH1 to SRH9 are cascaded. That is, the output terminal OUT of each stage is connected to the input terminal IN of the next stage. The number of stages is composed of eight stages SRH1 to SRH8 and one dummy stage SRH9 corresponding to the data line blocks. Each stage has an input terminal IN, an output terminal OUT, a control terminal CT, a clock input terminal CK, a first power supply voltage terminal VSS, and a second power supply voltage terminal VDD. The eight stages SRH1 to SRH8 provide the block select start signals DE1 to DE8 to the block select terminals of the data line blocks BL1 to BL8, respectively. The block selection start signal is an enable signal of each line block.

The first clock CKH is provided to the odd-numbered stages SRH1, SRH3, SRH5, SRH7, and SRH9, and the second clock CKHB is provided to the even-numbered stages SRC2, SRC4, SRH6, and SRH8. The first clock CKH and the second clock CKHB have phases opposite to each other. The duty periods of the clocks CKH and CKHB are 1/66 ms or less.

The output signal of the next stage is input to the control terminal CT as a control signal to each control terminal CT of each stage. That is, the control signal input to the control terminal CT becomes a signal delayed by the duty period of its output signal.

Accordingly, since output signals of each stage are sequentially generated with an active period (that is, a high state), corresponding data line blocks are selected and enabled in the active period of each output signal.

The dummy stage SRH9 is for providing a control signal to the control terminal CT of the previous stage SRH8.

FIG. 6 is a block diagram for describing a shift register employed in the gate driving circuit of FIG. 4.

Referring to FIG. 6, the gate driving circuit 170 of FIG. 4 includes one shift register, and the shift register is cascaded with a plurality of stages SRC1 to SRC193. That is, the output terminal OUT of each stage is connected to the input terminal IN of the next stage. The stages include 192 stages SRC1 to SRC192 and one dummy stage SRC193 corresponding to the gate lines. Each stage has an input terminal IN, an output terminal OUT, a control terminal CT, a clock input terminal CK, a first power supply voltage terminal VSS, and a second power supply voltage terminal VDD.

The scan start signal STV is input to the input terminal IN of the first stage SRC1. The scan start signal STV is a pulse synchronized with the vertical synchronization signal Vsync.

The output signals GOUT1 to GOUT192 of each stage are connected to the corresponding gate lines. The odd clock stages SRC1, SRC3,... Are provided with a first clock CKV, and the even stages SRC2, SRC4, ... are provided with a second clock CKVB. Here, the first clock CKV and the second clock CKVB have phases opposite to each other. In addition, the duty period of the first clock CKV and the second clock CKVB may be a period of 16.6 / 192 ms.

Therefore, the duty period of the clock of the shift register 170 of the gate driving circuit is about 8 times or more than the duty period of the clock of the shift register 164 of the data driving circuit.

In each control terminal CT of each stage SRC1, SRC2, SRC3, ..., the output signal GOUT2, GOUT3, GOUT4 of the next stage SRC2, SRC3, SRC4, ... is a control terminal as a control signal. It is input to (CT). That is, the control signal input to the control terminal CT becomes a signal delayed by the duty period of its output signal.

Therefore, since the output signals of each stage are sequentially generated with an active period (high state), the corresponding horizontal line is selected in the active period of each output signal.

FIG. 7 shows a detailed circuit configuration of each stage of the shift register shown in FIG. 6, and FIG. 8 is an output waveform diagram according to FIG.

Referring to FIG. 7, each stage of the shift register 170 includes a pull up unit 171, a pull down unit 172, a pull up driver 173, and a pull down driver 174.

The first NMOS transistor M1 having a drain connected to a power clock input terminal CKV, a gate connected to a third node N3, and a source connected to an output terminal GOUT [N] is connected to the pull-up unit 171. It consists of.

The second NMOS transistor M2 having a drain connected to an output terminal GOUT [N], a gate connected to a fourth node N4, and a source connected to a first power voltage VSS. It consists of.

The pull-up driving unit 173 includes a capacitor C and third to fifth NMOS transistors M3 to M5. The capacitor C is connected between the third node N3 and the output terminal GOUT [N]. The third transistor M3 has a drain connected to the second power supply voltage VON, a gate connected to an input terminal IN, that is, an output signal GOUT [N-1] of the previous stage, and a source of the third transistor M3. It is connected to node N3. In the fourth transistor M4, a drain is connected to the third node N3, a gate is connected to the fourth node N4, and a source is connected to the first power voltage VOFF. In the fifth transistor NT5, a drain is connected to the third node N3, a gate is connected to the fourth node N4, and a source is connected to the first power voltage VOFF. In this case, the size of the third transistor M3 is about twice as large as that of the fifth transistor M5.

The pull-down driver 174 includes sixth and seventh NMOS transistors M6 and M7. The sixth transistor M6 has a drain and a gate in common and is connected to the second power supply voltage VON, and a source is connected to the fourth node N4. In the seventh transistor M7, a drain is connected to the fourth node N4, a gate is connected to the third node N3, and a source is connected to the first power voltage VOFF. In this case, the size of the sixth transistor M6 is about 16 times larger than the size of the seventh transistor M7.

As shown in FIG. 8, when the first and second power clocks CKV and CKVB and the scan start signal ST are supplied to the shift register, the first stage SRC1 is provided at the leading end of the scan start signal ST. In response, the high level section of the first power clock CKV is delayed by a predetermined time Tdr1 to generate the output signal GOUT1 at the output terminal OUT.

As described above, the first and second power clocks CKV and CKVB are supplied to the glassy shift register on which the array substrate is disposed together with the scan start signal STV to drive the gate of the TFT provided in the array substrate. It performs an operation as a gate driving circuit.

FIG. 9 is a waveform diagram illustrating the driving waveform shown in FIG. 6 described above.

Referring to FIG. 9, the shift register selects either one of the first power clock CKV or the second power clock CKVB in which the phase is inverted with respect to the first power clock CKV. When applied, the gate signals GOUT1, GOUT2, GOUT3, ... are sequentially output to the TFT-LCD gate line. In this case, the first and second power clocks CKV and CKVB may output a signal having an amplitude of 0 to 3 V, which is an output of a timing controller (not shown), to drive a-TFT. Amplified signal.

As described above, when the capacitor is charged by the output signal of the front stage and the power clock connected to the pull-up section or the pull-down section becomes a high level, the above-mentioned voltage becomes the output voltage of the stage. The moment the application waveform is generated on the gate line of the stage, the next stage output operates the discharge transistor to discharge the capacitor voltage to terminate one operation cycle of the shift register.

Since the shift register of this structure is reset by the output of the next stage, at least one dummy stage must be added to reset the last stage. However, the means for resetting the above dummy stage is also a problem.

Such a reset means adopts a structure in which the scan start signal STV is even connected to the discharge transistor of the dummy stage as shown in FIG.

FIG. 10 is a view for explaining the shift register according to FIG. 7 described above. In particular, it is a view for explaining the wiring of the last stage and the dummy stage of the TFT gate driving stage.

As shown in FIG. 10, the transistor for discharging the capacitor included in the dummy stage is discharged, that is, a reset operation is performed by the scan start signal STV input to the first stage.

The simulation result of FIG. 11 described below describes the output waveform of the shift register in which five stages for outputting a gate signal are configured, and the last sixth stage is configured as a dummy stage. Of course, the output voltage of the last sixth stage does not mean the gate signal associated with the display operation.

FIG. 11 is a waveform diagram for explaining a simulation result by a shift register having five stages disclosed in FIG. 7 described above and one dummy stage at the end.

Referring to FIG. 11, the first clock signal CKV is changed to a high level after a predetermined time delay in response to the rising edge of the scan start signal STV, and the first clock CKV is changed to a high level. It can be seen that the first gate signal GOUT [1] is generated at the output terminal of the stage.

Subsequently, it is confirmed that second to fifth gate signals GOUT [2], GOUT [3], GOUT [4], and GOUT [5] are sequentially generated at the output terminals of the second, third, fourth, and fifth stages, respectively. Can be. Here, since the scan start signal STV is input to the sixth stage, which is the first stage and the dummy stage, the output of the sixth stage is input to the second clock CKVB until the next scan start signal STV is generated and reset. Outputs

However, when the dummy stage is reset, the problem described below occurs in a high-definition, large screen TFT LCD when the scan start signal STV is used.

That is, the layout space is lost because the wiring of the scan start signal STV must be extended over the entire shift register.

In addition, since the wirings of the scan start signal STV are arranged vertically, parasitic capacitance is increased due to overlap with the horizontal lines, and there is a problem that signal distortion is likely due to the increased parasitic capacitance.

In addition, in terms of power consumption, the power consumption of the large amplitude first clock CKV and the second clock CKVB, which must charge / discharge the parasitic capacitance, increases with the output of the dummy stage generated during the display blanking time. There is a problem that power is increased.

Then, with reference to the accompanying drawings, a structure for solving this problem will be described.

12 is a view for explaining a shift register according to an embodiment of the present invention, Figure 13 is a view for explaining the simulation results according to the above-described FIG. In particular, for convenience of description, only the N-th stage for outputting the N-th gate signal GOUT [N], which is the last gate signal, and one dummy stage connected thereto are shown.

Referring to FIG. 12, each stage of the shift register according to an exemplary embodiment of the present invention includes a pull-up unit 171, a pull-down unit 172, a pull-up driver 173, and a pull-down driver 174. Compared with FIG. 7, the pull-up unit 171, the pull-down unit 172, the pull-up driving unit 173, and the pull-down driving unit 174 are the same, and the same reference numerals are given, and detailed description thereof will be omitted.

The output signal of the pull-down driver 174 provided in the last stage is applied to the pull-down driver 172 and the pull-up driver 173 of the dummy stage.

More specifically, the source of the sixth transistor M6 of the last stage is connected to the gate of the fifth transistor M5 of the dummy stage.

In operation through this connection, the inverter output voltage, which is low during the Nth stage outputting the last gate signal, is reset to the high state while being reset by the N + 1th output signal. The transitioned high state is provided in the pull-up driver 171 of the dummy stage to operate the fifth transistor M5 to perform a discharge operation to reset the dummy stage.

Referring to FIG. 13, the output signals GOUT (1), GOUT (2), GOUT (3), GOUT (4), and GOUT (5) of five stages that generate the displayed gate driving voltage are normally generated. It can be seen that the output signal GOUT (6) of the dummy stage is also reset immediately after the last stage is reset.

Therefore, even if the display blanking time is long, the output of the dummy stage is absent, thereby reducing power consumption. That is, in FIG. 11, the gate signal output from the dummy stage was present even during the blanking time. However, in FIG. 13, since the gate signal output from the dummy stage does not exist, power consumption by the output of the dummy stage can be reduced. have.

In addition, since it is not a reset using the scan start signal STV, a separate wiring space for receiving the scan start signal STV can be saved, and the first clock CKV due to parasitic capacitance with the scan start signal STV can be saved. ) And an increase in power consumption of the second clock CKVB.

That is, in FIG. 10 described above, since the scan start signal STV applied to the first stage is extended to reset the dummy stage, a separate wiring space is required, and overlap with wirings applied to each stage can be avoided. There was no. However, according to the shift register shown in FIG. 12, a signal for resetting a dummy stage can be supplied from a stage for outputting the last gate signal, thereby not only saving wiring space, but also providing wiring lines applied to each stage. The overlap of can be avoided.

14 is a diagram for explaining a shift register according to another exemplary embodiment of the present invention, and FIG. 15 is a diagram for explaining a simulation result of FIG. 14. In particular, for convenience of description, only the N-th stage for outputting the N-th gate signal GOUT [N], which is the last gate signal, and one dummy stage connected thereto are shown.

Referring to FIG. 14, each stage of the shift register according to another embodiment of the present invention includes a pull-up unit 171, a pull-down unit 172, a pull-up driver 173, and a pull-down driver 174. Compared with FIG. 7, the pull-up unit 171, the pull-down unit 172, the pull-up driver 173, and the pull-down driver 174 are the same, and therefore, the same reference numerals will be given, and detailed description thereof will be omitted.

The output signal of the pull-down unit 172 provided in the dummy stage is applied to the pull-up driving unit 173 provided in the last stage to reset the last stage and is applied to the pull-up driving unit 173 of the dummy stage to reset the dummy stage. .

More specifically, the source of the first transistor M1 of the dummy stage or the drain of the second transistor M2 is connected to the gate of the fifth transistor M5 of the last stage, and also the fifth transistor M5 of the dummy stage. Is connected to the gate.

In operation through this connection, the inverter output voltage, which is low during the Nth stage outputting the last gate signal, is reset to the high state while being reset by the N + 1th output signal. The transitioned high state is provided in the pull-up driver 171 of the dummy stage to operate the fifth transistor M5 to perform a discharge operation to reset the dummy stage.

Referring to FIG. 15, the output signals GOUT (1), GOUT (2), GOUT (3), GOUT (4), and GOUT (5) of five stages that generate the displayed gate driving voltage are normally generated. It can be seen that the output signal GOUT (6) of the dummy stage is also reset immediately after the last stage is reset. In particular, compared to the above-described FIG. 13 described in an embodiment of the present invention, only the output level of the dummy stage is different, and the same operation result is displayed.

Therefore, even if the display blanking time is long, the output of the dummy stage is absent, thereby reducing power consumption. That is, in FIG. 11, the gate signal output from the dummy stage was present even during the blanking time. However, in FIG. 13, since the gate signal output from the dummy stage does not exist, power consumption by the output of the dummy stage can be reduced. have.

In addition, since it is not a reset using the scan start signal STV, a separate wiring space for receiving the scan start signal STV can be saved, and the first clock CKV due to parasitic capacitance with the scan start signal STV can be saved. ) And an increase in power consumption of the second clock CKVB.

That is, in FIG. 10 described above, since the scan start signal STV applied to the first stage is extended to reset the dummy stage, a separate wiring space is required, and overlap with wirings applied to each stage can be avoided. There was no. However, according to the shift register shown in FIG. 12, a signal for resetting a dummy stage can be supplied from a stage for outputting the last gate signal, thereby not only saving wiring space, but also providing wiring lines applied to each stage. The overlap of can be avoided.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

As described above, according to the present invention, in a shift register having a plurality of stages and one dummy stage for resetting the last stage among the stages, the reset signal of the dummy stage is changed to the last stage, more specifically, the inverter operation. By being provided from the pull-down driver to perform, the display blanking period can be extended, the power consumption can be reduced, the wiring space can be saved, and the first clock CKV due to the parasitic capacitance due to the wiring of the scan start signal STV. ) And increase in power consumption of the second clock CKVB.

In addition, according to the present invention, in the shift register having a plurality of stages and a dummy stage, the power consumption can be reduced even if the display blanking period becomes longer by using the dummy stage reset signal as the output signal of the dummy stage. The wiring space can be saved, and an increase in power consumption of the first clock CKV and the second clock CKVB due to parasitic capacitance caused by the wiring of the STV signal can be solved.

Claims (8)

In the shift register for arranging a plurality of stages, the start signal is coupled to the input terminal in the first stage, and sequentially outputs the output signals of each stage, Odd-numbered stages of the shift register are provided with a first clock, a first control signal for removing the output of the first clock, and even-numbered stages with a second clock phase-inverted to the first clock; A second control signal is provided for removing the output of the second clock. Each stage, Pull-up means for providing a corresponding one of the first and second clocks to an output terminal; Pull-down means for providing a first power supply voltage to the output terminal; A pull-up means connected to an input node of the pull-up means, the pull-up means being turned on in response to a leading end of an output signal of a previous stage, and the pull-up means being turned in response to a leading end of the first control signal or the second control signal; Pull-up driving means for turning off; And A pull-down connected to an input node of the pull-down means, the pull-down means being turned off in response to a leading end of the input signal, and a pull-down turning on the pull-down means in response to the leading end of the first control signal or the second control signal; With driving means, And at least one dummy stage for resetting a last stage of the plurality of stages, wherein the dummy stage is reset in response to an output signal of the dummy stage. The method of claim 1, wherein the dummy stage, Dummy pull-up means for providing a corresponding one of the first and second clocks to a dummy output terminal; Dummy pull-down means for providing a first power supply voltage to the dummy output terminal; A dummy pull-up means connected to an input node of the dummy pull-up means, the dummy pull-up means being turned on in response to a leading end of an output signal of a previous stage, and corresponding to one of the first and second clocks provided from the dummy pull-up means; Dummy pull-up driving means for turning off the dummy pull-up means in response; And Connected to an input node of the dummy pull-down means, the dummy pull-down means is turned off in response to the leading end of the input signal, and the dummy pull-down means is turned in response to the leading end of the first control signal or the second control signal. And a dummy pull-down driving means for turning on. The method of claim 2, wherein the dummy pull-up driving means, A capacitor connected to an input node and the output terminal of the dummy pull-up means; A first transistor having a drain supplied with a first power supply voltage, a gate provided with an output signal of the previous stage, and a source connected to an input node of the dummy pull-up means; A second transistor having a drain connected to an input node of the dummy pull-up means, a gate connected to an input node of the dummy pull-down means, and a source connected to a first power supply voltage; And And a third transistor having a drain connected to an input node of the dummy pull-up means, a gate connected to an output terminal of the dummy pull-up means, and a source connected to the first power voltage. In the shift register for arranging a plurality of stages, the start signal is coupled to the input terminal in the first stage, and sequentially outputs the output signals of each stage, Odd-numbered stages of the shift register are provided with a first clock, a first control signal for removing the output of the first clock, and even-numbered stages with a second clock phase-inverted to the first clock; A second control signal is provided for removing the output of the second clock. Each stage, Pull-up means for providing a corresponding one of the first and second clocks to an output terminal; Pull-down means for providing a first power supply voltage to the output terminal; A pull-up means connected to an input node of the pull-up means, the pull-up means being turned on in response to a leading end of an output signal of a previous stage, and the pull-up means being turned in response to a leading end of the first control signal or the second control signal; Pull-up driving means for turning off; And A pull-down connected to an input node of the pull-down means, the pull-down means being turned off in response to a leading end of the input signal, and a pull-down turning on the pull-down means in response to the leading end of the first control signal or the second control signal; With driving means, And one or more dummy stages dependent on the last stage for resetting the last stage, wherein the dummy stage is reset in response to a control signal provided from the last stage. The method of claim 4, wherein the dummy stage, Dummy pull-up means for providing a corresponding one of the first and second clocks to a dummy output terminal; Dummy pull-down means for providing a first power supply voltage to the dummy output terminal; The dummy pull-up means is connected to an input node of the dummy pull-up means and turns on the dummy pull-up means in response to the leading end of the output signal of the previous stage, and in response to the turn-off operation of the pull-down driving means of the previous stage. Dummy pull-up driving means for turning off; And Connected to an input node of the dummy pull-down means, the dummy pull-down means is turned off in response to the leading end of the input signal, and the dummy pull-down means is turned in response to the leading end of the first control signal or the second control signal. And a dummy pull-down driving means for turning on. The method of claim 5, wherein the dummy pull-up driving means, A capacitor connected to an input node and the output terminal of the dummy pull-up means; A first transistor having a drain supplied with a first power supply voltage, a gate provided with an output signal of the previous stage, and a source connected to an input node of the dummy pull-up means; A second transistor having a drain connected to an input node of the dummy pull-up means, a gate connected to an input node of the dummy pull-down means, and a source connected to a first power supply voltage; And And a third transistor having a drain connected to an input node of the dummy pull-up means, a gate connected to an output terminal of a pull-down driver of a previous stage, and a source connected to the first power supply voltage. And a display cell array circuit, a data driving circuit, and a gate driving circuit formed on the transparent substrate, wherein the display cell array circuit includes a plurality of data lines and a plurality of gate lines, and each display cell circuit includes corresponding data and In a liquid crystal display device connected to a pair of gate lines, The gate driving circuit includes a plurality of stages, and a first stage includes a shift register coupled to an input terminal and sequentially selecting the plurality of gate lines by an output signal of each stage. Odd-numbered stages of the register are provided with odd-numbered stages of the shift register and a first control signal for canceling the output of the first clock, and even-numbered stages are phased with the first clock. A second inverted clock and a second control signal for removing the output of the second clock are provided, Each stage, Pull-up means for providing a corresponding one of the first and second clocks to an output terminal; Pull-down means for providing a first power supply voltage to the output terminal; A pull-up means connected to an input node of the pull-up means, the pull-up means being turned on in response to a leading end of an output signal of a previous stage, and the pull-up means being turned in response to a leading end of the first control signal or the second control signal; Pull-up driving means for turning off; And A pull-down connected to an input node of the pull-down means, the pull-down means being turned off in response to a leading end of the input signal, and a pull-down turning on the pull-down means in response to the leading end of the first control signal or the second control signal; And at least one dummy stage for resetting a last stage of the plurality of stages, wherein the dummy stage is reset in response to an output signal of the dummy stage. And a display cell array circuit, a data driving circuit, and a gate driving circuit formed on the transparent substrate, wherein the display cell array circuit includes a plurality of data lines and a plurality of gate lines, and each display cell circuit includes corresponding data and In a liquid crystal display device connected to a pair of gate lines, The gate driving circuit includes a plurality of stages, and a first stage includes a shift register coupled to an input terminal and sequentially selecting the plurality of gate lines by an output signal of each stage. Odd-numbered stages of the register are provided with odd-numbered stages of the shift register and a first control signal for canceling the output of the first clock, and even-numbered stages are phased with the first clock. A second inverted clock and a second control signal for removing the output of the second clock are provided, Each stage, Pull-up means for providing a corresponding one of the first and second clocks to an output terminal; Pull-down means for providing a first power supply voltage to the output terminal; A pull-up means connected to an input node of the pull-up means, the pull-up means being turned on in response to a leading end of an output signal of a previous stage, and the pull-up means being turned in response to a leading end of the first control signal or the second control signal; Pull-up driving means for turning off; And A pull-down connected to an input node of the pull-down means, the pull-down means being turned off in response to a leading end of the input signal, and a pull-down turning on the pull-down means in response to the leading end of the first control signal or the second control signal; And at least one dummy stage subordinate to said last stage for resetting the last stage, said dummy stage being reset in response to a control signal provided from said last stage. Device.