KR20040001534A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR20040001534A KR20040001534A KR1020020036766A KR20020036766A KR20040001534A KR 20040001534 A KR20040001534 A KR 20040001534A KR 1020020036766 A KR1020020036766 A KR 1020020036766A KR 20020036766 A KR20020036766 A KR 20020036766A KR 20040001534 A KR20040001534 A KR 20040001534A
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- insulating layer
- semiconductor device
- oxygen
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- forming
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 235000002259 Callirhoe involucrata Nutrition 0.000 claims abstract description 14
- 241001339245 Callirhoe digitata Species 0.000 claims abstract description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 239000001301 oxygen Substances 0.000 claims abstract description 13
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 13
- 238000001312 dry etching Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000011261 inert gas Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000011065 in-situ storage Methods 0.000 claims abstract description 3
- 239000007789 gas Substances 0.000 claims description 4
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 240000006350 Callirhoe involucrata Species 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 제1절연막이 형성된 반도체 기판을 준비하는 단계; 상기 제1절연막상에 금속층을 형성하고 라이너와 제2절연막을 형성하는 단계; 상기 금속층이 노출되도록 상기 제2절연막과 라이너를 선택적으로 건식각하여 비아홀을 형성하는 단계; 상기 비아홀이 형성된 구조물에 인시튜로 산소를 이용하거나 또는 산소와 불활성기체를 이용하여 후식각처리(PET)하는 단계; 및 상기 제2절연막을 선택적으로 건식각하여 비아 와인 컵 구조를 형성하는 단계를 포함하며, PET 공정을 건식 식각 공정에 도입하여 습식 식각 공정을 생략하여 기존 공정의 단점을 해결함으로써 습식 식각 장비를 사용하지 않게 되어 원가 절감 및 TAT 관리에 많은 이점이 발생하는 효과가 있는 것이다.The present invention relates to a method of manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor substrate on which a first insulating film is formed; Forming a metal layer on the first insulating layer, and forming a liner and a second insulating layer; Selectively dry etching the second insulating layer and the liner to expose the metal layer to form a via hole; Post-etching (PET) using oxygen in situ on the via hole formed structure or using oxygen and an inert gas; And selectively dry etching the second insulating layer to form a via wine cup structure, by introducing a PET process into a dry etching process, eliminating the wet etching process to solve the disadvantages of the existing process, and using a wet etching apparatus. There are many benefits to cost reduction and TAT management.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는 습식 식각 공정을 생략하여 비아 와인 컵(via wine cup) 구조를 형성할 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of forming a via wine cup structure by omitting a wet etching process.
종래 기술에 따른 반도체 소자의 제조방법에 있어서 배리어 메탈 및 메탈 매립 효율을 향상시키기 위해 비아 와인 컵(via wine cup) 구조를 형성하는 것이 일반적이다. 이러한 비아 와인 컵 구조는 인터커넥션 프로세스(interconnectionprocess)에서 많이 사용하는 구조중의 하나이다.In the method of manufacturing a semiconductor device according to the prior art, it is common to form a via wine cup structure in order to improve barrier metal and metal filling efficiency. This via wine cup structure is one of the structures frequently used in the interconnection process.
그러나, 종래 기술에 따른 반도체 소자의 제조방법에 있어서는 다음과 같은 문제점이 있었다.However, there is a problem in the method of manufacturing a semiconductor device according to the prior art as follows.
종래 기술에 있어서, 비아 와인 컵 구조를 형성하기 위해선 습식 식각(wet etch)과 건식 식각(dry etch) 공정을 사용하는 방법을 많이 사용하여 왔는데, 이로 인하여 공정단계가 복잡하였고, 공정단가가 올라가 소자의 생산 원가 관리가 어렸웠다. 또한 공정 TAT(turn around time) 관리도 어렵다는 문제점도 있었다.In the prior art, many methods using wet etching and dry etching processes have been used to form a via wine cup structure, which has complicated the process steps and increased the unit cost. Production cost management was difficult. In addition, there was a problem that it is difficult to manage the process turn around time (TAT).
이에 본 발명은 상기한 종래 기술상의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 후식각처리(PET) 공정을 건식 식각 공정에 도입함으로써 습식 식각 공정을 생략하여 비아 와인 컵 구조를 형성할 수 있는 반도체 소자의 제조방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-mentioned problems in the prior art, an object of the present invention is to introduce a post-etching (PET) process in the dry etching process to omit the wet etching process to form a via wine cup structure The present invention provides a method for manufacturing a semiconductor device.
도 1 내지 도 4는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 각 공정별 단면도.1 to 4 are cross-sectional views for each process for explaining a method of manufacturing a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
90; 반도체 기판100; 제1절연막90; Semiconductor substrate 100; First insulating film
110; 금속층120,120a; 라이너110; Metal layers 120 and 120a; Liner
130,130a; 제2절연막140,140a; 포토레지스트 패턴130,130a; Second insulating films 140 and 140a; Photoresist pattern
150; 비아홀150a; 비아 와인 컵150; Via hole 150a; Via Wine Cup
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은, 제1절연막이 형성된 반도체 기판을 준비하는 단계; 상기 제1절연막상에 금속층을 형성하고 라이너와 제2절연막을 형성하는 단계; 상기 금속층이 노출되도록 상기 제2절연막과 라이너를 선택적으로 건식각하여 비아홀을 형성하는 단계; 상기 비아홀이 형성된 구조물에 인시튜로 산소를 이용하거나 또는 산소와 불활성기체를 이용하여 후식각처리(PET)하는 단계; 및 상기 제2절연막을 선택적으로 건식각하여 비아 와인 컵 구조를 형성하는 단계를 포함하는 것을 특징으로 한다.A semiconductor device manufacturing method according to the present invention for achieving the above object comprises the steps of preparing a semiconductor substrate having a first insulating film; Forming a metal layer on the first insulating layer, and forming a liner and a second insulating layer; Selectively dry etching the second insulating layer and the liner to expose the metal layer to form a via hole; Post-etching (PET) using oxygen in situ on the via hole formed structure or using oxygen and an inert gas; And selectively dry etching the second insulating layer to form a via wine cup structure.
상기 산소와 불활성 기체를 이용하여 후식각처리는 단계는 산소의 유량이 50~500sccm이고, 불활성기체의 유량은 100~500sccm인 것을 특징으로 한다.The post etching process using the oxygen and the inert gas is characterized in that the flow rate of oxygen is 50 ~ 500sccm, the flow rate of the inert gas is 100 ~ 500sccm.
상기 비아 와인 컵 구조를 형성하는 단계는 x가 1~5이고 y는 4~8인 플루오르카본 계열의 가스 CXFY를 사용하는 것을 특징으로 한다.The forming of the via wine cup structure is characterized in that x is 1 to 5 and y is 4 to 8 fluorocarbon-based gas C X F Y.
본 발명에 의하면, PET 공정을 건식 식각 공정에 도입함으로써 바이 와인 컵 구조 형성시 습식 식각 공정을 생략할 수 있게 된다.According to the present invention, by introducing the PET process into the dry etching process, it is possible to omit the wet etching process when forming the bi-wine cup structure.
이하, 본 발명에 따른 반도체 소자의 제조방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 4는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 각 공정별 단면도이다.1 to 4 are cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 제조방법은, 도 1에 도시된 바와 같이, 제1절연막(100)이 형성된 반도체 기판(90)을 준비한다. 상기 반도체 기판(90)상에는 도시하지 않았지만 여러 다양한 구조물이 형성되어 있을 수 있다.In the method of manufacturing a semiconductor device according to the present invention, as shown in FIG. 1, a semiconductor substrate 90 on which a first insulating film 100 is formed is prepared. Although not shown, various structures may be formed on the semiconductor substrate 90.
그다음, 상기 제1절연막(100)상에 금속층(110)을 형성한다. 그다음, 상기 금속층(110)을 피복하는 라이너(120;liner)와 제2절연막(130)을 형성한다.Next, a metal layer 110 is formed on the first insulating film 100. Next, a liner 120 and a second insulating layer 130 covering the metal layer 110 are formed.
이어서, 도 2에 도시된 바와 같이, 상기 제2절연막(130)상에 비아홀을 형성하기 위하여 포토레지스트 도포, 노광 및 현상공정 등으로 소정의 형태를 지닌 포토레지스트 패턴(140)을 형성한다.Subsequently, as shown in FIG. 2, a photoresist pattern 140 having a predetermined shape is formed through photoresist coating, exposure, and development processes to form via holes on the second insulating layer 130.
계속하여, 상기 포토레지스트 패턴(140)을 마스크로 하는 건식각(dry etch)공정으로 상기 금속층(120)이 노출하도록 상기 제2절연막(130)과 라이너(120)를 선택적으로 제거한다. 그리하여, 패터닝(patterning)된 제2절연막(130a)과 라이너(120a)를 관통하고 금속층(110)을 일부 노출시키는 일반적인 형태를 지닌 비아홀(150)을 형성한다.Subsequently, the second insulating layer 130 and the liner 120 are selectively removed to expose the metal layer 120 in a dry etch process using the photoresist pattern 140 as a mask. Thus, a via hole 150 having a general shape penetrating the patterned second insulating layer 130a and the liner 120a and partially exposing the metal layer 110 is formed.
이어서, 도 3에 도시된 바와 같이, 상기 비아홀(150)이 형성된 반도체 기판(90)상의 구조물에 대해 후식각처리(PET;post etch treatment) 공정을 실시한다. 상기 후식각처리(PET)는 산소를 이용하거나, 또는 헬륨(He), 아르곤(Ar) 또는 크세논(Xe)과 같은 8족기체인 불활성기체(inert gas)와 산소를 이용한다.Next, as shown in FIG. 3, a post etch treatment (PET) process is performed on the structure on the semiconductor substrate 90 on which the via holes 150 are formed. The post-etching process (PET) uses oxygen, or inert gas and oxygen, which is a group 8 gas such as helium (He), argon (Ar), or xenon (Xe).
예를 들어, 50~500sccm의 산소와 100~500sccm의 불활성기체를 이용하여 후식각처리를 진행하면, 상기 비아홀(150) 주변에 있던 포토레지스트 패턴(140)은 측면방향으로 제거되기 때문에 도3에 도시된 것과 같은 중간구조로 된다.For example, when the post-etching process is performed using 50 to 500 sccm of oxygen and 100 to 500 sccm of inert gas, the photoresist pattern 140 around the via hole 150 is removed in the lateral direction. It has an intermediate structure as shown.
한편, 후식각처리(PET)에 있어서 플라즈마 소스(plasma source)를 만드는 방식으로는 MERIE, TCP 또는 ICP 등을 이용할 수 있다.Meanwhile, MERIE, TCP, or ICP may be used as a method of making a plasma source in the post etching process (PET).
그다음, 도 4에 도시된 바와 같이, 상기 제2절연막(130a)중 상기 비아홀(150) 내면쪽의 상단 모서리부분을 선택적으로 건식각(dry etch)하여 마치 와인 컵(wine cup)과 같은 형태를 지닌 비아홀 구조, 즉 비아 와인 컵(150a:via wine cup) 구조를 형성한다. 이때, 상기 비아 와인 컵(150a) 구조를 형성하는 건식각 공정은 x가 1~5이고 y는 4~8인 플루오르카본 계열의 가스 CXFY를 사용한다.Next, as shown in FIG. 4, the upper edge portion of the second insulating layer 130a on the inner surface of the via hole 150 is selectively dry etched to have a shape like a wine cup. It has a via hole structure, ie, via wine cup (150a) structure. In this case, in the dry etching process of forming the via wine cup 150a structure, x is 1 to 5 and y is 4 to 8, and a fluorocarbon gas C X F Y is used.
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.
이상에서 설명한 바오 같이, 본 발명에 따른 반도체 소자의 제조방법에 이Td서는 다음과 같은 효과가 있다.As described above, this Td document has the following effects in the method of manufacturing a semiconductor device according to the present invention.
본 발명에 있어서는, PET 공정을 건식 식각 공정에 도입하여 습식 식각 공정을 생략하여 기존 공정의 단점을 해결함으로써 습식 식각 장비를 사용하지 않게 되어 원가 절감 및 TAT 관리에 많은 이점이 발생하는 효과가 있다.In the present invention, by introducing the PET process in the dry etching process by eliminating the wet etching process to solve the shortcomings of the existing process is not using the wet etching equipment has the effect of generating a lot of advantages in cost reduction and TAT management.
Claims (4)
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| KR1020020036766A KR20040001534A (en) | 2002-06-28 | 2002-06-28 | Method for fabricating semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100752189B1 (en) * | 2006-08-07 | 2007-08-27 | 동부일렉트로닉스 주식회사 | Manufacturing Method of Semiconductor Device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100752189B1 (en) * | 2006-08-07 | 2007-08-27 | 동부일렉트로닉스 주식회사 | Manufacturing Method of Semiconductor Device |
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