KR20030093575A - Method for fabricating capacitor using high selectivity nitride - Google Patents
Method for fabricating capacitor using high selectivity nitride Download PDFInfo
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- KR20030093575A KR20030093575A KR1020020031160A KR20020031160A KR20030093575A KR 20030093575 A KR20030093575 A KR 20030093575A KR 1020020031160 A KR1020020031160 A KR 1020020031160A KR 20020031160 A KR20020031160 A KR 20020031160A KR 20030093575 A KR20030093575 A KR 20030093575A
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- silicon nitride
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- 150000004767 nitrides Chemical class 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000003990 capacitor Substances 0.000 title claims abstract description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 38
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 38
- 239000010409 thin film Substances 0.000 claims abstract description 25
- 238000003860 storage Methods 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000011229 interlayer Substances 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims abstract description 15
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000010408 film Substances 0.000 claims description 44
- 239000007789 gas Substances 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 239000000203 mixture Substances 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- 238000000427 thin-film deposition Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910003902 SiCl 4 Inorganic materials 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910020776 SixNy Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 캐패시터 제조방법에 관한 것으로서, 보다 상세하게는 고선택성 나이트라이드를 이용한 캐패시터 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor using high selectivity nitride.
최근에는 디램소자의 캐패시터 형성공정에 있어서, 스토리지노드 산화막의 식각배리어로서 실리콘질화막(silicon nitride film)을 사용하고 있다. 이는 실리콘나이트라이드가 실리콘산화막에 비해 식각선택비가 있기 때문이며, 이러한 구조를 이용할 경우 소자의 선폭 축소(silicon-sizing)에 의한 프로파일 형성을 보다 쉽게 할 수 있기 때문이다.In recent years, a silicon nitride film is used as an etching barrier of a storage node oxide film in a capacitor forming process of a DRAM device. This is because silicon nitride has an etching selectivity compared to silicon oxide, and this structure makes it easier to form a profile due to silicon-sizing of the device.
그러나, 종래의 기술로 캐패시터를 형성할 경우 실리콘 나이트라이드가 완벽한 산화막의 식각배리어로서의 역할을 하지 못해 식각공격(etch attack)을 받으므로써 나이트라이드 펀치(nitride punch)가 일어나 트랜지스터의 쇼트(short) 및 폴(fall)의 원인이 될 수 있으며, 나이트라이드 두께를 증가시켜 식각배리어로 사용할 경우 실리콘나이트라이드와 하부물질인 실리콘산화막와의 미세한 스트레스(micro-stress)에 의해 특정 패턴에서 크랙을 유발하여 소자의 동작이 정상적으로 이루어지지 않는 현상이 나타나는 상태이다.However, when a capacitor is formed by the conventional technique, silicon nitride does not serve as an etch barrier of a perfect oxide film and is subjected to an etch attack, resulting in a nitride punch, resulting in short and short transistors. If it is used as an etching barrier by increasing the thickness of the nitride, it may cause cracks in a specific pattern by micro-stress between silicon nitride and the underlying silicon oxide film. This is a state where the operation does not work properly.
도 1에 도시된 바와같이, 종래의 캐패시터 제조시에 주변지역에서의 산화막 에천트에 의한 나이트라이드 펀치현상이 나타남을 알 수 있다.As shown in FIG. 1, it can be seen that the nitride punch phenomenon caused by the oxide film etchant in the surrounding area appears in the conventional capacitor manufacturing.
또한, 이러한 펀치현상을 없애기 위해 나이트라이드를 두껍게 증착할 경우에, 도 2에 도시된 바와같이, 나이트라이드와 하부물질과의 스트레스에 의한 나이트라이드크랙 현상이 나타남을 알 수 있다.In addition, when the nitride is thickly deposited to eliminate such a punch phenomenon, as shown in FIG. 2, it can be seen that the nitride crack phenomenon due to the stress between the nitride and the underlying material appears.
상기의 문제점은 소자의 디자인 룰이 축소되면서 캐패시터 높이가 증가하면서 더욱 증대되어 나타나고 있다.The above problems are further increased as the capacitor height increases as the design rule of the device is reduced.
이와 같은 문제점을 해결하기 위하여 실리콘산화막과의 식각선택비가 큰 물질을 사용하거나, 실리콘나이트라이드를 사용하면서 고선택비를 갖는 식각공정을 적용하는 방법을 개발하고 있으나 장비 투자 및 양산성에 있어 또 다른 문제가 되고 있다.In order to solve this problem, a method of using a material having a high etching selectivity with a silicon oxide film or an etching process having a high selectivity while using silicon nitride is being developed, but it is another problem in equipment investment and mass production. It is becoming.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 스토리지노드 산화막 식각시에 실리콘산화막과의 선택비를 높여 실리콘 나이트라이드의 펀치를 방지하여 식각공정마진을 향상시킴과 동시에 하부층과의 스트레스를 감소하여 스트레스에 기인한 크랙발생을 방지하여 반도체 수율을 향상시킬 수 있는 고선택성 나이트 라이드를 이용한 캐패시터 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, by increasing the selectivity with the silicon oxide film during the etching of the storage node oxide to prevent the punch of silicon nitride to improve the etching process margin and at the same time the lower layer and It is an object of the present invention to provide a method of manufacturing a capacitor using a high selectivity nitride which can improve the semiconductor yield by reducing the stress caused by stress.
도 1은 종래기술에 따른 반도체소자의 제조방법에 있어서, 주변지역에서의 산화막 에천트에 의한 나이트라이드 펀치 현상을 나타낸 사진.1 is a photo showing a nitride punch phenomenon by the oxide film etchant in the peripheral area in the method of manufacturing a semiconductor device according to the prior art.
도 2는 종래기술에 따른 반도체소자의 제조방법에 있어서, 펀치현상을 없애기 위해 나이트라이드를 두껍게 증착할 경우 나타나는 크랙(crack) 현상을 보여 주는 사진.FIG. 2 is a photo showing a crack phenomenon when a nitride is thickly deposited to eliminate punching in the method of manufacturing a semiconductor device according to the related art. FIG.
도 3 내지 도 5는 본 발명에 따른 고선택성 질화막을 이용한 반도체소자의 제조방법을 설명하기 위한 공정단면도.3 to 5 are process cross-sectional views illustrating a method for manufacturing a semiconductor device using a highly selective nitride film according to the present invention.
도 6은 본 발명에 따른 고선택성 질화막을 이용한 반도체소자의 제조방법에 있어서, 고선택성 나이트라이드를 이용할 경우의 정상적인 주변지역의 모습을 나타낸 사진.6 is a photo showing a state of the normal peripheral region when using a high selectivity nitride in the method of manufacturing a semiconductor device using a high selectivity nitride film according to the present invention.
도 7은 본 발명에 따른 고선택성 나이트라이드의 조성비에 따른 스트레스를 나타낸 그래프.7 is a graph showing the stress according to the composition ratio of the high selectivity nitride according to the present invention.
도 8은 본 발명에 따른 고선택성 나이트라이드의 조성비에 따른 식각률을 나타낸 그래프.8 is a graph showing the etching rate according to the composition ratio of the highly selective nitride according to the present invention.
[도면부호의설명][Description of Drawing Reference]
11 : 반도체기판13 : 층간절연막11: semiconductor substrate 13: interlayer insulating film
15 : 고선택성 나이트라이드막17 : 플러그층15 highly selective nitride film 17 plug layer
19 : 스토리지노드용 산화막21 : 콘택홀19: oxide film for storage node 21: contact hole
상기 목적을 달성하기 위한 본 발명에 따른 고선택성 나이트라이드를 이용한 캐패시터 제조방법은, 반도체기판상에 층간절연막을 형성하는 단계; 상기 층간 절연막상에 화학양론적 조성비가 실리콘리치한 실리콘나이트라이드박막을 형성하는 단계; 상기 실리콘나이트라이드박막 및 층간절연막을 패터닝하여 스토리지노드콘택을 형성하는 단계; 상기 스토리지노드콘택내에 플러그를 형성하는 단계; 상기 플러그를 포함한 실리콘나이트라이드박막상에 층간절연막을 형성하는 단계; 및 상기 층간 절연막을 패터닝하여 스토리지노드 형성지역을 한정하는 단계를 포함하여 구성되는 것을 특징으로한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor using high selectivity nitride, the method including: forming an interlayer insulating film on a semiconductor substrate; Forming a silicon nitride thin film having a stoichiometric composition ratio on the interlayer insulating film; Patterning the silicon nitride thin film and the interlayer insulating film to form a storage node contact; Forming a plug in the storage node contact; Forming an interlayer insulating film on the silicon nitride thin film including the plug; And patterning the interlayer insulating film to define a storage node formation region.
또한, 실리콘나이트라이드박막의 굴절율은 2.0 ∼2.4이며, 상기 실리콘나이트라이드박막 증착은 600 내지 800 ℃ 온도범위에서 진행하되, 챔버 형태의 LPCVD 반응로에서 증착하는 것을 특징으로한다.In addition, the refractive index of the silicon nitride thin film is 2.0 to 2.4, the silicon nitride thin film deposition is carried out in the temperature range of 600 to 800 ℃, characterized in that the deposition in the chamber type LPCVD reactor.
그리고, LPCVD 챔버내에서 실리콘의 소오스가스로는 SiH4, SiCl4, SiH2Cl2등의 가스를 사용하며, 질소의 소오스 가스로는 NH3, N2을 선택적 으로 사용하는 것을 특징으로한다.In the LPCVD chamber, gases such as SiH 4 , SiCl 4 , and SiH 2 Cl 2 are used as the source gas of silicon, and NH 3 and N 2 are selectively used as the source gas of nitrogen.
더욱이, 상기 실리콘나이트라이드박막 증착시 반응로내의 가스 비율은 1:1 내지 50:1 (NH3:SiH4)로 조절하고, 유량조절기를 통해 수 scm 내지 수 slpm까지 각각 정량화하여 공급하는 것을 특징으로한다.In addition, the silicon nitride thin film deposition during the deposition gas ratio in the reactor is adjusted to 1: 1 to 50: 1 (NH 3 : SiH 4 ), characterized in that to supply the quantitative supply of several scm to several slpm through the flow controller Should be.
또한, 상기 실리콘나이트라이드박막 증착시에 100 내지 400 torr 압력에서 진행하는 것을 특징으로한다.In addition, the silicon nitride thin film deposition is characterized in that it proceeds at 100 to 400 torr pressure.
그리고, 상기 실리콘나이트라이드박막은 단일막 또는 실리콘/질소의 조성이 다른 다층막을 인시튜(in-situ)로 증착하는 것을 특징으로한다.The silicon nitride thin film is characterized in that a single film or a multilayer film having a different composition of silicon / nitrogen is deposited in-situ.
(실시예)(Example)
이하, 본 발명에 따른 고선택성 나이트라이드를 이용한 캐패시터 제조방법을첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a capacitor using high selectivity nitride according to the present invention will be described in detail with reference to the accompanying drawings.
도 3 내지 도 5는 본 발명에 따른 고선택성 질화막을 이용한 반도체소자의 제조방법을 설명하기 위한 공정단면도이다.3 to 5 are process cross-sectional views illustrating a method of manufacturing a semiconductor device using a highly selective nitride film according to the present invention.
도 6은 본 발명에 따른 고선택성 질화막을 이용한 반도체소자의 제조방법에 있어서, 고선택성 나이트라이드를 이용할 경우의 정상적인 주변지역의 모습을 나타낸 사진이다.FIG. 6 is a photograph illustrating a normal peripheral region when a high selectivity nitride is used in the method of manufacturing a semiconductor device using the high selectivity nitride film according to the present invention.
도 7은 본 발명에 따른 고선택성 나이트라이드의 조성비에 따른 스트레스를 나타낸 그래프이고, 도 8은 본 발명에 따른 고선택성 나이트라이드의 조성비에 따른 식각률을 나타낸 그래프이다.7 is a graph showing the stress according to the composition ratio of the high selectivity nitride according to the present invention, Figure 8 is a graph showing the etching rate according to the composition ratio of the high selectivity nitride according to the present invention.
본 발명에 따른 고선택성 나이트라이드를 이용한 캐패시터 제조방법은, 먼저 도면에는 도시하지 않았지만, 반도체기판(11)상에 워드라인 및 비트라인을 형성한후 산화막 계열의 층간절연막(13)을 증착한다. 이때, 상기 층간절연막으로는 BPSG 또는 HDP 등의 산화막 계열의 물질을 사용한다.In the capacitor manufacturing method using the highly selective nitride according to the present invention, although not shown in the drawing, first, after forming word lines and bit lines on the semiconductor substrate 11, an oxide-based interlayer insulating layer 13 is deposited. In this case, an oxide-based material such as BPSG or HDP is used as the interlayer insulating film.
그다음, 상기 층간절연막(13)상에 실리콘 리치의 배리어 나이트라이드막 (15)을 증착한다. 이때, 상기 실리콘나이트라이드박막의 굴절율은 2.0 ∼2.4정도이다.Then, a silicon rich barrier nitride film 15 is deposited on the interlayer insulating film 13. At this time, the refractive index of the said silicon nitride thin film is about 2.0-2.4.
또한, 상기 실리콘나이트라이드박막의 증착은, 보통 LPCVD (저압화학 증착방법)이나 PECVD(plasma enhanced CVD)의 방법등을 사용하는데, 실리콘나이트 라이드의 막질 때문에 배리어막을 증착하는 경우에는 주로 LPCVD방법을 사용하고 있다. 그렇지만, 통상의 LPCVD는 퍼니스 타입의 반응로에서 증착하기 때문에 화학양론적 조성비가 3:4(Si:N)로 일정하게 유지된다. 따라서, 이러한 이유로 인해, 본 발명에서는 실리콘나이트라이드박막을 챔버형태의 LPCVD 방식으로 증착한다.In addition, the deposition of the silicon nitride thin film, LPCVD (low pressure chemical vapor deposition method) or PECVD (plasma enhanced CVD) method, etc. are usually used, but when the barrier film is deposited due to the film quality of silicon nitride, mainly LPCVD method is used. Doing. However, since conventional LPCVD is deposited in a furnace type reactor, the stoichiometric composition ratio is kept constant at 3: 4 (Si: N). Therefore, for this reason, in the present invention, a silicon nitride thin film is deposited by a chamber type LPCVD method.
또한, 챔버체적을 최소화하여 소오스 가스로 사용하는 SiH4계열, 즉 SiH4, SiCl4, SiH2Cl2등과 NH3계열, 즉 NH3, N2등의 가스비율을 조절하여 유량조절기로 정량된 양을 플로우시켜, 고유전 특성을 갖는 실리콘 나이트 라이드 박막을 형성하므로써 공정조건에서 요구되는 배리어 특성을 유지시키기 위해 SiH4/NH3가스의 가스유량을 변경시킬 수 있고, 후속 식각 공정진행시에 산화막의 높은 선택비를 유지시키기 위하여 실리콘리치의 실리콘나이트라이드박막을 형성하게 된다.In addition, the gas volume of the SiH 4 series, namely SiH 4 , SiCl 4 , SiH 2 Cl 2, and NH 3 series, that is, NH 3 , N 2, etc., used as a source gas by minimizing the chamber volume, was quantified by the flow controller. By flowing the amount, it is possible to change the gas flow rate of the SiH 4 / NH 3 gas in order to maintain the barrier properties required in the process conditions by forming a silicon nitride thin film having high dielectric properties, the oxide film during the subsequent etching process In order to maintain a high selectivity of, a silicon nitride thin film of silicon rich is formed.
이때, 박막 증착시의 압력은 100 ∼ 400 torr에서 일정하게 유지하며, 증착온도는 600 ∼ 800 ℃의 온도범위, 그리고 가스비율은 NH3가스의 유량속도를 증가시키는 조건하에서 실시한다. 또한, 상기 실리콘나이트 라이드박막 증착시 반응로내의 가스 비율은 1:1 내지 50:1 (NH3:SiH4)로 조절하고, 유량조절기를 통해 수 scm 내지 수 slpm까지 각각 정량화하여 공급한다.At this time, the pressure during thin film deposition is kept constant at 100 to 400 torr, the deposition temperature is carried out under the conditions of increasing the flow rate of NH 3 gas, the temperature range of 600 to 800 ℃, and the gas ratio. In addition, the gas ratio in the reactor during the deposition of the silicon nitride thin film is adjusted to 1: 1 to 50: 1 (NH 3 : SiH 4 ), and quantified to several scm to several slpm through a flow controller, respectively.
이어서, 도면에는 도시하지 않았지만, 상기 실리콘나이트라이드막(15)상에 스토리지 노드 콘택지역을 정의하는 감광막패턴을 형성한후 이를 마스크로 상기 나이트 라이드막(15)과 층간절연막(13)을 패터닝하여 스토리지노드 콘택홀(미도시)을 형성한다.Subsequently, although not shown in the drawing, a photoresist pattern defining a storage node contact region is formed on the silicon nitride layer 15, and then the nitride layer 15 and the interlayer dielectric layer 13 are patterned using the mask. A storage node contact hole (not shown) is formed.
그다음, 도 4에 도시된 바와같이, 상기 스토리지노드콘택홀(미도시)을 포함한 나이트라이드막(15)상에 상기 스토리지노드 콘택홀을 매립하는 플러그용 폴리 실리콘층(미도시)을 증착한후 이를 CMP 또는 전면식각하여 상기 스토리지노드콘택홀(미도시)내에 플러그(17)를 형성한다.Next, as shown in FIG. 4, after depositing the polysilicon layer (not shown) for embedding the storage node contact hole on the nitride layer 15 including the storage node contact hole (not shown). The CMP or the front surface is etched to form a plug 17 in the storage node contact hole (not shown).
이어서, 도 5에 도시된 바와같이, 감광막패턴(미도시)을 제거한후 상기 전체 구조의 상면에 산화막 계열의 스토리지노드 산화막(19)을 증착한후 스토리지노드 형성 지역을 정의하기 위해 상기 산화막(19)을 마스크공정(미도시)에 의해 패터닝 하여 스토리지노드 형성지역을 한정하는 콘택홀(21)을 형성한다.이때, 상기 패터닝 공정은 상기 실리콘나이트라이드막(15)을 배리어로 하여 상기 산화막(19)을 식각한다.Subsequently, as shown in FIG. 5, after removing the photoresist pattern (not shown), an oxide-based storage node oxide layer 19 is deposited on the upper surface of the entire structure, and then the oxide layer 19 is defined to define a storage node formation region. ) Is patterned by a mask process (not shown) to form a contact hole 21 defining a storage node formation region. In this case, the patterning process uses the silicon nitride film 15 as a barrier to form the contact hole 21. Etch).
또한, 상기 산화막으로는 소자의 분리에 사용하는 산화막을 증착한후 포토레지스트를 사용하여 패터닝한다. 이때, 콘택에 정확한 정렬을 하기 어렵기 때문에 콘택크기보다 더 크게 패터닝을 한후 질화막을 식각배리어로 사용하여 콘택식각을 한다. 또한, 실리콘나이트라이드박막은 실리콘리치(Si rich)하기 때문에 실리콘산화막과의 식각선택비가 탁월하여 층간절연막위에서 그 손실을 최소화할 수 있어 식각공정의 안정성을 얻을 수 있고 워드라인 및 비트라인과의 쇼트를 방지할 수 있다.Further, as the oxide film, an oxide film used for separation of devices is deposited and then patterned using a photoresist. At this time, since it is difficult to align the contact precisely, the contact is etched using the nitride film as an etching barrier after patterning larger than the contact size. In addition, since the silicon nitride thin film is silicon rich, the etching selectivity with the silicon oxide film is excellent, so that the loss can be minimized on the interlayer insulating film, so that the stability of the etching process can be obtained and the short with the word line and the bit line. Can be prevented.
도 7에 도시된 바와같이, 실리콘과 질소의 조성비에 따른 미세한 스트레스를관찰한 결과, 질소에 비해 실리콘이 리치한 경우에 스트레스가 미세하게 나타남을 알 수 있었다.As shown in FIG. 7, as a result of observing the minute stress according to the composition ratio of silicon and nitrogen, it can be seen that the stress is fine when silicon is rich compared to nitrogen.
또한, 도 8에 도시된 바와같이, 실리콘나이트라이드박막의 실리콘과 질소의 조성비에 따른 산화막 식각률을 비교검토한 결과, 종래의 PE 나이트라이드박막의 경우에 비해 실리콘이 리치한 고선택성 나이트라이드박막을 적용한 경우에 식각률이 감소함을 알 수 있다.In addition, as shown in FIG. 8, as a result of comparing and comparing the oxide etch rate according to the composition ratio of silicon and nitrogen of the silicon nitride thin film, a highly selective nitride thin film in which silicon is rich is compared with the conventional PE nitride thin film. It can be seen that the etching rate decreases when applied.
상기에서 설명한 바와같이, 본 발명에 따른 고선택성 나이트라이드를 이용한 캐패시터 제조방법에 의하면, 고선택성 LPCVD 실리콘나이트라이드를 사용하면 화학양론적 조성비가 실리콘 리치인 SixNy(x〉y)를 형성할 수 있어 기존에 사용하는 Si3N4보다 실리콘산화막과의 식각선택비를 높여 C4F8, CH2F2계열의 에천트에 의한 나이트라이드 박막의 손실을 줄일 수 있기 때문에 스토리지노드 산화막 식각배리어로서 효율적인 특성을 갖게 된다.As described above, according to the method of manufacturing a capacitor using a high selectivity nitride according to the present invention, the use of a high selectivity LPCVD silicon nitride can form SixNy (x> y) having a stoichiometric composition ratio of silicon rich. It is more efficient as a storage node oxide etching barrier because it can reduce the loss of nitride thin film caused by C 4 F 8 and CH 2 F 2 series etchant by increasing the etching selectivity with silicon oxide film than Si 3 N 4. Will have characteristics.
특히, 실리콘 리치 실리콘나이트라이드 박막의 경우 굴절율이 2.0 ∼2.4 (Si3N4의 굴절율은 1.8∼2.0임)정도로 증가하여 폴리실리콘에 가까운 특성을 갖기 때문에 SiO2와의 식각률에 선택비가 커지게 되어 질화막 펀치(nitride punch)를 없애므로써 스토리지노드 산화막 식각공정의 안정성을 가져 오며, 산화막 에천트에 의한 주변지역의 PMOS나 NMOS 트랜지스터의 쇼트(short) 및 자기정렬콘택 실패(SAC; self align contact fail)을 방지할 수 있다.Particularly, in the case of silicon rich silicon nitride thin films, the refractive index increases to about 2.0 to 2.4 (the refractive index of Si 3 N 4 is about 1.8 to 2.0), which is close to polysilicon, and thus the selectivity is increased in etching rate with SiO 2. It eliminates the punch, resulting in stability of the storage node oxide etch process, and short and self align contact fail (SAC) of PMOS or NMOS transistors in the surrounding area by oxide etchant. You can prevent it.
이와 더블어 Si 리치 나이트라이드막은, 도 6에서와 같이, 하부물질(보통은 산화막 계열임.)과의 미세한 스트레스를 완화하여 크랙을 발생시키지 않아 후속공정에 의한 소자의 열화를 방지하여 수율의 향상을 가져 올 수 있는 장점이 있다.As shown in FIG. 6, the double-Si Si-rich nitride film, as shown in FIG. 6, mitigates micro stresses with the underlying material (usually an oxide film series) and does not generate cracks to prevent deterioration of the device due to subsequent processes, thereby improving yield. There are advantages that can be brought.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
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