KR20030058507A - Method for forming mask pattern of semiconductor device - Google Patents
Method for forming mask pattern of semiconductor device Download PDFInfo
- Publication number
- KR20030058507A KR20030058507A KR1020010088963A KR20010088963A KR20030058507A KR 20030058507 A KR20030058507 A KR 20030058507A KR 1020010088963 A KR1020010088963 A KR 1020010088963A KR 20010088963 A KR20010088963 A KR 20010088963A KR 20030058507 A KR20030058507 A KR 20030058507A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- resist
- semi
- mask pattern
- semiconductor device
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 마스크 패턴 형성방법에 관한 것으로서, 보다 상세하게는 노광광의 선택적 투과와 포토레지스트의 선택적 감광성을 이용하여 이중 다마신 구조의 마스크 패턴을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a mask pattern of a semiconductor device, and more particularly, to a method of forming a mask pattern having a dual damascene structure using selective transmission of exposure light and selective photosensitive property of a photoresist.
반도체소자의 집적도가 높아짐에 따라 기존의 알루미늄배선 공정의 전기적 특성등의 한계로 인해 구리배선공정으로 대체되고 있는 추세이다.As the degree of integration of semiconductor devices increases, there is a tendency to be replaced by copper wiring process due to limitations of electrical characteristics of the existing aluminum wiring process.
이러한 관점에서, 종래기술에 따른 반도체소자의 마스크패턴 형성방법을 도 1 및 2를 참조하여 설명한다.In this regard, a method of forming a mask pattern of a semiconductor device according to the prior art will be described with reference to FIGS. 1 and 2.
도 1 은 종래기술에 따른 반도체소자의 마스크패턴 형성방법을 설명하기 위한 일반적인 이중 다마신 구조의 패턴 단면도이다.1 is a cross-sectional view of a pattern of a general dual damascene structure for explaining a method of forming a mask pattern of a semiconductor device according to the related art.
도 2는 종래기술에 따른 도 1의 일반적인 이중다마신 구조의 패턴평면도 이다.Figure 2 is a pattern plan view of the general dual damascene structure of Figure 1 according to the prior art.
종래기술에 따른 이중다마신 공정을 통한 마스크 패턴 형성방법은, 도 1에 도시된 바와같이, 반도체기판(1)상에 형성된 층간절연막(3)위에 비어홀마스크 (미도시)를 형성한후 이를 마스크로 층간절연막(3)을 선택적으로 제거하여 비어홀(3a)을 형성한다.In the mask pattern forming method using the dual damascene process according to the prior art, a via hole mask (not shown) is formed on the interlayer insulating film 3 formed on the semiconductor substrate 1 as shown in FIG. The interlayer insulating film 3 is selectively removed to form the via hole 3a.
그다음, 트렌치마스크(미도시)를 사용하여 상기 층간절연막(3)을 식각하여 상기 층간절연막(3)내에 트렌치(3b)를 형성한다.Then, a trench mask (not shown) is used to etch the interlayer insulating film 3 to form a trench 3b in the interlayer insulating film 3.
이어서, 상기 트렌치(3b) 및 콘택홀(3a)을 포함한 층간절연막(3)상에 전기도금방식으로 구리물질을 채운후 CMP공정을 통해 평탄화시켜 배선을 형성한다.Subsequently, a copper material is filled on the interlayer insulating film 3 including the trench 3b and the contact hole 3a by an electroplating method and then planarized by CMP process to form a wiring.
그러나, 상기와 같은 종래기술에 의하면, 상기 일반적인 이중 다마신 공정기술은 2번의 마스크 공정과 식각공정을 거치게 되면서 공정수가 많아져 원가 측면에서 불리하며, 소자 집적도 측면에서도 입자 등의 여러 가지 문제점을 야기시킬 수 있다.However, according to the prior art as described above, the general dual damascene process technology undergoes two mask processes and an etching process, resulting in a large number of processes, which is disadvantageous in terms of cost, and causes various problems such as particles in terms of device integration. You can.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 한번의 마스크공정과 식각공정을 통해 이중 마스크패턴을 형성할 수 있어 공정단순화 및 원가절감효과가 우수한 반도체소자의 마스크패턴 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the problems of the prior art, it is possible to form a double mask pattern through a single mask process and an etching process, the mask pattern forming method of a semiconductor device excellent in the process simplification and cost reduction effect The purpose is to provide.
도 1 은 종래기술에 따른 반도체소자의 마스크패턴 형성방법을 설명하기 위한 일반적인 이중 다마신 구조의 패턴 단면도.1 is a cross-sectional view of a pattern of a general double damascene structure for explaining a mask pattern forming method of a semiconductor device according to the prior art.
도 2는 종래기술에 따른 도 1의 일반적인 이중다마신 구조의 패턴 평면도.FIG. 2 is a pattern plan view of the general dual damascene structure of FIG. 1 according to the prior art. FIG.
도 3은 본 발명에 따른 반도체소자의 마스크패턴 형성방법을 설명하기 위한 레티클의 평면도.3 is a plan view of a reticle for explaining a method of forming a mask pattern of a semiconductor device according to the present invention;
도 4는 본 발명에 따른 반도체소자의 마스크패턴 형성방법에 있어서, 선택적 감광성을 이용한 이중다마신 포토공정을 나타낸 공정단면도.Figure 4 is a process cross-sectional view showing a double damascene photo process using a selective photosensitive in the mask pattern forming method of a semiconductor device according to the present invention.
도 5는 본 발명에 따른 반도체소자의 마스크패턴 형성방법에 있어서, 현상후 얻어진 레지스트패턴을 나타낸 단면도.5 is a cross-sectional view showing a resist pattern obtained after development in the method of forming a mask pattern of a semiconductor device according to the present invention.
[도면부호의설명][Description of Drawing Reference]
10 : 패턴이 형성되지 않을 지역 19a : 광감도가 낮은 제1레지스트막10: area where no pattern is to be formed 19a: first resist film having low light sensitivity
19b : 광감도가 높은 제2레지스트막 20 : 트렌치패턴이 형성될 지역19b: second resist film having high photosensitivity 20: region in which trench pattern is to be formed
25 : 콘택홀영역 27 : 트렌치영역25: contact hole area 27: trench area
30 : 콘택홀패턴이 형성될 지역 100 : 레티클30: area where a contact hole pattern is to be formed 100: reticle
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 마스크패턴 형성방법은, 투명성절연기판상에 일정 간격을 두고 형성된 반투과성 물질막과 상기 반투과성 물질막상에 상기 반투과성 물질막간 간격보다 큰 간격을 두고 형성된 광차단막으로 구성된 레티클을 제작하는 단계; 반도체 웨이퍼상에 광감도가 낮은 제1레지스트막과 광감도가 높은 제2레지스트막을 순차적으로 적층하는 단계; 상기 레티클을 통해 광을 상기 반도체웨이퍼상에 조사하여 상기 반투과성물질막을 투과한 광은 상기 광감도가 높은 제2레지스트 막에만 도달되도록 하고, 상기 비어홀영역만큼의 개구된 부분을 투과한 광은 제2레지스트막과 제1레지스트막을 전부 투과하도록 하는 단계; 및 상기 노광된 제1 및 제2 레지스트막을 현상 및 식각공정을 진행하여제1 및 제2 레지스트막패턴을 형성하는 단계를 포함하여 구성되는 것을 특징으로한다.According to an aspect of the present invention, there is provided a method of forming a mask pattern of a semiconductor device, comprising: a semitransparent material film formed at a predetermined interval on a transparent insulating substrate and a light formed at an interval greater than the gap between the semitransparent material film on the semitransparent material film. Manufacturing a reticle composed of a barrier film; Sequentially stacking a first photoresist film having a low light sensitivity and a second photoresist film having a high light sensitivity on a semiconductor wafer; The light transmitted through the reticle onto the semiconductor wafer to pass through the semi-transparent material film reaches only the second resist film having high photosensitivity, and the light transmitted through the opened portion of the via hole region is a second resist. Allowing all of the film and the first resist film to pass through; And developing and etching the exposed first and second resist films to form first and second resist film patterns.
(실시예)(Example)
이하, 본 발명에 따른 반도체소자의 마스크패턴 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a mask pattern of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 반도체소자의 마스크패턴 형성방법을 설명하기 위해 제조된 레티클의 평면도이다.3 is a plan view of a reticle manufactured to explain a method of forming a mask pattern of a semiconductor device according to the present invention.
도 4는 본 발명에 따른 반도체소자의 마스크패턴 형성방법에 있어서, 선택적 감광성을 이용한 이중다마신 포토공정을 나타낸 공정단면도이다.FIG. 4 is a process cross-sectional view illustrating a dual damascene photo process using selective photosensitivity in a method of forming a mask pattern of a semiconductor device according to the present invention.
도 5는 본 발명에 따른 반도체소자의 마스크패턴 형성방법에 있어서, 현상후 얻어진 레지스트패턴을 나타낸 단면도이다.5 is a cross-sectional view showing a resist pattern obtained after development in the method of forming a mask pattern of a semiconductor device according to the present invention.
본 발명에 따른 반도체소자의 마스크패턴을 형성하기 위해 먼저 도 3에 도시된 바와 같이, 레티클(100)을 제작하되, 먼저 패턴이 없는 지역(10)에 크롬처리 되어 있고, 트렌치패턴이 형성될 지역(20)은 몰리브덴 등의 반투과성물질로 형성 되어 있으며, 비어홀이 형성될 지역(30)은 개구되어 있다.In order to form a mask pattern of a semiconductor device according to the present invention, as shown in FIG. 3, a reticle 100 is first manufactured, but first, a region in which a pattern is formed is chromed and a trench pattern is formed. 20 is formed of a semi-permeable material such as molybdenum, and the region 30 in which the via hole is to be formed is opened.
그다음, 도 4에 도시된 바와같이, 반도체웨이퍼(미도시)에 층간절연막(미도시)을 증착한다음 상기 층간절연막(미도시)상에 광감도가 낮은 제1레지스트막 (19a)을 도포한후 상기 제1레지스트막(19a)상에 광민감도가 높은 제2레지스트막 (19b)을 도포하여 이중구조의 포토레지스트막(19)을 형성한다.Next, as shown in FIG. 4, an interlayer insulating film (not shown) is deposited on a semiconductor wafer (not shown), and then the first resist film 19a having low light sensitivity is applied onto the interlayer insulating film (not shown). A second photoresist film 19b having a high photosensitivity is applied onto the first resist film 19a to form a double photoresist film 19.
이어서, 도 3에서 제작된 레티클(100)을 이용하여 노광공정을 진행하되, 몰리브덴으로 이루어진 트렌치패턴이 형성될 지역(20)을 통과한 빛은 개구된 영역(30)과 대비하여 50 % (또는 ±α)의 빛만이 투과되어 제2레지스트막(19b)에 전달된다. 이때, 광민감도가 높은 제2레지스트막(19b)은 50 %의 광량만으로도 충분히 광반응을 수행하고, 하부의 광감도가 낮은 제1레지스트막(19a)은 영향을 받지 않는다.Subsequently, the exposure process is performed using the reticle 100 manufactured in FIG. 3, but the light passing through the region 20 in which the trench pattern made of molybdenum is to be formed is 50% (or 50%) compared with the opened region 30. Only light of ± α) is transmitted and transmitted to the second resist film 19b. At this time, the second resist film 19b having high photosensitivity sufficiently performs photoreaction only with a light amount of 50%, and the first resist film 19a having low photosensitivity is not affected.
또한, 상기 레티클(100)의 개구된 영역(30)을 통과하는 빛은 100 %의 광량 모두가 상하부의 제1 및 제2 레지스트막(19a)(19b)을 투과하게 되므로써 원하는 지역에 비어홀패턴(미도시)을 형성하게 된다.In addition, the light passing through the open area 30 of the reticle 100 transmits 100% of the light amount through the first and second resist films 19a and 19b of the upper and lower parts, thereby forming a via hole pattern ( Not shown).
그다음, 도 5에 도시된 바와같이, 상기 노광공정이 진행된 제1 및 제2레지스트막(19a)(19b)를 현상공정을 거쳐 선택적으로 제거하여 콘택홀영역(25) 및 트렌치영역(27)을 한정하는 레지스트패턴을 형성한다.Next, as shown in FIG. 5, the first and second resist films 19a and 19b subjected to the exposure process are selectively removed through a developing process to remove the contact hole region 25 and the trench region 27. A resist pattern to be defined is formed.
상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 마스크패턴 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the mask pattern forming method of the semiconductor device according to the present invention has the following effects.
본 발명에 따른 반도체소자의 마스크패턴 형성방법에 의하면, 한번의 마스크 공정 및 한번의 식각공정만으로 이중 다마신 패턴을 형성할 수 있다.According to the method of forming a mask pattern of a semiconductor device according to the present invention, a double damascene pattern may be formed by only one mask process and one etching process.
따라서, 기존의 2번의 마스크 공정과 2번의 식각공정 및 2번의 레지스트 제거공정을 모두 각각 한번씩으로 줄일 수 있어 공정단순화 및 원가절감 측면에서 탈월하다.Therefore, the existing two mask processes, two etching processes, and two resist removal processes can be reduced to one time each, which deviates from the viewpoint of process simplification and cost reduction.
또한, 트렌치와 비어홀을 따로 형성하는 경우처럼 정렬과정이 생략되므로 오정렬에 대한 우려가 전혀 없다.In addition, there is no concern about misalignment because the alignment process is omitted as in the case of forming the trench and the via hole separately.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010088963A KR20030058507A (en) | 2001-12-31 | 2001-12-31 | Method for forming mask pattern of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010088963A KR20030058507A (en) | 2001-12-31 | 2001-12-31 | Method for forming mask pattern of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20030058507A true KR20030058507A (en) | 2003-07-07 |
Family
ID=32216411
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010088963A KR20030058507A (en) | 2001-12-31 | 2001-12-31 | Method for forming mask pattern of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20030058507A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101504543B1 (en) * | 2013-03-29 | 2015-03-20 | 삼한박막진공 주식회사 | Mask for forming pattern with double structure and method of manufacturing this |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06282063A (en) * | 1993-03-26 | 1994-10-07 | Hoya Corp | Halftone type phase shift mask |
| KR980003826A (en) * | 1996-06-10 | 1998-03-30 | 쯔지 하루오 | How to Form Multilevel Reticle Systems and Multilevel Photoresist Profiles |
| JP2000208521A (en) * | 1999-01-08 | 2000-07-28 | Seiko Epson Corp | Method for forming wiring of semiconductor device |
| US6436587B1 (en) * | 2000-09-18 | 2002-08-20 | Sharp Laboratories Of America, Inc. | Method of making a multi-level reticle using bi-level photoresist, including a phase-shifted multi-level reticle |
-
2001
- 2001-12-31 KR KR1020010088963A patent/KR20030058507A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06282063A (en) * | 1993-03-26 | 1994-10-07 | Hoya Corp | Halftone type phase shift mask |
| KR980003826A (en) * | 1996-06-10 | 1998-03-30 | 쯔지 하루오 | How to Form Multilevel Reticle Systems and Multilevel Photoresist Profiles |
| JP2000208521A (en) * | 1999-01-08 | 2000-07-28 | Seiko Epson Corp | Method for forming wiring of semiconductor device |
| US6436587B1 (en) * | 2000-09-18 | 2002-08-20 | Sharp Laboratories Of America, Inc. | Method of making a multi-level reticle using bi-level photoresist, including a phase-shifted multi-level reticle |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101504543B1 (en) * | 2013-03-29 | 2015-03-20 | 삼한박막진공 주식회사 | Mask for forming pattern with double structure and method of manufacturing this |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6127096A (en) | Method for reducing photolithographic steps in a semiconductor interconnect process | |
| CN100499069C (en) | Double Damascus copper technology using selected mask | |
| KR100323161B1 (en) | A method for forming self-aligned features | |
| KR930022494A (en) | Manufacturing method of exposure mask and exposure mask substrate and pattern formation method based on exposure mask | |
| US5656414A (en) | Methods of forming tall, high-aspect ratio vias and trenches in photo-imageable materials, photoresist materials, and the like | |
| JP2005107195A (en) | Photomask, method for manufacturing photomask, and method for manufacturing semiconductor device by using the photomask | |
| KR100752180B1 (en) | method for fabricating contact hole of semiconductor device | |
| KR20010017560A (en) | Method for forming dual damascene structure | |
| KR20030058507A (en) | Method for forming mask pattern of semiconductor device | |
| US5902717A (en) | Method of fabricating semiconductor device using half-tone phase shift mask | |
| KR100390963B1 (en) | Method of forming a contact hole in a semiconductor device | |
| KR100480811B1 (en) | Exposure Mask and Exposure Method Using the Mask | |
| KR100269632B1 (en) | A method fabricating multi-interconnenction line | |
| JP2667517B2 (en) | Method of forming hole in interlayer insulating film | |
| KR100257762B1 (en) | Method for manufacturing metal wiring of semiconductor device | |
| KR100420414B1 (en) | Method for forming a metal line | |
| KR100723466B1 (en) | Photomask for dual damascene process, method thereof and method of forming dual damascene interconnection using the photomask | |
| KR0137997B1 (en) | Fabrication method of contact hole in semiconductor device | |
| KR20030066999A (en) | Method for forming metal wiring of semiconductor device | |
| KR20020030600A (en) | Method for forming the photo resist contact hole | |
| US20020177085A1 (en) | Self-aligned photolithographic process for forming silicon-on-insulator devices | |
| KR100252928B1 (en) | Method for forming metal line of semiconductor device | |
| KR20000014553A (en) | Method for fabricating semiconductor device and mask used thereof | |
| KR100289664B1 (en) | Manufacturing Method of Exposure Mask | |
| KR0172279B1 (en) | Contact mask and method of manufacturing contact hole using it |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |