KR20030047516A - Mos transistor having oxidation barrier spacer and fabrication method thereof - Google Patents
Mos transistor having oxidation barrier spacer and fabrication method thereof Download PDFInfo
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- KR20030047516A KR20030047516A KR1020010078164A KR20010078164A KR20030047516A KR 20030047516 A KR20030047516 A KR 20030047516A KR 1020010078164 A KR1020010078164 A KR 1020010078164A KR 20010078164 A KR20010078164 A KR 20010078164A KR 20030047516 A KR20030047516 A KR 20030047516A
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- 125000006850 spacer group Chemical group 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 230000003647 oxidation Effects 0.000 title description 8
- 238000007254 oxidation reaction Methods 0.000 title description 8
- 230000004888 barrier function Effects 0.000 title description 4
- 230000003064 anti-oxidating effect Effects 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 9
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims abstract description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 3
- 238000005468 ion implantation Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims 1
- 241000293849 Cordylanthus Species 0.000 abstract description 3
- 239000003963 antioxidant agent Substances 0.000 description 8
- 230000003078 antioxidant effect Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
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Abstract
Description
본 발명은 반도체소자 및 그 제조방법에 관한 것으로, 특히 산화방지 스페이서를 갖는 모스 트랜지스터 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a MOS transistor having an antioxidant spacer and a method of manufacturing the same.
모스 전계효과 트랜지스터(MOSFET)를 형성함에 있어서, 반도체기판 상에 소자 분리(isolation) 공정을 실시한다. 이어서, 게이트 전극을 형성하고 기판 표면을 열산화(thermal oxidation) 시켜서 열산화막 형성 공정을 진행한다. 열산화막은 후속 공정인 소오스/드레인 형성을 위한 이온주입시의 완충층(buffer layer) 및 게이트 스페이서 형성시의 식각저지층(etch stop buffer layer)으로 작용하게 된다.In forming a MOS field effect transistor, an isolation process is performed on a semiconductor substrate. Subsequently, the gate electrode is formed and the surface of the substrate is thermally oxidized to thermally oxidize the thermal oxide film. The thermal oxide film serves as a buffer layer for ion implantation for forming a source / drain and an etch stop buffer layer for forming a gate spacer.
첨부된 도 1은 종래기술에 의한 게이트 전극 형성 후에 열산화막 형성 공정을 진행한 모스 트랜지스터의 단면도이다.1 is a cross-sectional view of a MOS transistor in which a thermal oxide film forming process is performed after forming a gate electrode according to the prior art.
도 1을 참조하면, 반도체기판(100) 상에 게이트 절연막(105)과 게이트 전극(110)을 형성하고, 열산화를 시키면 열산화막(115)이 형성된다. 그런데, 게이트 전극(110) 하부의 가장자리와 반도체기판(100)과의 경계면에서도 산화가 진행되면서 측면 확산(lateral diffusion)이 발생하여 게이트 절연막(105)의 두께가 증가하는 게이트 버즈빅(gate bird's beak, 120)이 발생한다. 다음으로, 게이트 스페이서(125)를 형성하고, 이온주입 및 열처리를 실시하면 소오스/드레인(130)이 형성된다.Referring to FIG. 1, when the gate insulating layer 105 and the gate electrode 110 are formed on the semiconductor substrate 100, and thermally oxidized, a thermal oxide film 115 is formed. However, a gate bird's beak in which the thickness of the gate insulating layer 105 increases due to lateral diffusion as oxidation progresses even at the edge between the bottom edge of the gate electrode 110 and the semiconductor substrate 100. , 120). Next, when the gate spacer 125 is formed, and ion implantation and heat treatment are performed, the source / drain 130 is formed.
상기 게이트 버즈빅(120)은 모스 트랜지스터에 있어서 게이트 전극(110)과 소오스/드레인(130)의 오버랩 영역(135) 캐패시턴스(overlap capacitance)를 감소시켜 속도를 증가시키고, 게이트 유기 드레인 누설전류(Gate Induced Drain Leakage current, GIDL)를 감소시키는 장점이 있다. 반면에 산화가 과도하게 진행할 경우 즉, 게이트 버즈빅(120)이 게이트 절연막(105) 내로 과도하게 침투한 경우에는 문턱전압(threshold voltage, Vt)을 증가시키고, 문턱전압의 균일성을 나쁘게 하며 구동전류(driving current)를 감소시키는 등의 단점을 유발하는 문제점이 있다.The gate buzzvik 120 increases the speed by reducing the overlap capacitance of the gate electrode 110 and the source / drain 130 in the MOS transistor, and increases the gate organic drain leakage current (Gate). Induced Drain Leakage Current (GIDL) On the other hand, when the oxidation proceeds excessively, that is, when the gate bird's 120 penetrates into the gate insulating film 105 excessively, the threshold voltage (Vt) is increased, and the uniformity of the threshold voltage is deteriorated. There is a problem that causes disadvantages such as reducing the current (driving current).
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로, 게이트 전극 형성 후에 실시하는 열산화막 공정시에 발생하는 게이트 버즈빅(gate bird's beak)을 최소화 시킬 수 있는 모스 트랜지스터의 제조방법 및 그에 의해 제조된 모스 트랜지스터를 제공하는데 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a method of manufacturing a MOS transistor capable of minimizing gate bird's beak generated during the thermal oxide film process performed after the formation of the gate electrode, and manufacturing by the same The purpose is to provide a MOS transistor.
도 1은 종래기술에 의한 열산화막 형성 공정을 진행한 모스 트랜지스터의 단면도,1 is a cross-sectional view of a MOS transistor having a thermal oxide film forming process according to the prior art,
도 2a 내지 도 2e는 본 발명에 따른 산화방지 스페이서를 갖는 모스 트랜지스터 제조방법을 나타내는 단면도들,2A to 2E are cross-sectional views illustrating a method of manufacturing a MOS transistor having an anti-oxidation spacer according to the present invention;
도 3a 및 도 3b는 각각 종래기술 및 본 발명에 따른 모스 트랜지스터의 구조에 대한 시뮬레이션(simulation) 결과이다.3A and 3B are simulation results of the structure of the MOS transistor according to the prior art and the present invention, respectively.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
200 : 반도체기판205 : 게이트 절연막200: semiconductor substrate 205: gate insulating film
210a : 게이트 전극215a : 산화방지 스페이서210a: gate electrode 215a: anti-oxidation spacer
220 : 열산화막225 : 게이트 버즈빅220: thermal oxide film 225: gate buzz big
230 : 완충막235a : 게이트 스페이서230: buffer film 235a: gate spacer
240 : 소오스/드레인240: source / drain
상기 목적을 달성하기 위한 본 발명의 모스 트랜지스터는 게이트 전극을 형성한 후에 산화방지 스페이서(oxidation barrier spacer)를 게이트 전극 측벽에 형성하는데 특징이 있다.The MOS transistor of the present invention for achieving the above object is characterized by forming an oxidation barrier spacer on the sidewall of the gate electrode after the gate electrode is formed.
즉, 상기 산화방지 스페이서의 두께를 조절함으로써, 후속 열산화막 형성공정시에 발생하는 게이트 절연막 가장자리의 게이트 버즈빅의 길이를 최소화 시킨다. 따라서, 모스 트랜지스터의 문턱전압은 낮아지고 구동전류는 증가되게 된다.That is, by controlling the thickness of the anti-oxidation spacer, the length of the gate buzz big at the edge of the gate insulating film generated during the subsequent thermal oxide film forming process is minimized. Therefore, the threshold voltage of the MOS transistor is lowered and the driving current is increased.
상술한 목적, 특징들 및 장점은 첨부된 도면과 관련한 다음의 상세한 설명을 통하여 보다 분명해 질 것이다.The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.
첨부된 도 2e는 본 발명에 따른 바람직한 일실시예에 의한 산화방지 스페이서를 갖는 모스 트랜지스터의 구조를 나타낸다.2E shows the structure of a MOS transistor having an anti-oxidation spacer according to a preferred embodiment of the present invention.
도 2e를 참조하면, 본 발명의 모스 트랜지스터는 기판(200) 상에 형성된 게이트 절연막(205), 상기 게이트 절연막(205)의 소정영역 상에 형성된 게이트 전극(210a), 상기 게이트 전극(210a)의 측벽에 형성된 산화방지 스페이서(215a), 상기 게이트 전극(210a) 및 상기 산화방지 스페이서(215a)로 이루어진 게이트 패턴의 양 옆의 기판에 형성된 소오스 및 드레인(240)으로 구성된다.Referring to FIG. 2E, the MOS transistor of the present invention includes a gate insulating film 205 formed on the substrate 200, a gate electrode 210a formed on a predetermined region of the gate insulating film 205, and the gate electrode 210a. An anti-oxidation spacer 215a formed on the sidewall, the gate electrode 210a and a source and a drain 240 formed on both sides of the gate pattern formed of the anti-oxidation spacer 215a.
상기 산화방지 스페이서(215a)의 외 측벽에는 게이트 스페이서(235a)를 더 포함하는 것이 바람직하다. 또한, 경우에 따라서는 상기 산화방지 스페이서(215a) 및 상기 게이트 스페이서(235a) 사이에 개재된 완충막(230)을 더 포함할 수 있다.The outer sidewall of the anti-oxidation spacer 215a may further include a gate spacer 235a. In some cases, the semiconductor device may further include a buffer layer 230 interposed between the anti-oxidation spacer 215a and the gate spacer 235a.
상기 게이트 전극(210a)의 가장자리에는 열산화막(220) 형성시에 측면 확산에 의한 게이트 버즈빅(225)이 형성되어 있다. 상기 게이트 버즈빅(225)은 상기 산화방지 스페이서(215a)에 의하여 크기가 조절되어 게이트 전극과 소오스/드레인의 오버랩 영역(245)은 최소화되어 있다.At the edge of the gate electrode 210a, a gate buzz big 225 is formed by side diffusion when the thermal oxide film 220 is formed. The gate buzzvik 225 is sized by the anti-oxidation spacer 215a so that the overlap region 245 of the gate electrode and the source / drain is minimized.
이하, 도 2a 내지 도 2e를 참조하여 본 발명에 따른 산화방지 스페이서를 갖는 모스 트랜지스터 제조방법을 설명한다.Hereinafter, a method of manufacturing a MOS transistor having an anti-oxidation spacer according to the present invention will be described with reference to FIGS. 2A to 2E.
도 2a를 참조하면, 반도체기판(200) 상에 게이트 절연막(205) 및 게이트 전극 도전막(210)을 형성한다. 상기 게이트 절연막(205)은 열산화막(thermal oxide), 실리콘 질화막, 티타늄 산화막, 실리콘 옥시나이트라이드막, 탄탈륨 펜타옥사이드막으로 구성되는 일군으로부터 선택된 적어도 하나를 사용할 수 있다. 상기 게이트 전극 도전막(210)은 폴리사이드, 코발트(Co), 텅스텐(W), 티타늄(Ti), 및 니켈(Ni)로 구성된 일군에서 선택된 적어도 하나를 사용한다.Referring to FIG. 2A, a gate insulating film 205 and a gate electrode conductive film 210 are formed on the semiconductor substrate 200. The gate insulating layer 205 may use at least one selected from the group consisting of a thermal oxide film, a silicon nitride film, a titanium oxide film, a silicon oxynitride film, and a tantalum pentaoxide film. The gate electrode conductive layer 210 uses at least one selected from the group consisting of polyside, cobalt (Co), tungsten (W), titanium (Ti), and nickel (Ni).
도 2b를 참조하면, 상기 게이트 전극 도전막(210)을 사진 식각 공정을 사용하여 패터닝하여 게이트 전극(210a)을 형성한다. 게이트 전극 도전막(210)을 식각시에는 하부의 게이트 절연막(205)을 전부 식각할 수도 있고, 일부 남길 수도 있다. 도면에서는 전부 식각하는 것으로 도시되어 있다.Referring to FIG. 2B, the gate electrode conductive layer 210 is patterned using a photolithography process to form the gate electrode 210a. When the gate electrode conductive layer 210 is etched, all of the lower gate insulating layer 205 may be etched or partially left. In the figures all are shown as being etched.
도 2c를 참조하면, 산화방지막(oxidation barrier layer)을 증착한 후에 비등방성 식각을 실시하여 상기 게이트 전극(210a)의 측면에 산화방지 스페이서(215a)를 형성한다. 상기 산화방지막은 산화(oxidation)가 되지 않는 물질인 실리콘 질화막(SiN), 알류미늄 산화막(Al2O2), 탄탈륨 펜타옥사이드(Ta2O5) 중에서 선택된 적어도 하나를 적용할 수 있으며, 두께는 20Å 내지 200Å으로 적용한다.Referring to FIG. 2C, after an oxidation barrier layer is deposited, an anisotropic etching is performed to form an oxidation spacer 215a on the side of the gate electrode 210a. The anti-oxidation film may be applied to at least one selected from silicon nitride film (SiN), aluminum oxide film (Al 2 O 2 ), tantalum pentaoxide (Ta 2 O 5 ), which is a material that is not oxidized, and has a thickness of 20Å. To 200 kPa.
도 2d를 참조하면, 소오스/드레인 형성을 위한 이온주입 공정에서의 완충층 및 게이트 스페이서 형성시의 식각저지층으로 사용되는 열산화막(220)을 형성한다. 상기 열산화막(220)의 형성 온도는 700℃ 내지 1100℃의 범위로 하며, 두께는 20Å 내지 200Å의 범위로 한다.Referring to FIG. 2D, a thermal oxide layer 220 used as a buffer layer in an ion implantation process for forming a source / drain and an etch stop layer for forming a gate spacer is formed. The formation temperature of the thermal oxide film 220 is in the range of 700 ° C to 1100 ° C, and the thickness is in the range of 20 kPa to 200 kPa.
열산화막 형성을 위한 산화가 진행되면서 게이트 버즈빅(225)이 형성되는데, 이는 게이트 전극 하부의 가장자리 게이트 절연막(205)으로의 측면 확산에 기인한다. 그런데, 도 2c에서 형성된 상기 산화방지 스페이서(215a)는 과다한 게이트 버즈빅 형성을 억제한다. 이 때의 게이트 버즈빅(225)의 길이는 산화방지막의 두께에 따라 제어가 가능하여 최소화된 게이트 버즈빅을 형성할 수 있다.As the oxidation for forming the thermal oxide film proceeds, the gate bird's 225 is formed, which is due to the side diffusion into the edge gate insulating layer 205 under the gate electrode. However, the anti-oxidation spacer 215a formed in FIG. 2C suppresses excessive gate buzz big formation. At this time, the length of the gate buzz big 225 can be controlled according to the thickness of the antioxidant film to form a minimized gate buzz big.
도 2e를 참조하면, 식각저지 및 완충을 위해 열산화된 기판 전면에 콘포멀한 완충막(230)을 형성할 수 있다. 이어서, 상기 게이트 전극(210a) 및 상기 산화방지 스페이서(215a)로 이루어진 게이트 패턴을 이온주입 마스크로 사용하여 상기 기판의 전면에 불순물을 주입하여 상기 게이트 패턴의 양 옆의 기판에 저농도 드레인(Lightly Doped Drain, LDD)구조를 위한 저농도 소오스 및 드레인을 형성할 수 있다. 상기 완충막(220)은 화학기상증착법(Chemical Vapor Deposition, CVD)을 사용하여 형성하며, 두께는 20Å 내지 200Å으로 한다.Referring to FIG. 2E, a conformal buffer layer 230 may be formed on the entire surface of the thermally oxidized substrate for etching inhibition and buffering. Subsequently, impurities are implanted into the entire surface of the substrate using a gate pattern including the gate electrode 210a and the anti-oxidation spacer 215a as an ion implantation mask to lightly doped the substrates on both sides of the gate pattern. Low concentration source and drain can be formed for the Drain (LDD) structure. The buffer film 220 is formed by using chemical vapor deposition (CVD), and the thickness is 20 kPa to 200 kPa.
다음으로, 스페이서 절연막을 형성하고 에치백하여 게이트 스페이서(235a)를 형성할 수 있다. 상기 스페이서 절연막은 산화막 또는 실리콘 질화막(SiN)으로 적용할 수 있으며, 두께는 100Å 내지 1000Å의 범위로 한다.Next, the gate insulating layer 235a may be formed by forming and etching back the spacer insulating layer. The spacer insulating film may be applied as an oxide film or a silicon nitride film (SiN), and has a thickness in the range of 100 kV to 1000 kV.
다음으로, 상기 게이트 패턴 및 상기 게이트 스페이서(235a)를 이온주입 마스크로 사용하여 상기 기판의 전면에 불순물을 주입한다. 이어서, 열처리를 실시하여 소오스/드레인(240)을 형성하면, 게이트 전극(210a)의 전압에 따라서 게이트 절연막(205)의 하단에 채널이 형성되어 전류가 흐르는 모스 트랜지스터가 완성된다.Next, impurities are implanted into the entire surface of the substrate using the gate pattern and the gate spacer 235a as an ion implantation mask. Subsequently, when the source / drain 240 is formed by heat treatment, a channel is formed at the lower end of the gate insulating layer 205 according to the voltage of the gate electrode 210a to complete the MOS transistor through which current flows.
도 3a 및 도 3b는 산화방지 스페이서가 있는 경우 및 없는 경우에 대한 TSUPREM의 시뮬레이션(simulation) 결과이다. 시뮬레이션에서는 게이트 절연막은 산화막으로서 35Å을 적용하였다. 열산화막은 증착온도는 850℃로 설정하여, 두께는 80Å으로 진행하였다. 그리고, 산화방지 스페이서가 있는 경우에는 산화방지막을 실리콘 질화막(SiN)으로서 두께는 50Å으로 진행하였다.3A and 3B show simulation results of TSUPREM with and without antioxidant spacers. In the simulation, 35 kV was applied to the gate insulating film as the oxide film. The thermal oxidation film was set at a deposition temperature of 850 ° C. and a thickness of 80 kPa. In the case where the antioxidant spacer was present, the thickness of the anti-oxidation film was 50 nPa as the silicon nitride film (SiN).
시뮬레이션에서는 게이트 버즈빅의 침투 및 문턱전압과 구동전류 특성을 평가하였다.In the simulation, the penetration and threshold voltage and driving current characteristics of the gate buzz big were evaluated.
도 3a를 참조하면, 산화방지 스페이서가 없는 경우로서 게이트 절연막 가장자리에 게이트 버즈빅이 형성된 것을 알 수 있다. 반면에 도 3b를 참조하면, 산화방지 스페이서가 있는 경우로서 게이트 가장자리에 게이트 버즈빅이 최소화 되었음을 알 수 있다.Referring to FIG. 3A, it can be seen that a gate buzz big is formed at the edge of the gate insulating layer when there is no antioxidant spacer. On the other hand, referring to Figure 3b, it can be seen that the gate buzz big is minimized at the edge of the gate when there is an antioxidant spacer.
표 1은 산화방지 스페이서가 있는 경우 및 없는 경우의 문턱전압과 구동전류의 시뮬레이션 비교값이다.Table 1 shows simulation comparisons between threshold voltages and driving currents with and without an antioxidant spacer.
상기 표 1에서의 구동전류의 측정 조건으로는 게이트 단자(VG) 및 드레인 단자(VD)에 각각 2V를 인가하였다. 그리고 게이트 전극의 채널 길이는 0.2μm로 설정하였다.As the measurement conditions of the driving current in Table 1, 2V was applied to the gate terminal V G and the drain terminal V D , respectively. The channel length of the gate electrode was set to 0.2 µm.
표 1에서 나타난 바와 같이 산화방지 스페이서가 있는 경우에는 문턱 전압을 감소시킴과 동시에 구동전류는 증가하는 것을 확인할 수 있다.As shown in Table 1, in the presence of the anti-oxidation spacer, it can be seen that the driving current increases while reducing the threshold voltage.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기와 같이 이루어진 본 발명은, 게이트 전극을 형성하고 확산방지 스페이서를 게이트 전극 측벽에 형성함으로써, 이 후 열산화막을 형성할시 발생하는 과도한 측면 확산에 의한 게이트 버즈빅을 최소화하여 문턱전압을 감소시킴과 동시에 구동전류를 증가시키는 효과가 있다.According to the present invention, the gate electrode is formed and the diffusion barrier spacer is formed on the sidewall of the gate electrode, thereby minimizing the gate buzz big due to excessive side diffusion occurring when the thermal oxide film is formed. At the same time, there is an effect of increasing the driving current.
Claims (10)
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