KR20020093919A - Deposited thin films and their use in separation and sacrificial layer applications - Google Patents

Abstract

The present invention utilizes large surface area to volume ratio materials for separation, release layers, and sacrificial material applications. The present invention outlines material concepts, application design and manufacturing methods. The present invention is demonstrated using a column / void network material deposited as an example of a large surface area to volume ratio material. In many of the specific applications described, it is described that after creating a structure on a laminate on a mother substrate, it is desirable to separate this laminate from the mother substrate using this separation scheme using a separation layer material approach. It is also shown that the materials have excellent release layer utility. In many applications, how an approach can be used to uniquely form cavities, channels, air gaps and related structures in or on various substrates is described. It has also been demonstrated that it is possible and desirable to combine a scheme for laminate separation and a scheme for cavity formation.

Description

Deposited Thin Films, and Their Separation and Sacrificial Layer Applications TECHNICAL FIELD

The separation layer approach is used to physically separate the separated material system into at least two other systems. The approach is based on using some separation material disposed between other materials, whereby the separation material is etched, mechanically worn or dissolved, leaving at least two, physically separated, different groups of materials. Although used, in a release layer application, the two material systems are not completely separated. The separating or releasing layer material is typically a polymer (eg photoresist), silicon dioxide, or polycrystalline silicon (Kim Sang-kuk and Hwang Kyu-ho, Information Display, 15, 30, (1999)). Recently, electrochemically etched porous silicon has been used as a separation layer for creating insulator silicon (SOI) wafers for microelectronics applications (T. Yonehara and K. Sakaguchi, Abstract # 438, The Electrochemical Society, Fall Meeting, Oct. 2000, Phoenix, Az.).

Sacrificial layer applications are used to create micro- and nano-unit voids or cavity regions. Such voids and cavities are filled continuously, as are closed voids. Void formation is accomplished by removing the sacrificial material, leaving a blank area surrounded by an envelope of one or more materials. The size and shape of the voids or cavities can be designed for specific applications. The form can vary and supports various functions such as channels, tubes, "air gaps" or cavities. Commonly used sacrificial layer materials include polymers, silicon dioxide, and polycrystalline silicon (MB Stern, MWGeis and JECurtin, J. Vac. Sci. Technology. Vol. B15 (6), pp. 2887 (1997). And SWTurner and HG Craighead, Proc. SPIE Vol. 3258, pp. 114 (1998).

Deposited or thermally grown silicon dioxide and deposited polysilicon are probably the most used sacrificial materials (PJFrench, J. Micromech. Microeng. Vol. 6, pp 197 (1996) and S. Sugiyama, O. Tabata, K.). Shimaoka and R. Ashahi, IEDM Tech.Dig.pp. 127 (1994)), their etch rates can be relatively very high when deposited in open areas. When used as a sacrificial layer in the creation of void structures such as channels, tubes, cavities or "air gaps", these materials are of course covered with a cap layer that forms the "roof" of what is to be a void region. The void or cavity area is then formed by etching the sacrificial layer material through a window or through hole inside or beside the cap layer. These windows provide etchant access and reaction product outlets. As a result, the etch rate depends on both transport processes rather than the etchant solution, reaction product or one chemical reaction rate, so the etch rate can be very slow. That is, not only the chemical etching rate but also the removal of the reaction product from the sacrificial layer material and the removal of the sacrificial layer depend on the access of the etchant. As a result, materials with high etch rates when deposited in open areas often have significantly slower etch rates when used as a sacrificial layer.

Conventional porous silicon produced by electrochemical etching of silicon has been tried for sacrificial layer applications (TE Bell, PTJ Gennissen, D. DeMunter and M Kuhl, J. Micromech. Microeng. Vol. 6, pp. 361 (1996) And P. Steiner, A. Ritcher and W. Lang, J. Micromech.Microeng. Vol. 3, pp. 32 (1993)). However, lack of uniformity and controllability, the need for an electrically conductive path for the electrochemical etching necessary to create the material, the fact that it must be formed on the conductor, and residual impurities remaining in the material after the electrochemical etching For this reason the use of this material is limited.

Generally, there are several ways to create void structures as well as using sacrificial layers. All approaches, including the use of a sacrificial layer, fall into two basic ways. A first, agglomerate micromachining, substrate-to-substrate or wafer-to-wafer bonding technique creates objects on a surface using standard processes such as etching, milling, stamping, stamping, etc., and then bonds the substrate and the capping wafer or substrate. Thereby creating nano- or micro channel objects. In principle, this bonding approach is a relatively simple process. However, this has the crucial disadvantage of requiring anode or direct (integrated) bonding and requiring top and bottom alignment. This makes it difficult to fabricate small dimension channels due to misalignment between the two substrates and microvoid formation at the bonding interface during the bonding process. The second technique, surface micromachining, is a method based on the use of a sacrificial layer. Since this is based on the use of a sacrificial layer, it is possible to produce channel sizes of several nanometers or less, even though the sacrificial layer removal process is a relatively complex process so far (MJ de Boer, W. Tjerkstra et al., J. of Microelectrochemical). systems, Vol. 9, No. 1, pp. 94, March 2000). Among these techniques, surface micromachining is considered the most reliable way to produce fine structures, and is the most reliable method for applications requiring strict structural dimensions such as optical resonant cavities.

The present invention utilizes a separation and release layer material and is based on a sacrificial material approach in device fabrication. In particular, the present invention is based on the use of new materials for separation, release and sacrificial applications, and the use of new and simple processing flows for implementing separation, release and sacrificial layers. The new materials of the present invention are large film surface to material volume ratio thin films deposited. The large surface area to volume ratio ensures a large void area between the material (ie, material volume) areas that allows for easy access by the etch chemistry and easy removal of the reaction product. This ensures a very uniform, substantially wetted material that leads to a very uniform attack and removal. In addition, large surface areas ensure efficient chemical attack of the material when exposed to the removing chemical. Large surface area versus volume structures also lead to mechanically weak materials where mechanical agitation can assist in removal or gases trapped in the material can be used to enhance removal. With the materials of the present invention, the procedures for separation layer applications and removal procedures for sacrificial layer applications are more reliable than other release and removal layer applications, and are faster than other release and sacrificial layer applications, allowing for close process control. Let's do it. In addition, these new materials can be deposited and thus used with several substrates including, but not limited to, plastic, glass and metal foils.

The present invention relates to deposited thin films of semiconductors and dielectrics. The invention also relates to using these thin films for separation, release and sacrificial layer applications. Separation and release layer applications for these thin films are materials and structures in manufacturing processing in areas such as microelectronics, displays, solar cells, sensors, detectors, optoelectronics, biotechnology, and microelectronic mechanical (MEM) devices and systems It includes a function for separating. Sacrificial layer applications of these thin films include void areas for use in channels, tubes, "air gaps" and microfluidics, separation / sorting structures, fuel cells, dielectrics, acoustic structures, and optical structures. Sacrificial film function for generation.

1A-1D illustrate an approach using separation layer and through hole access. Structures, circuits, devices, etc. (shown here as TFTs) are subsequently separated after being fabricated on a mother substrate. The plastic material deposited or formed prior to the device manufacturing process flow is used to provide the necessary mechanical integrity after separation. 1A illustrates a rigid substrate having a columner void layer or sacrificial layer, a polymer coating and a device, and a sensor or actuator deposited thereon. 1B shows through holes etched into the system. 1C shows the separation of the device from the substrate by removing the columner void layer or sacrificial layer. 1D shows a separate device deposited on a rough or flexible substrate.

2A-2D illustrate another approach using separation layer and through hole access. Structures, circuits, devices and the like (shown here as TFTs) are fabricated on the mother substrate and subsequently separated. In FIG. 2, the plastic material deposited or formed after the device manufacturing process flow is used to provide mechanical integrity after separation. 2A illustrates a rigid structure with a columner void layer or sacrificial layer, a polymer coating and a sensor or actuator deposited thereon. 2B shows through holes etched into the system. 2C illustrates separating the device from the substrate by removing the columner void layer or sacrificial layer. FIG. 2D illustrates a separate device that has been converted and deposited onto a rough or flexible substrate.

3 shows a CAPS structure composed of several plastic laminates including power devices such as circuits and fuel cells. In this example, the final laminate includes the pixels that make the system a display. Each of the laminates assembled to make this system are each manufactured and separated after the method shown schematically in FIG. 1 or FIG. 2.

4A-4F illustrate the use of a columner void network deposited silicon film to form an empty cross section using a deposition / etch approach. 4A illustrates columner void layer or sacrificial layer deposition on a substrate. 4B shows lithography and etching of a columner void layer or sacrificial layer. 4C shows a wall / capping layer deposited on an etched columner void layer or sacrificial layer. 4D illustrates a wet etchant access window etch that creates through holes as needed on the top or side for efficient etching. 4E illustrates etching of the columner void layer or sacrificial layer. 4F illustrates the deposition of a window filling or other coating on the void structure.

5A-5H illustrate the use of a columner void network deposited silicon film to form an empty cross section using a deposition / etching / lift-off approach. 5A illustrates base layer deposition. 5B shows lithography and etching of the base layer and stencil layer. 5C illustrates deposition of a columner void layer or sacrificial layer. 5D illustrates a lift-off process to remove the stencil layer as part of the sacrificial layer. 5E illustrates capping layer deposition. 5F illustrates wet etchant access window etching to form through holes as needed. 5G illustrates etching of the columner void layer or sacrificial layer. 5H illustrates window filling of a void structure.

6A-6H illustrate the use of a columner void network deposited silicon film to form a closed hollow structure, such as channels, tubes, cavities, etc. of relatively large cross sections that can be produced in a single wet chemical etch without the need for a so-called deep etch reactive ion etch process. It is shown. FIG. 6A illustrates base layer deposition onto a substrate including a substrate, an optimal etch stop or barrier layer, and a base layer (eg, silicon nitride) to be deposited (eg, a-Si and poly Si). 6B shows lithography and base layer etching. 6C shows columner void layer or sacrificial layer deposition. 6D illustrates lift off of the stencil layer as part of the columner void layer or sacrificial layer. 6E illustrates a capping layer application. 6F illustrates etchant access window etching. 6G shows the sacrificial layer etch and trench creation. 6H illustrates window charging.

FIG. 7 is a cross-sectional SEM micrograph of a void or cavity structure made after the deposition / etch approach shown schematically in FIG. 4.

FIG. 8 is a cross-sectional SEM micrograph of a void or cavity structure prepared after the deposition / etching / lift-off approach schematically shown in FIG. 5.

9A shows a fuel cell fabricated using a silicon wafer.

FIG. 9B shows a fuel cell fabricated using deposited silicon on a lightweight substrate, such as a polymer, glass or metal foil.

FIG. 10 shows a detailed fuel cell processing sequence for FIGS. 9A and 9B.

11A-11C are illustrations of an actual sorting structure formed using a columner void layer as a sacrificial material. Such a structure may be a laminate formed by a separation procedure. 11B shows the boundary between the deep and shallow channels. FIG. 11C shows the magnified image of FIG. 11B.

12 shows molecular immobilization for detection. Detection is accomplished by monitoring alternating or direct current electrical responses between molecules that immobilize molecular identity.

13A-H illustrate the formation of a release layer for the application of the material. 13A illustrates Cr / Au deposition. 13B shows lithography and etching. 13C illustrates columner void network material deposition. 13D illustrates contact tip etching. Figure 13E illustrates beam support etching. Figure 13F illustrates lithography of a columner void network material. 13G illustrates Au deposition. 13H illustrates a columner void network material etch.

The present invention comprises the steps of (a) providing a substrate; (b) forming a high surface area to volume ratio material layer on the surface of the substrate; And (c) removing at least a portion of the high surface area to volume ratio material layer during subsequent processing of the substrate. In an embodiment of the invention, a high surface area to volume ratio material layer is deposited on the substrate in step (b). In another embodiment of the invention, the high surface area to volume ratio material layer is a columnar void layer, deposited metal, dielectric, semiconductor or organic material. The columner void layer comprises a plurality of uniform substantially non-contacting columnar units penetrating successive voids, the units having regular spacing, adjustable uniform height and adjustable variable diameter, The basic columnar units of are arranged uniformly oriented on the substrate. The basic columnar unit contains silicon, germanium, carbon, hydrogen, other inorganics, or mixtures thereof. The columner void layer has a thickness of about 10 nm and is deposited in a vacuum environment at a pressure lower than atmospheric pressure at a temperature of about 250 ° C. or less.

In an embodiment of the invention, a high surface area to volume ratio material layer is formed on at least one intervening layer disposed between the high surface area to volume ratio material layer and the substrate.

In another embodiment of the invention, the removal of the high surface area to volume ratio material layer of step (c) is carried out by chemical means, physical means or a combination thereof. Removal of the high surface area to volume ratio material layer of step (c) is performed by chemical means through dry etching, wet etching and combinations thereof. A portion of the substrate may be removed before, during or after removing at least a portion of the high surface area to volume ratio material layer of step (c). In a further embodiment of the present invention, the intervening layer between the high surface area to volume ratio material layer and the substrate is removed.

In a further embodiment of the invention, further comprising depositing at least one coating on the high surface area to volume ratio material layer after forming a high surface area to volume ratio material layer on the surface of the substrate in step (b).

In one embodiment of the present invention, the described method further comprises fabricating the device, structure or both on at least one coating forming the device, the coating structure, the coating and mixtures thereof. Removing at least a portion of the high surface area to volume ratio material layer in step (c) detaches the device, coating structure, coating or mixture thereof from the substrate. In one preferred embodiment of the present invention, the method further comprises creating a through hole through the device, coating structure, coating or mixture thereof to remove the high surface area to volume ratio material layer. The through hole can be produced through the substrate, the coating or coatings or both. The method further includes forming a second coating on the device, the coating structure, the coating, and a mixture thereof. The first coating, the second coating, or both act as substrates, followed by a combination comprising the device and the structure after removal of the high surface area to volume ratio material layer of step (c). In another embodiment of the present invention, after removal of the high surface area to volume ratio material layer of step (c) through the resulting through hole, the device, coating structure, coating, and mixture thereof are separated from the substrate, and then the second substrate And using the carrier substrate to place the device, coating structure, coating or mixture thereof separated on the phase.

In another embodiment of the present invention, removing a portion of the high surface area to volume ratio material layer in step (c) of the described method includes selectively etching the high surface area to volume ratio material layer so that the portion remains. The method further includes forming at least one layer on the remaining portion of the high surface area to volume ratio material layer. Another additional step includes creating a through hole that accesses a high surface area to volume ratio material layer. The process of removing residues of the high surface area to volume ratio material layer then uses the through holes to create the cavity structure. Deposition of at least one further layer on the at least one layer is followed by blocking the through-holes.

In a further embodiment of the invention, providing a substrate in step (a) of the described method comprises depositing a stencil layer on the substrate, patterning the stencil layer, and selectively removing a portion of the stencil layer. Thereby leaving the exposed portions of the substrate and at least one residue of the stencil layer. The exposed portion of the substrate is subsequently etched using the stencil layer as a mask.

Forming a high surface area to volume ratio material layer includes forming a high surface area to volume ratio material layer on the exposed surface of the substrate and at least one residue of the stencil layer, further comprising lifting off the stencil layer. This removes a portion of the high surface area to volume ratio material layer deposited thereon. An additional step includes depositing a second layer on the substrate and the high surface area to volume ratio material layer. Through-holes are created through the second layer.

Depositing a layer blocking the through-holes, if necessary, after removal of the high surface area-to-volume ratio material layer through the through-holes created to create the cavity structure. After removal of the columner void layer of step (c) through the through hole created to create the cavity structure, adding gas or liquid to the cavity structure and depositing a layer blocking the through hole and sealing the cavity structure. It further comprises a step.

In one embodiment of the present invention, providing the substrate includes removing a portion of the deposited material system from which the material system is deposited on the substrate and leaving a portion of the material system. In a preferred embodiment of the present invention, forming a high surface area to volume ratio material layer on the substrate comprises forming a high surface area to volume ratio material layer and a residual material on the substrate, to expose a portion of the residual material. Removing a portion of the high surface area to volume ratio material layer. The method further includes depositing additional material on the high surface area to volume ratio material layer and the exposed portion of the previously deposited material, such that a portion of the additional material is in contact with the exposed portion of the previously deposited material.

The present invention also provides a method for forming a high surface area to volume ratio material layer on a substrate; b) forming at least one coating on the high surface area to volume ratio material layer; c) manufacturing the device, structure or both on at least one coating to form a device / coating structure / coating or mixture thereof; d) removing the high surface area to volume ratio material layer, thereby separating the system from the substrate. In one embodiment of the invention, the high surface area to volume ratio material layer is a columner void layer. In another embodiment of the invention, a columner void layer is deposited. The columner void layer comprises (a) a plurality of uniform substantially non-contacting columnar units penetrating successive voids, the unit having adjustable regular spacing, adjustable uniform height, and adjustable variable diameter. -; And (b) a plurality of basic columnar units that are constantly oriented and disposed on the substrate.

In a preferred embodiment of the invention, the first substrate is rigid. In a more preferred embodiment of the invention, the first substrate is selected from the group comprising silicon wafers, quartz, glass, organic materials, polymers, ceramics, semiconductors, metals, insulating materials, and mixtures thereof.

In an embodiment of the invention, the step of forming at least one coating on the high surface area to volume ratio material layer of step (b) comprises depositing, applying, spin-coating, screening, printing, sputtering, dewatering, and diffusing. It is performed by a technique selected from the group containing. At least one coating is organic or inorganic and preferably is a material selected from the group comprising chemically active materials, polymers, insulators, nitrides, oxides, piezoelectrics, ferromagnetics, metals, pyroelectrics, biological materials and semiconductors. The device is one structure selected from the group comprising sensors, actuators, electronics, chemical micro-fluidics, detectors, fixed structures, circuits, displays, acoustic devices, solar cells, optoelectronic devices, fuel cells and combinations thereof.

In one embodiment of the present invention, the described method further includes creating a through hole used to remove the high surface area to volume ratio material layer. The through-holes are created through at least one layer selected from the group comprising a substrate, a high surface area to volume material layer, an intervening layer between the substrate and a high surface area to volume material layer, a layer or layers on the high surface area to volume material, and combinations thereof. The generation of through holes is performed using one technique selected from the group comprising dissolution, dry etching, wet etching, reactive ion etching, deep silicon etching, and magnetically enhanced reactive ion etching. In another embodiment of the present invention, the step of removing the high surface area to volume ratio material layer of step (d) is performed by chemical means, mechanical means or a combination thereof. In a further embodiment of the invention, the method further comprises depositing a separate device, coating or mixture thereof on the second substrate. In another embodiment of the present invention, the method further comprises depositing at least one coating on the device, coating structure, coating or mixture thereof, wherein the at least one coating is separated from the substrate of step (d), A carrier substrate used to be disposed on the second substrate. In a preferred embodiment of the invention, the second substrate is flexible and is an organic, glass or metal foil material. Use of the system for the second substrate includes, but is not limited to, thin film transistors, electronics, sensors, actuators, detectors, microelectromechanical devices, displays, fuel cells, optical electronics, or solar cells.

The present invention also includes the steps of: a) forming a high surface area to volume ratio material layer on a substrate; b) forming at least one layer on the high surface area to volume ratio material layer; And c) removing a portion of the high surface area to volume ratio material layer to create a cavity structure. In one embodiment of the invention, the high surface area to volume ratio material layer deposited on the substrate in step (a) is patterned using a soft masking material, a hard masking material, or a combination thereof.

In another embodiment of the present invention, removing a portion of the high surface area to volume ratio material layer of step (c) is performed by chemical means, mechanical means, or a combination thereof. In a further embodiment of the invention, the removal of a portion of the high surface area to volume ratio material layer of step (c) also removes a portion of the substrate. At least one layer on the high surface area to volume ratio material layer is one material selected from the group comprising chemically active materials, polymers, insulators, nitrides, oxides, piezoelectrics, ferromagnetics, metals, pyroelectrics, biological materials, and semiconductors . In an embodiment of the present invention, gas or liquid is added to the cavity structure after the high surface area to volume ratio material layer is removed in step (c). In an embodiment of the present invention, the method further comprises creating a through hole through at least one layer, substrate, or both to access a high surface area to volume ratio material layer. In addition, the method further includes forming an additional layer on the substrate after removing the high surface area to volume ratio material layer of step (c), thereby blocking the through hole.

In an embodiment of the invention, the height of the cavity structure is at least 10 nm and the width of the cavity structure is at least about 10 nm.

The creation of the cavity structure is MEMS; Field emission sources; Bolometer structure; Accelerometer; Optical trapping; Resonance; Electric field shaping; send; Acoustic trapping; Display micro-mirror formation; Biomedical and medical devices; Sorting structures and proteomic sorting for functions such as DNA; Cell nutrients, growth control or both; Capillary function; Gettering regions for silicon on solid phase crystallization or insulating structures; Interlayer stress control; Optical waveguide and optical device applications; Fluidic channels, chromatography, chemical reagents / product transport for electrical, chemical and electrochemical sensors; Fuel cells; display; And the use of a molecule selected from the group comprising molecular sorting.

The present invention comprises the steps of: a) forming at least one stencil layer on a substrate; b) removing a portion of the stencil layer to create an exposed portion of the substrate; c) forming a high surface area to volume ratio material layer on the stencil layer and a portion of the exposed substrate; d) lifting off a portion of the stencil layer to remove a portion of the high surface area to volume ratio material layer formed thereon and leaving a portion of the high surface area to volume ratio material layer formed on the exposed portion; e) forming at least one layer on the substrate and the high surface area to volume ratio material layer; And f) removing the high surface area to volume ratio material layer to form the cavity structure. The stencil layer comprises one material selected from the group comprising photoresist, nitride, oxide, metal, polymer, dielectric, and mixtures thereof. The substrate is selected from the group comprising silicon wafers, quartz, glass, organic materials, polymers, ceramics, semiconductors, metals, and mixtures thereof. In an embodiment of the present invention, the stencil layer of step (b) is performed using one technique selected from the group comprising dissolution, dry etching, wet etching and combinations thereof. In a preferred embodiment of the present invention, step (d) of lifting off the stencil layer is performed by dissolution, etching, mechanical means or a combination thereof. In another embodiment of the present invention, the method further comprises creating a through hole to access the high surface area to volume ratio material layer. In a further embodiment of the invention, the method further comprises adding gas or liquid to the cavity structure after the high surface area to volume ratio material layer is removed in step (f). In one embodiment of the present invention, the method further comprises depositing an additional layer, the additional layer blocking the through hole. This additional layer is one material selected from the group comprising dielectrics, polymers, metals, photoresists, nitrides, oxides, and mixtures thereof.

The present invention comprises the steps of: a) forming a first material system on a substrate; b) etching a portion of the first material system; c) forming a high surface area to volume ratio material layer on the first material system and the substrate; d) removing a portion of the high surface area to volume ratio material layer to expose a portion of the first material system; e) forming a second material system on the high surface area to volume ratio material layer and the exposed portion of the first material system such that the second material system is in contact with a portion of the first material system; And f) freeing a portion between the first and second material systems while maintaining the at least one contact area by removing the high surface area to volume ratio material layer. A method of creating a region on a substrate. In one embodiment of the present invention, the first and second material systems include metals, semiconductors, chemically active materials, polymers, insulators, nitrides, oxides, piezoelectrics, ferromagnetics, pyroelectrics, biological materials, semiconductors, and combinations thereof. It is selected from the group to say. The substrate is one material selected from the group comprising silicon wafers, quartz, glass, organic materials, polymers, ceramics, semiconductors, metals and mixtures thereof. In another embodiment of the present invention, the removal of the high surface area to volume ratio material layer by chemical means has an etch rate of 25 μm or less per minute. The creation of at least one contact region between the first and second material systems provides for the fabrication of a structure selected from the group comprising MEMS devices, cantilever structures, micro-switch structures, micro-mirror structures and actuators.

The present invention relates to a method of manufacturing an assembly comprising the step of forming a channel in or on a substrate comprising a reactant, an article, or both, wherein the channel and catalyst structure is formed by the described method. In particular, a method of manufacturing a fuel cell includes a) depositing a masking layer on a substrate; b) using the stencil layer to define the position of the channel region in the masking layer; c) covering the defined area in the masking layer and the stencil layer in the area adjacent to the sacrificial layer material; d) lifting off the sacrificial layer material in the stencil coating area by dissolving or etching the stencil layer; e) depositing an anode material on the entire resulting surface for the layer formed in step (d); f) patterning the anode material to form an anode; g) depositing an electrolyte on the resulting surface for the layer formed in step (d); h) employing means for accessing the sacrificial layer; i) using means to etch or dissolve the sacrificial layer in the region to be the channel; j) using these regions of the sacrificial material removed as defining regions for subsequent or successive etching or dissolution of the underlying material to create a channel comprising fuel, oxidant or both; k) depositing and patterning the cathode material on the resulting surface for the layer formed in step (d); And l) depositing and patterning interconnects and contacts on the resulting surface for the layer formed in step (d) to provide electrical current flow and power generation for the fuel cell.

The present invention is directed to the use of "deposited" large surface area to volume ratio materials for separation, release layers and sacrificial material applications. In these applications, the separating, releasing and sacrificial materials are removed by chemical attack, mechanical perturbation and destruction, gas pressure or chemical effects, or some combination thereof. In the case of a separation layer application, the removal of material creates at least two physically separate material systems. In the case of release layer applications, the removal of material creates a material system that is attached to at least one location. In a sacrificial layer application, the removal of material creates a void or cavity (may or may not be continuously filled) within the material system. The present invention has been demonstrated using deposited columner void network thin films having controllable void volumes as separation and sacrificial materials. These materials have a structure that is adaptable from a variable and continuous film (no void) to a film comprising (a) a network of columnar units in a continuous void and (b) a substrate to which a network of columnar units are attached. have. These columner void films can be conductors, semiconductors, or metals. These may be based on chemical elements such as silicon, germanium, carbon, hydrogen or mixtures thereof. The films can be converted to other materials such as oxides, nitrides and intermetallic compounds by chemical reactions. The fingerboard supporting these films may be made of various materials including, but not limited to, glass, metal, insulating material, polymer material, semiconductor, and semiconductor containing material.

As pointed out, the concept of large surface area to volume ratio separation / sacrificial membranes in the present invention has been demonstrated using nanostructured column / void materials with networks of units collected in clusters and formed by deposition of plasma systems. The spacing and height of the network of columnar units can be determined by oxidation, silicidation, etching, voltage, current, sputtering voltage, voltage between plasma and substrate, substrate temperature, plasma power, process pressure, electromagnetic field around substrate, deposition gas and flow rate, Adjustable by a parameter selected from the group comprising chamber conditioning, and substrate surface.

Another approach that utilizes high performance structures that can be created on plastic laminates with the separation approach of the present invention is to cut each device-containing island of plastic or other material laminate into a separate die. They can then be assembled into the system as needed using self-assembly techniques such as those based on electrostatics, chemistry, or atomic placement compatibility.

In the present invention, an approach to produce materials having a large void volume, and therefore a large surface area to volume ratio, uses deposition to grow an as-deposited porous membrane. In the present invention, the void areas (small holes) are fairly constant over the thickness and transverse direction of the film. The deposition process is unique because it is carried out at low temperatures, and the inventors can use the present invention to control the void size and void fragments, and the void-column network shape does not vary over the thickness of interest, and the columns are double crystal or It has been demonstrated that it can be an amorphous material. Plasma approaches, including DC and RF discharge, sputtering, and high density plasma tools, can be used to control the interaction between deposition and etching during growth. Proven processes using high density plasma deposition etch interactions can provide high porosity (up to approximately 90%) of controlled small pore size materials without any back contact and anodization-based wet treatment. Unlike other deposition processes, the process is based on high density plasma deposition-etching interactions, and therefore has a high level of controllable porosity (up to 90%), a shape that does not vary with thickness, and doped or undoped A double crystal column can be provided. It is also unique to the present invention that it has the ability to produce high surface area to volume ratio materials on many types of substrates including glass, metal foils, insulators, plastics, and semiconductor containing materials.

The high density plasma (HDP) deposition tool used for this demonstration was an electron cyclotron resonant plasma machine. In particular, high surface area-to-volume ratio columner void network silicon is a high density plasma tool (e.g., electron cyclotron resonant plasma enhanced chemical vapor deposition) utilizing hydrogen dilution silane (H ₂ : SiH ₄ ) at substrate deposition temperatures less than or equal to about 250 ° C. (ECR-PECVD) tool (Plasma Therm SLR-770). These tools play off silicon etching and deposition to create a two-dimensional silicon array, and the analysis results show that the silicon column size is controllable, the spacing between the columns is controllable, and the shape does not vary greatly with thickness. . Unlike other deposited column silicon materials, the column spacing can be maintained as the film thickness grows, and the column phase synthesis can be controllably varied from double crystal to amorphous. The resulting columner void network structure is fully developed after the object size is nanoscale and film thickness in the 10-20 nm range is established. This allows for direct deposition of amorphous or silicon of high surface area to volume ratio on any substrate, with any thickness greater than about 10 nm, preferably between 10-20 nm. The high void volume semiconductor film produced by the present invention may be converted to an insulator or metal composite through in-situ or ex-situ treatment.

The present invention provides a deposited high surface area to volume ratio membrane comprising a plurality of perturbations that extend into voids having up to about 90% porosity. The plurality of perturbations is disposed almost perpendicularly to the substrate or alternatively to the base layer. The plurality of perturbations are rod-shaped columns and are double crystal or amorphous like silicon material. Porosity is the result of continuous voids. The perturbations have a height that is adjustable by film thickness and has a diameter of about 1 nm to about 100 nm. More specifically, the column has a diameter of about 3 nm to about 7 nm. In addition, perturbations are found in clusters having a diameter between about 50 and 500 nm or more.

The special features of the deposited columner void network-type high surface area to volume thin films are controlled by a number of factors. These include (a) the voltage between the plasma and the substrate, (b) substrate temperature, (c) plasma power and process pressure, (d) magnetic fields around the substrate, (e) deposition gases and flow rates, (f) chamber conditioning, (g ) Sputtering voltage, and / or (h) the substrate surface. The influence of many of these factors is not expected.

The invention also provides a material and structure for separating the material system into physically separate systems, releasing the material into partially separated systems, and creating a closed cavity in the materials. Many applications are provided that result from using these materials and structures. The present invention utilizes a large surface area to volume ratio material deposited as the separating, sacrificial or releasing material. In particular, it is shown that large surface area to volume ratio materials deposited efficiently are provided by deposited columner void network membranes.

The present invention is demonstrated with an embodiment of deposited large surface area to volume material, deposited columnner void network silicon. Such materials have large, adjustable surface area to volume ratios (ie, large surface areas). This large surface area to volume ratio means that the material has a large surface area and is therefore very weak to chemical attack and easily weakened mechanically. Large surface area to volume ratio also means that chemical species can move relatively freely through the void region penetrated by the column. This "wets" the material quickly and uniformly due to the capillary action that leads to a uniform removal procedure based on chemical attack or dissolution. In addition, the large void volume (ie, high porosity) of these materials allows the storage of gases that can be used in the removal process if gas pressure or gas interaction is used to separate the material system in release layer applications.

There are several approaches to producing large surface area versus volume (ie large surface area) materials. The most interesting technique today is based on the electrochemical etching mentioned previously. When electrochemical etching is used to produce large surface area silicon, the resulting material is commonly referred to as porous silicon. Porous Si was first electrochemically obtained in 1956 by Uhlirdp of Bell Labs, but until 1970 the porosity of electrochemically etched Si was not realized (Y. Watanabe and T. Sakai, Rev. Electron.Column.Labs 19, 899 (1971). A recent discussion is given by R.C. Anderson, R. C. Muller and C.W. Tobias, Journal of Microelectro-mechanical Systems, vol. 3, 10 (1994).

The starting material for this wet etched conventional porous Si material is either a conventional silicon wafer or thin film Si produced by some deposition processes such as low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). In either case, the electrochemical wet etch process involves the exposure of the silicon sample to the wet solution, the current being in contact with the etch sample, the etch sample, the solution (eg, a mixture of hydrofluoric acid, water and ethanol), and the solution. Passed through an electrode (cathode, for example platinum) in contact. This current causes “pitting” or etching of the Si sample to create the porous network network structure.

In an electrochemical (anode) etch process, the structure (e.g., small pore size and spacing) and the porosity-Si layer thickness depend on the resistance (size and type) of silicon itself, current density, applied potential, electrolyte compound, application of light. , Controllable by temperature and exposure time. For sufficiently long exposures and sufficiently thick starting materials, this electrochemical etching process can continue up to the point where nanoscale structures (ie, nanometer-based objects) are obtained. The silicon object is a continuous single crystal, as is usual when the sample is etched from a single crystal wafer, and is polycrystalline silicon when the sample is etched from the deposited film. All these conventional (electrochemically etched) porous silicon materials are (1) the result of a wet, electrochemical etch process, and (2) during this wet etch require electrical contact on the sample and current flow through the sample. (3) having generally separated small hole areas that can be connected after extensive etching, and (4) being the result of sequential processing that first requires the formation of silicon and then subsequent wet etching. . In addition to the complexity of having electrical contacts and preparing, using, and disposing of wet chemical etch baths, these wet etched porous materials present problems with the type of residual etching and product remaining in the small holes. In isolation and sacrificial layer applications of porous silicon, electrical contact to silicon in the region to be the release or sacrificial layer must first be established and then electrochemically etched.

An approach to producing high surface area to volume ratio materials of the present invention is to use deposition to grow the high surface area film to be grown. The ratio in the high surface area to volume ratio material is based on taking into account the transient area above or above what is present when the film is continuous and has no voids. A good ratio of high surface area to volume ratio material is up to 10,000 to one. High surface deposition is an deposited film that can be placed anywhere needed for release or sacrificial layer applications. They can be deposited on flat or curved surfaces and on a substrate of any compound. They can be deposited in a full spectrum of tunable surface area to volume ratios. This tunability proved to allow up to about 90% porosity in the continuous (surface area, ie void) membranes. Due to this porosity control feature, wettability, mechanical stringency, gas content, and etch rate can be adjusted as needed. This approach utilizes deposition performed at low temperatures and is adjusted to achieve the desired shape. There is no wet treatment and associated special etching process used to prepare the material to be the release or sacrificial layer. It is also unique to the present invention that these deposited films can be fabricated on many types of substrates of semiconductor containing materials, including substrates having glass, metal foils, insulators, plastics, and circuit structures, while the designed structures match the application. It is the ability to

The concept of deposited large surface area to volume ratio thin films for isolation and sacrificial layer applications is demonstrated using columner void network silicon materials prepared by plasma enhanced chemical vapor deposition (PECVD). In particular, this approach is demonstrated by preparing columner void network material using a high density plasma tool (eg, an electron cyclotron resonant plasma enhancement chemical tool (plasma term SLR-770)). The deposition of the material used hydrogen diluted silane (H ₂ : SiH ₄ ) as the preparation gas at substrate deposition temperatures less than or equal to about 250 ° C. The high density plasma tool approach plays off silicon etching and deposition to create a two dimensional silicon array, and the analysis has demonstrated that the silicon column size is controllable and the spacing between columns is controllable. The resulting column / void network structure is fully developed after the object size is nanoscale and film thickness in the range of 10-20 nm is established. The column diameter is between 30 nm and about 100 nm. This allows for direct deposition of large surface area versus volume material (ie, high porous material) of crystalline or amorphous phase onto any substrate at any thickness greater than about 10 nm. The column / void semiconductor film produced by the present invention can be converted to an insulator or metal compound through in situ or non-in situ processing. In addition, the functionalization of the layers may be formed or deposited after or prior to the deposition of the column / void network material. By varying the deposition parameters in the high density plasma tool, continuous (voidless) medium or high void density materials may be produced.

Unlike conventional porous silicon, the columner void network silicon used in the present invention is deposited rather than formed by wet electrochemical etching, allowing it to be formed anywhere on any substrate. The deposited film has a unique column structure and includes voids (ie, empty spaces) originally formed between the columns. That is, the structure has the unusual feature of a stick (column) that is close to or substantially perpendicular to the thin transition layer on the surface on which the film is deposited. Membrane voids are continuous, which facilitates rapid removal of material in sacrificial, separation or release layer applications by allowing for high-speed transfer of reactants and reaction products through the bed and high-speed transfer through wet-etch solutions, access windows or through-holes. do. Rapid removal of the sacrificial, separation or heze layer increases the reliability of the manufacturing process since it reduces the likelihood that other structural layers will be damaged during wet etching. In addition, the deposited columnner void silicon can be placed on any type of substrate, such as plastic, glass, silicon wafers and metal foils. This is another unique advantage of deposited columnner void network silicon over conventional electrochemically wet etched porous silicon, and requires a silicon substrate or film with at least one underlying electrical contact for electrochemical formation.

1. Separation layer

Much attention has been given to fabricating electrons, fluids, solar cells, sensors and detectors, and chemicals on flexible substrates that are not conventional. These substrates are relatively inexpensive, lightweight, and flexible (eg, plastic, glass, or metal foil), but they often have rough, uneven surfaces. Furthermore, fabricating devices directly on such substrates is difficult due to the difficulty of lithography and the dimensional rigor of such substrates. Electronic, chemical, display, micro-fluidic, and optoelectronic devices that benefit from being provided on these substrates include diodes, transistors, sensors, actuators, heat transfer systems, micro-electro-mechanical devices (MEMS), fuel cells , Solar cells, and combinations thereof. The manufacture of such devices and structures on non-traditional substrates provides a number of new applications, as systems can be created that are collapsible, impact resistant, lightweight or a combination thereof. In addition, the fabrication of such devices and structures onto a flexible substrate enables the integration of the substrate (laminate) into a more complex system, as in the example of FIG. 3, and the optimization and adaptability (CAPS approach) using plastic substrates. Is called. In addition to these advantages, these new devices and circuits can be present on polymer substrates such as elastomers that can be shrink-controlled in various forms. Devices and structures on flexible substrates can be used in rough environments as well as operated on curved surfaces.

The present invention provides for the fabrication of electronic, chemical, mechanical, fluid, display and optoelectronic devices and structures on flexible substrates despite the rough, uneven substrate surface, dimensional accuracy, mechanical strength, and thermal stability issues of flexible substrates. Provided by renewable and manufacturable technology. The invention disclosed herein provides the necessary separation layer materials, manufacturing techniques, and application concepts. 1A-1D and 2A-2D illustrate two general approaches using large surface area to volume ratio materials as separation layers. In either case, structures, circuits, devices, etc. (shown here as TFTs) are fabricated on the mother substrate and subsequently separated. In Figure 1, a carrier substrate material, such as a plastic material deposited or formed prior to the device fabrication process flow, is used to provide the necessary mechanical stringency after separation from the mother substrate. In Figure 2, a carrier substrate material, such as a plastic material deposited or formed after the device manufacturing process flow, is used to provide mechanical rigidity after separation from the mother substrate. The latter processes provide the advantage that the processing flow includes at least some high temperature processes. In either case, after separation, the plastic carrier material, including for example a device, a circuit, or both, may be attached to another laminate (FIG. 3), another substrate or another object.

In both approaches shown in FIGS. 1A-1D and 2A-2D, conventional rigid smooth substrates, such as Si wafers, quartz, or Corning glass substrates, are rigid moder substrates due to their compatibility with smooth surfaces and microelectronic processing. Is selected as. Such a moder substrate is reusable and may or may not have a coating layer on its surface. In the demonstration of the approach of FIGS. 1A-1D and 2A-2D, a sacrificial layer was deposited on the smooth surface of the silicon wafer serving as a rigid substrate. In general, such sacrificial layers are designed to be removed by chemical, mechanical, or some combination thereof. Then, as shown in FIG. 1A, a polymer film is coated on the sacrificial layer, and this polymer coating is baked for curing and degassing. This layer becomes a transport (carrier laminate) layer for delivering devices and circuits to their final location. Then, as shown in FIG. 1, a device was fabricated on this polymer coated substrate. The key process in this process is the creation of downward through holes at the interface between the polymer coating and the sacrificial layer. In this demonstration, lithographic techniques were used to define the location, size and number of through holes, and the holes were etched with a reactive ion etcher. These through holes serve as a conduit for the chemical (eg, acid, base or organic solution) used to remove the sacrificial layer. These chemicals flow through these ducts and penetrate to the top of the sacrificial layer, wet the sacrificial layer, and chemically attack the sacrificial layer material. In a specific experiment demonstrating this separation technique using a through hole conduit, the metal sacrificial layer was evaporated and a 10-5 nm polymer layer was spin coated onto Corning 1737 glass. After the through hole was defined lithographically and the hole was etched by reactive ion etching, the sample was immersed in acid. The acid penetrates through the through-hole duct to the top of the sacrificial layer, etches the sacrificial layer and diffuses in the transverse direction. The polymer coating separates as the acid moves transversely and etches the sacrificial layer. As this separation process proceeds further, the separated regions grow larger.

In the variations of FIGS. 1A-1D, the through hole for chemical access to the sacrificial layer may be in the mother substrate and, as noted, reusable. By removing the sacrificial layer, the device structures and circuits on the laminate can be separated from the rigid substrate as indicated in process (c) of FIG. 1. Since a separate device structure is disposed on the flexible polymer transport layer, such a device may be placed on any coarse substrate, any surface of planar or curved surface, or other laminate (FIG. 3), as shown in process (d) of FIG. Can be attached).

Figure 2 shows the general form of the second version of this approach. As shown in FIG. 2, the sacrificial layer is first deposited on a rigid mother substrate prior to the device fabrication process. Such a moder substrate may be reusable and have a coating. After fabrication of an electronic, chemical, fluid, mechanical, display, solar cell, or optoelectronic device and structure or some combination of these or other devices and structures, a carrier substrate, such as a polymer layer, is coated onto the device and structure. As shown in FIG. 2, a through hole from the polymer coating to the sacrificial layer is created. In this demonstration, the location, size, and number of through holes were defined lithographically using a photolithography process and the holes were etched with a reactive ion etcher or a wet process. These through holes provided a pipeline for the chemicals used to remove the sacrificial layer. These chemicals enter the structure through these ducts, penetrate the top of the sacrificial layer, wet the layer, and remove it by chemical attack. In the variation of FIG. 2, through holes for chemical access to the sacrificial layer may be present in the mother substrate. By removing the sacrificial layer, the device structure can be separated from the rigid substrate, as shown in process (c) of FIG. The separated device structure is covered by a carrier layer, such as a flexible polymer transport layer, so that the laminate can be transported and attached to any rough surface substrate, as shown in process (d) of FIG. 2. Such laminates may be formed together to produce the system shown in FIG. 3. The laminate can also be attached to any curved surface.

The present invention relates to the use of a general separation layer in the process shown in FIG. The invention also relates to the specific use of high surface area to volume materials, such as columner void network materials, as separation layers in processes such as those shown in FIGS. 1 and 2.

This separation process using through-hole ducts allows various devices and systems, including thin film transistors, sensors, actuators, microelectro-mechanical devices (MEMS), fuel cells and solar cells, to be placed on the transfer (laminate) layers of FIGS. 1 and 2. It can be employed to manufacture. Of course, this approach of using the sacrificial layer / through hole and transfer layer can be used to establish devices and circuits on pre-existing devices, wafers and dies.

High-performance structures that can be produced on plastic laminates in a separate approach can be used in other ways, ie the individual device-containing islands of plastic or other material laminates are cut after the structure of FIG. 1 or 2 is formed, Mowed or otherwise separated into individual dies. They can then be assembled into the required system using self-assembly techniques such as based on electrostatics, chemistry or spatial compatibility.

Alternatively, by using two sacrificial layers, a cavity (ie, a channel) can be formed using the deposited thin film material according to the present invention. One of these layers is a columner void layer and the second material is used in the portion of the area that becomes the channel. The other layer is some other material, such as a metal. This is the only sacrificial layer in other parts of the channel. The purpose of using the two materials to form the channel is to ensure that a very accurate and very shallow channel depth in a particular area is created where the sacrificial layer is used. That is, the shallow region may be as shallow as 10 nm in the region using metal, and the deep region in the same channel or cavity structure may be as deep as several hundred microns in the region using both sacrificial layers. As a result, channels with widely varying depths for sorting and sensor applications that can occur as molecules flow through the channel. In sensor applications, sensors may be placed in shallow areas.

II. Release layer

The release layer application of the membrane according to the invention may also have a number of applications. These applications are very similar to those of the separating layers, except that separate material systems are not completely separated and connected at least in one place. The advantages and treatments of the materials of the present invention in release layer applications are similar to separation layers. The only significant difference is that the material systems involved in the release layer application are not completely separated but are connected at least in one place.

Ⅲ sacrificial layer

The present invention relates in particular to the use of large surface area to volume materials deposited as sacrificial materials for the creation of voids (ie cavities). The resulting void-based structure has an empty area (cavity) area defined by an envelope of one or more materials. The size and shape of the cavity can be modified depending on the application purpose. Such structures include a nozzle structure; Cooling or heating applications; Mimicry circuit system capillary function for culture, tissue, and organic physics and nutrition support (e.g. nutrition transport, temperature control, oxidation, etc.), systems for drug diffusion and delivery, nebulizers for drug delivery Reaction chambers in chemical devices such as chromatographic tube applications, filtering or catalytic structures, liquid or gas delivery systems, and fuel cells; It can be used as a channel for microfluidic applications such as sorting and delivery structures for beads, particles, cells or molecular separation. These structures can also be applied to many MEMS devices, such as actuators, detectors, bolometers, and cantilever sensors.

The approach of cavity (void) formation disclosed herein for structures such as air gaps, cavities, channels and tubes is a surface micromachining technique based on the use of a sacrificial layer. Patterns that define cavity formation can be established by various pattern transfer approaches, including conventional lithography, jet printing, beam lithography, and soft and contact printing methods. A key feature of this new process flow is that the structures are formed using large surface area versus volume material deposited as sacrificial material. Specific demonstrations are performed with the unique columner void network structure film, which is an excellent large surface area versus volume material. For cavities, channels, etc. having cross-sections or empty cross-sections that are filled back after manufacture, the columner void material is removed using etchant / etch-product access holes, and the etch is combined with mechanical perturbation. If the deposited columner void material remains in the channel (ie remains to occupy a cross section), it is useful for sorting and filtering applications and the like, and no etching of such material is required. In this case, the columner void network material is not sacrificed, but is allowed to be used and remain to establish and support the void capping layer.

The inventors have discovered that the key to creating a manufacturable, renewable and controllable closed void area in a material is a large surface area versus volume material approach deposited. The present invention utilizes this approach using columner void network silicon, which, unlike conventional porous silicon, has a unique, regular and controllable columner void structure in which silicon is deposited and has nothing to do with electrochemical etching and the silicon penetrates the void. Proved. Using a plasma deposition process at low temperatures, materials can be placed on a wide variety of substrates, including previously formed circuits and devices, plastics, glass, organic and polymeric materials, and metal foils. The columner void structure makes excellent preparation for the creation of empty channels, voids, cavities and tubes in filter intermediate and hollow cross-section applications in filled channel applications. In the latter case, it is a sacrificial layer and provides a fast etch rate even when etched through a small wet-etch access window. The open area of the columner void network silicon film allows for fast transport of the etchant and reaction product upon removal of the sacrificial layer, and the fast sacrificial etch rate increases the overall process reliability. In addition, the fast etch rate allows the formation of microstructures with thin capping layers. The base, sidewalls, and top of the channels formed by this approach can be composed of various organic and inorganic materials, including elastomers, insulators, semiconductors, or metals. These may be composed of active layers such as current carrying structures, gate structures, piezoelectrics, pyroelectrics, ferromagnetics or magnetic materials. The bases, sidewalls and tops of the channels, voids, cavities, air gaps and tubes may be composed of materials such as small organic molecules or polymers. The sacrificial layer can be employed in the deposition / etch formation approach (FIGS. 4A-4F), the deposition / etch / lift-off formation approach (FIGS. 5A-5H), or a combination thereof.

Usually, when lift off treatment is used, the key to a successful process is to ensure that the thickness of the deposited film to be lifted off must be much thinner than the stencil layer in terms of the step pattern (see FIGS. 5A-5H), To ensure that the film is discontinuous. Therefore, lift off processes are often not used in the manufacture of MEMS or bio MEMS devices. This is because they require a relatively thick film. However, the deposited columnner void silicon of the present invention has a very unique continuous void (silicone column penetrating voids from the variant layer) structure, which is a stencil of gas and liquid for chemicals designed to remove this layer. Allows easy access to the layer (the layer causing the lift off). For example, if the stencil layer is a photoresist, it has been found that acetone can easily attack the photoresist disposed even under the thick columner void silicon layer. In this case, acetone passes through the void region penetrated by the silicon column to reach the photoresist (stencil) layer, dissolve the layer, and lift off the silicon film present on the stencil. Due to the unique columner void structure of certain silicon materials, this lift-off approach also works with thickly deposited columner void network Si films.

As pointed out, nano or micro voids, cavities, channels and the like can be prepared by some modification of the deposition / etch treatments (FIGS. 4A-4H), and very good deposition / etching / lift-off treatments (FIGS. 5A-5H). It can be produced by some modification of. In either case, manufacturing involves only low temperature processes and has flexible design rules. Deposition / etching / lift-off treatment is particularly useful because it provides a very simple treatment, ultraflat and thin capping layer. Both deposition / etching / treatment (FIGS. 4A-4F) or deposition / etching / lift-off treatment (FIGS. 5A-5H) are organic, plastic, glass, deposited semiconductors, semiconductors with previously manufactured circuits and chips, silicon It can be applied to a wide range of substrates, including chips or wafers, and metal foils. Note that these substrates can be bent either before or after manufacture.

The flat face and thin capping structures (e.g., channels for fluid flow) enabled by the lift-off approach increase the heat transfer efficiency by increasing the interface area that connects the flat face and thin capping layers to be heated or cooled. As it increases, it is beneficial for cooling or heating applications. Since the channels can be fabricated with low temperature, non-destructive processing methods, this approach allows cooling (or heating) structures to be built directly on the circuits and devices after fabrication. Since the channels of the present invention can be fabricated on metal or plastic foil, for example, a heat absorbing channel based structure is fabricated on a foil substrate such as the laminate of FIG. 3 and then attached onto circuits and devices for cooling and temperature control. Can be.

The flexible design rules allowed by this approach also include nozzles for voids, cavities, channels, etc .; Mimic circulation system capillary functions for culture, tissue, and organic support (eg, nutrient transport, temperature control, oxidation, etc.), capillary system for drug mixing and delivery; Nebulizers for drug delivery; Tubes for chromatography and fuel cells; Filtering or electrolyte structure; And other nano or microfluidic applications such as beads, particles, cells, or sorting structures for molecular separation. In addition, the channels can function as scaffolds as well as capillaries for cell, tissue and organ growth.

Detailed descriptions of examples of process flows related to the deposition / etch approach to fabricating nano- and micro-void structures can be taken using FIGS. 4A-4F. In the demonstration of the structure of FIGS. 4A-4F, firstly silicon dioxide is coated on a substrate (not shown in FIGS. 4A-4F) using a plasma Therm SRL 770 electron cyclotron resonance-plasma enhanced chemical vapor deposition (ECR-PECVD). Was actually deposited. Detailed deposition conditions are described in Table 1. Silicon dioxide was used as the base layer for the void structure, which (or other layers that could be used for the same function) was used when the columner void network silicon release layer was removed, i.e. such material could be used as an etch stop layer. Can be used to prevent any possible substrate from being etched. In the case of the treatment used to demonstrate the process flow of FIG. 4, the etchant used to remove the deposited columnner void network silicon was tetra methyl ammonium hydroxide (TMAH). Etch Deposition for Silicon Oxide Columner Void Network The etching selectivity of TMAH for silicon is very high, and 500 microseconds of silicon dioxide used in the present proof was thick enough to protect the substrate. Another purpose of silicon dioxide (or other first layer) deposition may be to function as an interdiffusion barrier layer and to improve the interface with the substrate used. The latter can be said to be very important for stress control, for example.

The micro- and nano-cavities made with this approach may be used for dielectric separation and adjustment of optical response and interaction. For example, they can be applied to interreflective and absorbing structures, intermetallic dielectric (IMD) microelectronic chip applications such as optical switches, waveguides and amplifiers, and optical device applications. For optical applications, the fundamental optical frequencies of the cavities can be tuned by changing the cavity size and shape, and the ambient material refractive index, and this ability to tune the resonance mode can be achieved by tunable optical gates, optical switches, channel drop filters, and It is very useful for optical devices such as optical interconnects. Low dielectric constant (ie, low k) applications may require multiple cavities, and structures need to provide lower dielectric constants and have mechanical stability, requiring a larger size cavity structure than optical applications.

The columner void network silicon layer was the next layer to be deposited in this proof. This was deposited after ECR-PECVD chamber conditioning using hydrogen plasma and oxygen plasma. Such conditioning can be used for process control for release, separation, or sacrificial layer deposition. The detailed chamber conditioning parameters that were used for this demonstration are described in Table 2. Conditioning with hydrogen plasma and oxygen plasma was performed for 30 and 10 minutes respectively. Then, columner void network silicon used as the sacrificial layer was deposited by the same ECR-PECVD. This columner void network deposited silicon layer is removed by a subsequent etching process (TMAH wet etching is used in this demonstration) to create a cavity region, so this silicon deposition will be a cavity area for air gaps, channels, etc. Decide if As shown in Figures 4A-4F, the thickness of the deposited columner void network silicon is the height dimension of the cavity of the present approach, and consequently the height of the cavity area can be changed very easily and accurately. Alternatively, another material is deposited before the columner void network silicon, and the columner void material is etched to deepen the final cavity (for channels, air gaps, etc.) whose depth is not controlled by the columner void silicon thickness. Can be designed to etch. Examples of such voids (cavities) are shown in FIGS. 6A-6H. In this case, the processing approach of FIGS. 5A-5H is followed and the approach of FIG. 4 is also used.

4A-4F, after completion of deposition of the columner void network silicon layer, another 500 microseconds of silicon dioxide layer was deposited on the silicon layer in this example. This was done because the columner void network silicon is extremely mechanically brittle due to the large pore volume possible due to the structure of the column passing through the continuous voids. If such a coating layer is not used, the columner void network silicon may also be damaged by the developer and photoresist removal solution used in the lithography process.

In the present proof of the present invention using deposited columnner void network silicon that produces void (ie cavity, channel, airgap, etc.) structures, the three layer sandwich provided after the three depositions described previously is lithography. Patterned and etched to provide the structure shown in process (b) of FIG. Then they were coated with silicon nitride where this capping layer was deposited by ECR-PECVD. Silicon nitride serves as the pillar and capping (loop) layer in this particular experiment. Detailed deposition parameters are shown in Table 1. In the shown proof, 1000 ns of silicon nitride was deposited on the top of the three layers and on the sidewalls and base of the holes. This was very suitable. The thickness of the silicon nitride layer can be adjusted to change properties such as strength, dielectric constant, optical properties, diffusion barrier properties, thermal conductivity, or some combination thereof. Other coating materials may be used and similarly adjusted. Alternatively, the lift off process is used to form the deposited porous silicon region and only the capping function will be played by this layer.

Small window structures are needed or adjacent to the cap layer to etch away the deposited columner void network silicon sacrificial layer as shown in FIG. 4D. In this demonstration, they were established using a lithography process performed using Shipjley 1813 photoresist. After the lithography process, the window pattern was etched by a plasma Therm 720 reactive ion etching (RIE) system. CF ₄ / O ₂ plasma was used and detailed etch parameters are described in Table 3.

ECR-PECVD Deposition Parameters Silicon dioxide Columner Void Network Si Silicon nitride RF power (W) 900 500 900 Process pressure (mtorr) 4 8 4 Substrate temperature (℃) 300 100 300 Process gas / flow rate (sccm) SiH ₄ / 4O ₂ /5.1Ar/3 SiH ₄ / 2H _2/40 SiH ₄ / 4N ₂ / 5Ar / 3 Deposition time (min) 3.47 30 12.20

Chamber condition parameters Hydrogen plasma Oxygen plasma RF power (W) 800 800 Process pressure (mtorr) 5.5 4 Substrate temperature (℃) 300 300 Process gas / flow rate (sccm) Ar / 3H _2/20 Ar / 3O _2/18 Deposition time (min) 30 10

RIE Etching Parameters DC power (W) 400 Process pressure (mtorr) 200 Substrate temperature (℃) 25 Etching time (min) 1.10 Etching Gas / Flow Rate (sccm) CF ₄ / 45O _2/5

The nanostrip removed the photoresist used to define the RIE process by soaking the samples in solution for 10 minutes. Next, a 0.1% solution of BOE (buffered oxide etchant) is followed to remove the original oxide layer on the columner void network silicon surface exposed by the window. The BOE process is very important because it can impact other structural layers. Therefore, BOE etch time and concentration of solution are very important in this particular proof.

With the etchant / reaction product window in place, the deposited columnner void network silicon sacrificial layer was removed by TMAH solution. For the voids (cavity regions) of the present proof, columner void network silicon sacrificial layer removal takes less than 30 minutes to complete as compared to a conventional release layer process which takes more than 20 conventional hours. Rinsing and drying processes after etch removal of the release layer are important process processes since the structure becomes very brittle after the release layer etch. Rinse is achieved by immersing the sample in DI water with constant flowing additional DI water entering the bath. Samples are rinsed for at least 1 hour and dried by very weak nitrogen blow dry. The angle of the nitrogen flow is very important and the blowing direction is almost parallel to the sample surface. It has been found that vacuum chamber environmental drying is a very efficient and least impacting process on the sample. The present proof result of the approach of FIG. 4 is the void structure shown in FIG. The structure of the void-column deposited porous silicon consists of a continuous array of voids (small holes) column, thus this is the void column network material.

A detailed description of an example of a very good deposition / etching / lift-off approach according to the invention is provided using the method provided in FIG. 5. In the actual proof of processing following this procedure, Corning 1737 glass is used as the substrate. Acetone, IPA and DI water are used to wash this substrate in an ultrasonic bath for 20 minutes. Next, after the substrate was baked on a hotplate for 10 minutes to remove DI water vapor, 5000 ns of silicon nitride was deposited using electron cyclotron resonance-plasma enhanced chemical vapor deposition (ECR-PECVD) on the washed substrate. Detailed deposition conditions of silicon nitride that serve to define the base of the channel of this example are shown in Table 4. Shipley 1813 photoresist is used in the first lithography process (ie, patterning of the nitride) and this pattern is used again in the lift-off process. The photoresist's properties are a decisive factor in the lift-off process because the photoresist hardens when exposed to high ion energy plasma for a long time and is difficult to remove using acetone cleaning in an ultrasonic bath. Most of the columner void silicon film is deposited on a stencil (here photoresist) which is lifted off within one minute submerged in the present bath and the process is completed after three minutes. The lift-off process provides a super flat surface without chemical mechanical polishing (CMP) treatment, allows the selection of a thin capping layer that maintains a flat surface, and allows multiple layers of tube or cavity structures with crossovers. The substrate is washed with acetone, isopropylal alcohol and deionized water after lift-off. Next, 2000 ns of silicon nitride was deposited on the top of the substrate as a capping layer. Deposition conditions are the same as the first silicon nitride layer, and the deposition rate is calculated from the first silicon nitride deposition. Si ₃ N ₄ was etched for 160 seconds at 200 W and 50 G, and CF ₄ and O ₂ were used as process gas in the proof. For example, if the photoresist functions as a defining layer and stencil for nitride etching, one lithography process can be used to define both the channel base and the stencil layer. The nitride is etched by reactive ion etching (RIE) using a CF ₄ / O ₂ mixed gas under the conditions of Table 5. The silicon nitride layer is over etched to ensure removal of the layer. In this example, the photoresist mask for this nitride base definition etch is not used as a stencil for lift-off. Instead, although the same photoresist layer pattern is needed in the subsequent lift-off process, it is removed using acetone. There are two reasons for photoresist removal used in this particular example. The first reason is that, for the etching parameters and materials used in this example, the photoresist used as the nitride mask can be a bad recommendation for the lift-off process because it is difficult to cure and remove due to the etching plasma exposure. . The second reason is that for the etching parameters and materials used, there is a thickness change in the photoresist in the treatment of this example due to plasma exposure. This can be a factor that causes errors in the subsequent lift off process, so that the nitride mask photoresist is removed after the nitride etch that mitigates these two factors. A second photoresist and exposure is performed to form a stencil. Alternatively, the parameter or material is altered to eliminate this second photoresist application and the need for exposure. For example, thicker photoresists that function as both nitride etch masks and stencils can be used to eliminate the need for this double lithography process employed in the present proof. Alternatively, non-polymeric material can be used as the stencil for lift-off.

After the creation of the stencil, column / void networked silicon was deposited using the same ECR-PECVD used for silicon nitride deposition and the detailed deposition parameters are described in Table 4. The lift-off is then performed in an ultrasonic acetone bath. Most of the columner void silicon film deposited on the stencil (here photoresist) was lifted off within 1 minute of soaking in the bath and the process was completed after 3 minutes. The lift-off process provides super flat surfaces without chemical mechanical polishing (CMP) treatment and allows the selection of a cavity structure with a thin capping layer, multiple layers of tubes or crossovers to maintain the flat surface. The substrate is washed with acetone, IPA, and DI water after lift-off and baked for 10 minutes on a hotplate. Next, 2000 ns of silicon nitride is deposited on the top of the substrate as a capping layer. Deposition conditions are the same as the first silicon nitride layer, and the deposition rate is calculated from the first silicon nitride layer deposition.

An additional lithography process is then performed to allow wet etchant access to the columner void film by creating a window (access hole for the chemical used to attack the sacrificial material) at a predetermined location. RIE is used to etch these spaced windows. The etching conditions are the same as before, and the etching time is calculated from the first silicon nitride etch rate. The substrate is immersed in 1% BOE for 2 minutes to remove any oxide layer grown on the columner void silicon surface prior to sacrificial layer etching. 5% tetramethyl ammonium hydroxide (TMAH) is then used to perform etching of the sacrificial layer columner void silicon through the access hole. This TMAH solution was heated at 75 ° C. The etched samples are then washed in flowing DI water for 30 minutes and dried in a vacuum environment.

The access window is sealed using spin on glass (SOG) (see FIG. 5), and the thickness of the SOG film can be tuned by changing the rotational speed of the chuck. The sample is processed on a hotplate. If good for applications such as nutrient delivery, drug delivery, spraying, these access hole windows are left unfilled.

ECR-PECVD Deposition Parameters Columner Void Network Si Silicon nitride RF power (W) 500 900 Process pressure (mtorr) 8 4 Substrate temperature (℃) 100 100 Process gas / flow rate (sccm) SiH ₄ / 2H _2/40 SiH ₄ /10.7N ₂ / 8Ar / 3 Deposition time (min) for 5000Å 30 30

RIE Etching Parameters DC power (W) 200 Process pressure (mtorr) 200 Substrate temperature (℃) 25 Etching time (min) for 5000 ms One Etch Gas / Flow Rate (sccm) CF ₄ / 45O _2/5

A cavity structure fabricated following the process flow concept outlined in FIG. 5 is shown in FIG. 8. 8 shows a micro tube. The width of this tube is in the range of about 100 μm or less, preferably between 10 μm and 50 μm and has a base layer under the tube substrate. The height of the tube is in the range of 0.5 µm to 50 µm, and may be as low as 50 nm. Since a silicon wafer is used as the substrate, a base layer Si ₃ N ₄ is used in the tube to prevent substrate etching during the sacrificial layer etching process. The capping layer used for these tubes is 5000 mm thick. This thickness appears too thin for a 50 μm wide tube and appears to have some cap layer that curves in the middle. Flexion is caused by bubbles generated during sacrificial layer etching. For example, for a 5000 kPa capping film, the height of the bend is about 1.5 μm. This is about three times the height of the original tube. This high etch rate of the columner void network material prevents thinning and damage of other structural materials and enables the fabrication of tubes up to 100 μm wide. For tubes greater than 100 μm in width, the 5000 kPa capping layer results in a cracked tube ceiling, and the ceiling is destroyed due to stress due to capping layer bending. Thicker capping layers improve the capping layer bending problem and allow for the manufacture of wider tubes.

Thicker capping layers allow for wider tube fabrication, and altering the design and placement of the access holes can be another factor allowing tube structures wider than 100 μm.

There are applications such as sorting and filtering where it is beneficial to leave the columner void network in the cavity, channel, air gap, etc. without removing it. This may be done in one of the process flows schematically depicted in FIG. 4 or 5 or some variation or combination thereof.

Using a large surface area to volume ratio material as the sacrificial material allows for sacrificial material removal in a deposition / etching approach or a deposition / etching / lift-off approach. The deposition / etch approach is schematically illustrated in FIG. 4. The deposition / etching / lift-off approach is shown schematically in FIG. 5. In the proof of the invention, both approaches are used in combination with columner void network silicon deposition films. The lift-off based approach, which has not been proposed or proven in conventional electrochemically prepared porous silicon, has several advantages. In other words, it is simple and manufacturable, allowing the use of thick sacrificial layer silicon films if necessary, and can be used to create extremely flat faces of void areas defining sidewalls, bases and tops, if desired. Alternatively, it can be used to create relatively large cross-section channels, tubes, sorting structures, etc., without the so-called deep etch reactive ion etch process, as shown in FIG. In general, even when thick silicon sacrificial films are lifted off (i.e. removed in the selected area), due to the columner void network structure of the current film, a very effective lift-off treatment is possible. The unique column / void structure allows the etch liquid to efficiently reach the stencil (cause lift off) layer under columner void silicon in the interchannel region. The stencil layer defining where the silicon material is removed is attacked by a chemical that penetrates the columner void silicon layer. This results in the dissolution or etching removal of the stencil layer and the floating (ie lift-off) of the currently unsupported silicon layer in areas such as between channels or between air gaps. The columner void silicon to be the channel region is not lifted off as shown in FIG. 5 or FIG. 6. The lift-off process eventually appears to be very flat in the inter-channel, etc. area, eliminating the need for any planarization process and allowing the thickness of the capping layer of FIG. Thus, if necessary, very thin capping layers are allowed. The capping layer is a film that defines the top (ie, roof) of the void structure (eg, channel, tube, air gap, etc.) as shown in FIGS. 4, 5, or 6. Since thick capping layers can interfere with material or heat transport through capillaries (ie channels), thin capping layers can be a key factor for some applications such as nutrient delivery, drug delivery, and micro-cooler or heater applications. have. In some applications, such as fuel cells, the capping layer may consist of a number of materials or sublayers in which part of it is actually patterned (eg, grid or screen pattern). In some applications, such as sorting and sensing, the capping layer may be patterned (eg, grid or screen) or may be a permeable member that separates low void areas on top of other such areas.

Ⅳ Application

The above description has outlined several specific applications of separation technology, release layer technology, sacrificial layer technology and combinations thereof. In many of these applications, it is clear that using the present sacrificial layer approach to create a structure on a laminate on a mother substrate and then separating the laminate from the mother substrate using this separation scheme. In all cases, these applications are intended to suggest the flexibility and availability of the approach of the present invention.

(a) fuel cells

The present invention demonstrates a novel manufacturing process for micro unit fuel cells based on using the sacrificial layer approach according to the present invention. The fabrication processes used include photolithography, reactive ion etching (RIE), chemical vapor deposition (CVD), selective wet etching, and deep silicon etching. However, a unique feature of the operation according to the invention is the use of a large surface area to volume ratio material for the sacrificial layer. In the present proof provided herein as an example, the present low-deposition temperature deposited columner void network material is used as a sacrificial layer for channel formation. Columner void network silicon is removed with high etch selectivity to other structural materials to define the channel for fuel cell fabrication. Another unique aspect of this study is the use of lift-off in combination with deposited columnner void network material. In addition, the SiO ₂ material deposited in the proof is used as the proton transporting medium. Other proton transport materials can be utilized, including Nafion. In the proof, the deposited Si ₃ N ₄ is used as the only proton confinement layer. This application of nitride may or may not be used depending on the situation.

The advantages of this particular fuel cell design and fabrication include (a) ease of manufacture, (b) compatibility with lightweight substrates such as plastic and metal foils, (3) ease of combination into stacked structures, and transistors for power management, Ease of integration with diodes or both, (4) ease of integration with sensors for chemical reaction control, (5) ease of integration with various micro-fluids, display pixels, sensors and detectors to enhance various functions, and (6) includes ease of integration into a stacked structure as shown in FIG.

9A illustrates a fuel cell structure fabricated on a silicon wafer in accordance with the present invention. Here, the electrode, the solid electrolyte and the base unit of the electrode are fabricated on the silicon wafer, and the channel is patterned by selective etching of the sacrificial layer. Channels inherent in the silicon substrate function as a supply path for fuel to the fuel cell. A fuel, a hydrogen-containing source such as hydrogen gas, or an alcohol such as methanol is supplied through the channel for the electron-emitting reaction shown in FIG. 9A. This reaction is the oxidation of a hydrogen source that produces byproducts such as protons, electrons and hydrocarbons. The electrode from which this occurs consists of a catalyst such as platinum or palladium. Protons produced by this oxidation reaction diffuse into the proton transport layer toward the counter electrode. However, the electrons are blocked from entering the proton transport layer due to the low electrical conductivity. Hydrocarbon-polymer materials, such as, for example, Nafion ^{™ from} DuPont, have been used in member electrolytes for fuel cells for many years and can be proton transport layers in FIG. 9A. In the present invention, other materials such as deposited silicon dioxide having high proton conductivity can be used for such a solid proton transport layer. Protons penetrate the electrolyte (eg, Nafion ^™ or silicon dioxide) towards the other electrode, where a reduction reaction occurs. This is the reduction of the arriving protons utilizing the electrons and oxygen coming through the external electrical circuit. In FIG. 9A, this oxygen is supplied from the atmosphere. In another arrangement, oxygen is reaching through the channel in the same way as hydrogen. As shown in FIG. 9A, the deposited Si ₃ N ₄ layer is used with a hydrogen source channel to block transverse proton transfer. Alternatively, this layer can be replaced by deposited SiO ₂ which is designed to produce a more transversely uniform proton supply.

Such fuel cells can be fabricated on other types of substrates such as polymers, glass and metal foils. For example, as shown in FIG. 9B, a silicon layer or other material may be deposited on a fuel cell fabricated on a plastic, glass or metal foil substrate and the deposited silicon layer. In this case, the sacrificial layer is removed as shown in FIG. 9A and the removal chemistry is used to etch the deposited silicon instead of the wafer material as needed.

The detailed process sequence is shown in FIG. 10A and the other is shown in FIG. 10B. In FIG. 10A, a thick silicon nitride layer is first deposited on a silicon wafer to define the channel and to function as a masking layer for channel etching. In certain fabrication sequences performed for demonstration, other deposition processes may also be used, but electron cyclotron resonant plasma enhanced chemical vapor deposition (ECR-PECVD) is used for silicon nitride deposition. Process conditions for silicon nitride deposition are shown in Table 6. In this particular proof of the invention, 2500 ns of silicon nitride was deposited using 15 minute deposition. Channel regions are defined by photolithography and magnetically enhanced reactive ion etching (MERIE) techniques. In this demonstration, 1.3 μm thick photoresist and I-line contact aligner were used in the photolithography process. A 30 second exposure to MERIE was performed to etch 2500 ns of silicon nitride including overetching. Process conditions for MERIE etching of silicon nitride are shown in Table 7. After reactive ion etching of silicon nitride, the deposited columner void network silicon material is deposited for the sacrificial layer. Table 8 shows details of columner void network material deposition. As shown, it was deposited on photoresist and silicon. After this deposition, the columner void network material on the photoresist is removed by the lift-off procedure described in detail above. In the lift-off process, columner void network material outside of the channel is attached by dissolving the underlying photoresist.

Deposition Conditions for Silicon Nitride Using ECR-PECVD item Details Condition Environment Temperature 100 ℃ pressure 4mTorr gas Ar 3sccm SiH ₄ 10sccm N ₂ 8sccm Plasma conditions Upper magnetic 173 Bottom magnetic 24 RF power 900 W Deposition rate 167 Å / min (2500 Å @ 15min)

MERIE Process for Silicon Nitride item Details Condition Environment Temperature 25 ℃ pressure 200 mTorr gas CF ₄ 45sccm O ₂ 5sccm N ₂ 8sccm Plasma conditions Magnetic 50 Gauss RF power 200 W Deposition rate 7000 Å / min (3500 Å @ 30sec)

Deposition Conditions for Columner Void Network Materials Using ECR-PEVCD item Details Condition Environment Temperature 100 ℃ pressure 8mTorr gas Ar 2sccm SiH ₄ 40sccm Plasma conditions Upper magnetic 173 Bottom magnetic 24 RF power 500 W Deposition rate 167 Å / min (2500 Å @ 15min)

After the lift-off process, an electrolyte / electrical contact layer that assists in proton formation and electron glass is deposited on the entire surface, including the columner void network silicon material remaining in the channel. In this demonstration, a 300 kHz platinum layer is deposited on the photoresist by electron gun evaporation. The photoresist is patterned to form a screened or grid electrolyte layer, which eventually becomes a metal having this pattern after another lift-off process. In this process, this metal is disposed on and supported by the sacrificial layer. After formation of this electrode, a solid electrolyte is deposited. If silicon dioxide is used as the proton transport medium, the ECR-PEVCD process is used for deposition. When the Nafion membrane was used for the proton transporting medium, spin coating was used. Table 9 shows the process conditions for silicon dioxide using ECR-PEVCD. In the proof using Nafion, the coating procedure is performed for 30-50 seconds at a rotational speed of 500-4000 rpm depending on the target thickness.

Deposition Conditions for Silicon Dioxide Using ECR-PECVD item Details Condition Environment Temperature 100 ℃ pressure 4mTorr gas SiH ₄ 4sccm O ₂ 5.1sccm Ar 3sccm Plasma conditions Upper magnetic 173 Bottom magnetic 24 RF power 900 W Deposition rate 130 Å / min (3900 Å @ 30min)

At this point, through holes are created to provide access to the sacrificial columner void network material. These are patterned by selectively etching solid proton transport media. In the case of silicon dioxide, BOE (buttered oxide etchant 10: 1 NH ₄ : HF) is used to selectively etch the oxide at an etching rate of 14600 mA / min at 21 ° C. After through hole etching, the channel is opened by selective etching of columner void network material and substrate silicon in an etching solution such as TMAH (tetra-methyl ammonium hydroxide), NH ₄ OH solution. The columner void network material layer functions as a blotter to allow easy and uniform access by the etchant. These columner void network materials have high etch rates in TMAH solutions. The etchant can also attack the silicon layer uniformly as shown in part of FIG. 10A. Since the columner void network material functions as a blotter and etch exposes the underlying Si very uniformly, this is a very uniform etching of the underlying silicon (whether wafer material or deposited Si). Of course, these blotting and etchant-source functions of the columner void material can be adjusted by adjusting the membrane porosity and through hole position and size. In this demonstration, a 20 minute etch in a 5% TMAH solution at 75 ° C. eventually results in a 15-20 μm deep channel in the silicon substrate. The channels produced by this etching allow for fuel supply after completion of fuel cell manufacturing (part 5 of FIG. 10A).

If the substrate is a [100] -oriented silicon wafer, the channel shape may be as shown in portions 4 and 5 of FIG. 10A. In the case where the substrate is silicon or other material deposited on a coated or uncoated mechanical substrate, such as glass, plastic, metal foil or other material, the channel shape becomes something like parts 4 and 5 in FIG. 10B. The protruding layer (Si ₃ N _{4 in} FIG. 10B) mechanically supports the grid and the solid electrolyte. If Si ₃ N ₄ is used, this also interrupts interchannel communication. If this treatment is performed with silicon or other material formed in or on the laminate on the mother substrate, the laminate can be separated as outlines and used as shown in FIGS. 1, 2 and 3.

After channel formation, depending on the position of the through hole, additional deposition of the solid proton electrolyte may be required to cover the entire surface with the electrolyte material. In either case, after filling the through holes, the top (reduction grid) layer is deposited on top of the electrolyte and patterned in the same way as the patterning used for the other electrodes.

The micro-unit fuel cells produced by the present invention have a wide range of applications. In addition, the size of the fuel cell produced by the present approach outlined herein can be reduced to be as small as required by the particular application. Current technology can easily define patterns of several hundred nanometers or less. In this size situation, a channel can be defined as a "nano-channel".

Typical PEM fuel cells include one or more layered membranes and separators that are stacked alternately with each other. This layered sandwich includes a polymer electrode member (PEM), an anode and a cathode, and a PEM film is sandwiched between two electrodes.

These small fuel cells, which can exhibit better efficiency than conventional conventional micro-unit fuel cells, are integrated on-site with MEMS devices, displays, sensor arrays, detector arrays, and all multifunction systems on the same substrate. -site) can be a power generator. In addition, using the processing techniques outlined herein, the fuel cells can be stacked on top of one another to produce higher voltages or, if desired, to be connected in parallel to produce higher currents. In addition, these cells can be fabricated on plastic or other types of laminates and integrated into the system as shown in the CAPS concept of FIG. 3. Fuel cells are promising means for the portable power of mobile electronics because of their light weight and high energy density. Portable power usage applications include a wide range of consumer electronics such as cellular phones, laptop / palmtop computers, video camcorders, and the like. By incorporating the micro-unit fuel cell approach into lightweight substrates such as plastic, glass and foil, it enables the power supply of systems including lightweight displays, sensor and detector structures, telecommunications, and these and other functions.

(b) smart power

The fuel cell structure described above can be fabricated with both integrated in a transistor, diode or fuel cell layout. In the presence of such electronics, the circuit is integrated with the fuel cell structure to provide a smart power laminate. This smart power combines fuel cells in parallel, in series, or in a modified form together on demand to provide the instantaneous current, voltage and power needed for the application. Sensors, detectors and MEMS devices are also integrated into such a system, allowing chemical reaction control and fuel switching and consumption control.

(c) display

The cavities and channels that can be created by the sacrificial layer approach can be used for display applications. For example, these structures can be created with electrodes in the envelope layer. They may have a field divergence source or may be filled with a gas selected to ionize to form a light divergence plasma when a voltage is applied to these electrodes. Therefore, each cavity or channel is used as a pixel and separately controlled to form a plasma color display. Control can be built in or on the material from which the cavity or channel is built. If a transistor or diode is used for such control, an active matrix plasma display can be constructed. Obviously, this can be achieved on a laminate that is separated from the mother substrate using a separation method as well. Such display laminates can be part of the system shown in FIG. 3 if desired.

(c) Sorting and Sensor Structure

Using the sacrificial materials and methods disclosed herein, sorting, filtering and sensor structures can also be fabricated on plastic, glass or metal foil. Integrating these procedures with the separation layer method means that such structures can be separated for use in a system such as the concept of FIG. 3 after being formed in and on the material on the mother substrate. Integrating these structures with active circuit elements in and on the same material means that these structures can be compliant and smart. Figure 11 shows the sacrificial layer material, the design and the actual DNA sorting structure produced using the fabrication methods described above.

Structures with channels or even the variable cross-section of FIG. 11 may have electrodes or conductive grids integrated into the enveloped cavity walls, ceilings or floors. As possible with the deposition sacrificial layer, careful control of the electrode or grid spacing allows these spacings to accommodate molecular units. With the appropriate choice of self-assembled molecules and the electrode and grid material, molecules for adhesion between these spaces can be selected. Molecules can be selected for detection and sensing. For example, single stranded DNA can be attached to these channels such as that of FIG. 11 and used to detect incoming DNA samples. For example, detection can be accomplished by changing the interelectrode conductivity. Such detection can be accomplished for other entities by the selection of molecules immobilized between electrodes.

(e) release structure

Columner void network materials are very effective as release materials. Release layers are commonly used in many MEMS devices to form structures that are connected to other material systems in at least one location. An excellent example of a release layer application is the creation of cantilever structures. The materials of the present invention have high etch rate and etch selectivity compared to commonly used structural layers such as silicon nitride and silicon oxide, making them very effective for release layer applications. In fact, the etch rate of the columner void network film, 2.5 μm / min, is about four times faster than the polysilicon etch rate, 0.6 μm / min, and poly Si is one of the most commonly used release agents. In addition, the fast etch rate of the film reduces the chemical exposure time of the structural layers, thus increasing the overall process reliability. 13 shows a micro-switch structure as an example of release layer utilization in manufacturing.

It is obvious that the above description is merely provided for the description of the present invention. Those skilled in the art can design various alternative methods and modifications without departing from the present invention. Accordingly, the invention is intended to embrace all such alterations, modifications and variations that fall within the scope of the appended claims.

Claims (99)

In the method of processing a substrate, (a) forming a high surface area to volume ratio material layer on the surface of the substrate; And (b) removing at least a portion of the high surface area to volume ratio material layer Substrate processing method comprising a. The method of claim 1, wherein the high surface area to volume ratio material layer is deposited on the substrate in step (a) and the high surface area to volume ratio material layer has a ratio of up to 10,000 to one. The method of claim 1, wherein the high surface area to volume ratio material layer is a columner void layer onto which metals, dielectrics, and semiconductors are deposited. The method of claim 3, The columnar void layer comprises a plurality of essentially homogeneous non-contact base columnar units that penetrate successive voids, the units having an adjustable constant spacing, an adjustable uniform height and an adjustable variable diameter. And the plurality of basic columnar units are arranged uniformly oriented on the substrate. The method of claim 4, wherein the basic columnar unit comprises at least one component selected from the group consisting of silicon, germanium, carbon, hydrogen, inorganics, organics, and mixtures thereof. The method of claim 3, wherein the columner void layer has a thickness of at least 10 nm. The method of claim 3, wherein the columner void layer is deposited in a vacuum environment at a pressure lower than atmospheric pressure. The method of claim 3, wherein the columner void layer is deposited at a temperature of about 250 ° C. or less. The method of claim 1, wherein the high surface area to volume ratio material layer is formed on at least one intervening layer disposed between the high surface area to volume ratio material layer and the substrate. The method of claim 1, wherein the removal of the high surface area to volume ratio material layer in step (b) is performed by chemical, physical, or combinations thereof. The method of claim 1, wherein the removal of the high surface area to volume ratio material layer in step (b) is performed by means selected from the group comprising dry etching, wet etching, and combinations thereof. The method of claim 1, wherein a portion of the substrate is removed before, during, or after removing at least a portion of the high surface area to volume ratio material layer in step (b). 10. The method of claim 9, wherein a portion of the intervening layer or layers between the high surface area to volume ratio material layer and the substrate are removed. The substrate of claim 1, further comprising depositing at least one coating on the high surface area to volume ratio material layer after forming the high surface area to volume ratio material layer on the surface of the substrate in step (a). Treatment method. The method of claim 14, wherein the at least one coating is organic or inorganic. 15. The method of claim 14, further comprising fabricating a device, structure, or combination thereof on the at least one component selected from the group comprising a device, a coating structure, a coating, and a mixture thereof. 17. The method of claim 16, wherein removing at least a portion of the high surface area to volume ratio material layer in step (b) comprises at least one component selected from the group comprising a device, a coating structure, a coating and a mixture thereof from the substrate. Substrate processing method for removing. 17. The substrate processing of claim 16, further comprising removing the high surface area to volume ratio material layer by creating a through hole through at least one component selected from the group comprising a device, a coating structure, a coating, and a mixture thereof. Way. 17. The method of claim 16, further comprising removing the high surface area to volume ratio material layer by creating a through hole through the substrate. 17. The method of claim 16, further comprising removing the high surface area to volume ratio material layer by creating a through hole through at least the coating. 17. The method of claim 16, further comprising forming a second coating on at least one component selected from the group comprising a device, a coating structure, a coating, and a mixture thereof. 22. The method of claim 17 or 21, wherein the second coating system carries by carrying out the transport of a combination comprising devices and structures after removal of the high surface area to volume ratio material layer of step (b). The substrate processing method which makes it function as a carrying substrate. 23. The method of claim 22, wherein after removal of the high surface area to volume ratio material layer of step (b) through the resulting through hole, a device, coating structure, coating, and mixtures thereof are selected from the substrate. After separating at least one component, disposing the separated device, coating structure, coating or mixture thereof on a second substrate. The method of claim 1, wherein removing a portion of the high surface area to volume ratio material layer in step (b) comprises selectively etching the high surface area to volume ratio material layer to leave a portion thereof. . 25. The method of claim 24, further comprising forming at least one layer on the remaining portion of the high surface area to volume ratio material layer. The method of claim 25, (a) creating a through hole accessing the high surface area to volume ratio material layer; And (b) removing the remaining portion of the high surface area to volume ratio material layer using the through hole to create a cavity structure. Substrate processing method further comprising. 27. The method of claim 26, wherein using the through hole to remove the remaining portion of the high surface area to volume ratio material layer to create a cavity structure, then depositing at least one additional layer on the at least one layer. And blocking the through hole. The method of claim 1, wherein providing a substrate comprises depositing a stencil layer on the substrate, patterning the stencil layer, and selectively removing a portion of the stencil layer. Leaving exposed portions and at least one residue of the stencil layer. 29. The method of claim 28, wherein forming a high surface area to volume ratio material layer comprises forming the high surface area to volume ratio material layer on the exposed surface of the substrate and the at least one residue of the stencil layer. Removing the portion of the high surface area to volume ratio material layer deposited thereon by lifting off the stencil layer. 30. The method of claim 29, further comprising (c) depositing a second layer on the substrate and the high surface area to volume ratio material layer. 31. The method of claim 30, further comprising creating a cavity structure by creating a through hole through the second layer for removal of the high surface area to volume ratio material layer in step (c) through the created through hole. Substrate processing method. 32. The method of claim 31, further comprising: (d) depositing a layer blocking said through hole after removal of said high surface area to volume ratio material layer in step (c) through said created through hole to create a cavity structure. Substrate processing method further comprising. 32. The method of claim 31, after the removal of the columner void layer in step (c) through the created through hole to create a cavity structure, adding gas or liquid in the cavity structure and Depositing a layer that blocks and seals the cavity structure. The method of claim 1 comprising prior to step (a), after a material system is deposited on the substrate, and subsequently selectively removing a portion of the deposited material system to leave a portion of the material system. Substrate processing method. 35. The method of claim 34, wherein forming the high surface area to volume ratio material layer on the substrate further comprises removing a portion of the high surface area to volume ratio material layer to expose a portion of the residual material. . 36. The method of claim 35, further comprising depositing additional material on the high surface area to volume ratio material layer and exposed portions of the previously deposited material such that a portion of the additional material is exposed to the previously deposited material. The substrate processing method which contacts a part. A method for transferring a system of material from a substrate, a) forming a high surface area to volume ratio material layer on the substrate; b) forming at least one coating on said high surface area to volume ratio material layer; c) manufacturing at least one component selected from the group comprising a device, a coating structure, a coating and a mixture thereof on the at least one coating; d) separating from the substrate at least one component selected from the group comprising a device, a coating structure, a coating and a mixture thereof by removing the high surface area to volume ratio material layer The delivery method of the material system comprising a. 38. The method of claim 37, wherein the high surface area to volume ratio material layer is a columner void layer. The method of claim 38, wherein the columner void layer is deposited. The method of claim 38, The columner void layer is a nanounit composition, (a) a plurality of essentially homogeneous non-contact base columnar units penetrating successive voids, the units having adjustable regular spacing, adjustable uniform height, and adjustable variable diameter, (b) the plurality of basic columnar units are uniformly oriented and disposed on the substrate. 38. The method of claim 37, wherein the first substrate is a rigid substrate. 38. The method of claim 37, wherein the first substrate is at least one selected from the group consisting of silicon wafers, quartz, glass, organic materials, polymers, ceramics, semiconductors, metals, insulating materials, and mixtures thereof. . 38. The method of claim 37, wherein forming at least one coating on the high surface area to volume ratio material layer in step (b) comprises applying, spin-coating, screening, printing, sputtering, dehydration, chemical deposition, A method of delivery of a material system performed by a technique selected from the group comprising physical deposition and spreading. 38. The method of claim 37, wherein the at least one coating is organic, inorganic or some combination thereof. The material system of claim 37, wherein the at least one coating is a material selected from the group comprising chemically active materials, polymers, insulators, nitrides, oxides, piezoelectrics, ferromagnetics, metals, pyroelectrics, biological materials, and semiconductors. Way of delivery. 38. The device of claim 37, wherein the at least one component selected from the group comprising a device, a coating structure, a coating and a mixture thereof is selected from the group consisting of sensors, actuators, electronics, chemical micro-fluidics, detectors, fixed structures, circuits, displays. A method of delivering a material system selected from the group comprising: acoustic devices, solar cells, optoelectronic devices, fuel cells and combinations thereof. 38. The method of claim 37, further comprising creating a through hole used to remove the high surface area to volume ratio material layer. 48. The method of claim 47, wherein the through hole comprises the substrate, the high surface area to volume ratio material layer, an intervening layer between the substrate and the high surface area to volume ratio material layer, a coating layer on the high surface area to volume ratio material, and combinations thereof. A method of delivery of a material system produced through at least one layer selected from the group. 48. The method of claim 47, wherein the generation of the through holes is performed using one technique selected from the group comprising dissolution, dry etching and wet etching. 38. The method of claim 37, wherein removing the high surface area to volume ratio material layer in step (d) is performed by chemical, thermal, mechanical, or combinations thereof. 38. The method of claim 37, further comprising depositing on the second substrate at least one component selected from the group comprising a device, a coating structure, a coating, and a mixture thereof. 53. The method of claim 51, further comprising depositing at least one coating on the at least one component selected from the group comprising a device, a coating structure, a coating, and a mixture thereof. The apparatus of claim 52, wherein the at least one coating on the at least one component selected from the group comprising a device, a coating structure, a coating, and a mixture thereof. After the selected at least one component is separated from the substrate in step (d), it is disposed on a second substrate. The method of claim 51, wherein the second substrate is flexible, curved, irregularly shaped, or both. 55. The method of claim 54, wherein the second substrate is an organic material. 53. The device of claim 51, wherein the at least one component selected from the group comprising a device, a coating structure, a coating, and a mixture thereof, disposed on the second substrate, comprises a transistor, diode, display, sensor, actuator, detector, A method of delivering a material system for manufacturing a thin film system selected from the group consisting of acoustic devices or arrays, microelectromechanical devices, fuel cells, biological systems or arrays, and solar cells. In a method for creating a cavity structure, a) forming a high surface area to volume ratio material layer on the substrate; b) forming at least one layer on said high surface area to volume ratio material layer; And c) removing a portion of the high surface area to volume ratio material layer to create a cavity structure Cavity structure generation method comprising a. 59. The method of claim 57, wherein the high surface area to volume ratio material layer is a columner void layer. 59. The method of claim 58, wherein the columner void layer is deposited. The method of claim 58, The columner void layer is a nanounit composite, (a) a plurality of uniform substantially non-contacting columnar units penetrating successive voids, the units having adjustable regular spacing, adjustable uniform height, and adjustable variable diameter, (b) the plurality of basic columnar units are constantly oriented and disposed on the substrate. 58. The method of claim 57, wherein the substrate is selected from the group comprising silicon wafers, quartz, glass, organic materials, polymers, ceramics, semiconductors, metals, and mixtures thereof. 58. The method of claim 57, wherein the high surface area to volume ratio material layer deposited on the substrate in step (a) is patterned continuously. 59. The method of claim 57, wherein the high surface area to volume ratio material layer is patterned using soft masking material, hard masking material, or a combination thereof. 59. The method of claim 57, wherein removing a portion of the high surface area to volume ratio material layer in step (c) is performed by chemical, mechanical, or combinations thereof. 59. The method of claim 57, wherein removing a portion of the high surface area to volume ratio material layer in step (c) also removes a portion of the substrate. 58. The method of claim 57, wherein the at least one layer on the high surface area to volume ratio material layer comprises a chemically active material, polymer, insulator, nitride, oxide, piezoelectric, ferromagnetic, pyroelectric, metal, biological material, and semiconductor. Cavity structure creation method, which is one material selected from the group. 58. The method of claim 57, further comprising adding gas or liquid to the cavity structure after the high surface area to volume ratio material layer is removed in step (c). 59. The method of claim 57, further comprising creating a through hole through the at least one layer that accesses the high surface area to volume ratio material layer. 58. The method of claim 57, further comprising blocking the through hole by forming an additional layer on the substrate after removing the high surface area to volume ratio material layer of step (c). 59. The method of claim 57, wherein the height of the cavity structure is at least 10 nm. 59. The method of claim 57, wherein the width of the cavity structure is at least about 10 nm. 59. The method of claim 57, wherein the creation of the cavity structure comprises MEMS; Field emission sources; Bolometer structure; Accelerometer; Optical trapping; Resonance; Electric field shaping; send; Acoustic trapping; Display micro-mirror formation; Biomedical and medical devices; Sorting structures and proteomic sorting for functions such as DNA; Cell nutrients, growth control or both; Capillary function; Gettering regions for silicon on solid phase crystallization or insulating structures; Interlayer stress control; Optical waveguide and optical device applications; Fluidic channels, chromatography, chemical reagents / product transport for electrical, chemical and electrochemical sensors; Fuel cells; display; And a method for creating a cavity structure that provides for the manufacture of a use selected from the group comprising molecular sorting. In the method of creating a cavity structure in a substrate, a) forming at least one stencil layer on the substrate; b) removing a portion of the stencil layer to create an exposed portion of the substrate; c) forming a high surface area to volume ratio material layer on the stencil layer and the portion of the exposed substrate; d) lifting off a portion of the stencil layer to remove a portion of the high surface area to volume ratio material layer formed thereon and leaving a portion of the high surface area to volume ratio material layer formed on the exposed portion; e) forming at least one layer on said substrate and said high surface area to volume ratio material layer; And f) removing the high surface area to volume ratio material layer to form a cavity structure Cavity structure generation method comprising a. 74. The method of claim 73 wherein the stencil layer comprises one material selected from the group comprising photoresist, nitride, oxide, metal, polymer, dielectric, and mixtures thereof. 74. The method of claim 73, wherein the substrate is selected from the group comprising silicon wafers, quartz, glass, organic materials, polymers, ceramics, semiconductors, metals, insulators, and mixtures thereof. 74. The method of claim 73, wherein removing the stencil layer in step (b) is performed using one technique selected from the group comprising melting, dry etching, wet etching, and combinations thereof. . 74. The method of claim 73 wherein the high surface area to volume ratio material layer is deposited. 74. The method of claim 73 wherein the high surface area to volume ratio material is a columner void layer. The method of claim 78, The columner void layer is a nanounit mixture, (a) a plurality of uniform substantially non-contacting columnar units penetrating successive voids, said units having an adjustable regular spacing, an adjustable uniform height, and an adjustable variable diameter; (b) the plurality of basic columnar units are constantly oriented and disposed on the substrate. 74. The method of claim 73 wherein the step of lifting off the stencil layer in step (d) is performed by melting, etching, or a combination thereof. 74. The method of claim 73, wherein the at least one layer is one material selected from the group consisting of chemically active materials, polymers, insulators, nitrides, oxides, piezoelectrics, ferromagnetics, metals, pyroelectrics, biological materials, and semiconductors. How to create a cavity structure. 74. The method of claim 73, wherein (f) removing the high surface area to volume ratio material layer is performed by chemical, mechanical, or combinations thereof. 74. The method of claim 73, further comprising creating a through hole that accesses the high surface area to volume ratio material layer. 74. The method of claim 73, further comprising adding gas or liquid to the cavity structure after the high surface area to volume ratio material layer is removed in step (f). 84. The method of claim 83, further comprising depositing an additional layer, wherein the additional layer blocks the through hole. 86. The method of claim 85, wherein the additional layer is one material selected from the group consisting of dielectrics, polymers, metals, photoresists, nitrides, oxides, biological materials, semiconductors and insulator materials, and mixtures thereof. 74. The method of claim 73, wherein the cavity structure has a height of at least 10 nm. 74. The method of claim 73, wherein the cavity structure has a width of at least 10 nm. 74. The method of claim 73, wherein the cavity structure is formed of: MEMS; Field emission sources; Bolometer structure; Accelerometer; Optical trapping; Resonance; Electric field shaping; send; Acoustic trapping; Display micro-mirror formation; Biomedical and medical devices; Sorting structures and proteomic sorting for functions such as DNA; Cell nutrients, growth control or both; Capillary function; Gettering regions for silicon on solid phase crystallization or insulating structures; Interlayer stress control; Optical waveguide and optical device applications; Fluidic channels, chromatography, chemical reagents / product transport for electrical, chemical and electrochemical sensors; Fuel cells; display; And a method for creating a cavity structure that provides manufacture by use selected from the group comprising molecular sorting. A method of creating at least one control contact region between a first and a second material system on a substrate, a) forming a first material system on the substrate; b) etching a portion of the first material system; c) forming a high surface area to volume ratio material layer on the first material system and the substrate; d) removing a portion of the high surface area to volume ratio material layer to expose a portion of the first material system; e) forming a second material system on the high surface area to volume ratio material layer and the exposed portion of the first material system such that a portion of the second material system is in contact with the portion of the first material system; And f) freeing a portion between the first and second material systems while maintaining the at least one contact area by removing the high surface area to volume ratio material layer. Control contact area generation method comprising a. 91. The system of claim 90, wherein the first material system is from a group comprising metals, semiconductors, chemically active materials, polymers, insulators, nitrides, oxides, piezoelectrics, ferromagnetics, pyroelectrics, biological materials, organic materials, and combinations thereof. The method of generating the selected control contact region. 91. The method of claim 90, wherein the substrate is one material selected from the group consisting of silicon wafers, quartz, glass, organic materials, polymers, ceramics, semiconductors, metals, and mixtures thereof. 91. The method of claim 90, wherein the second material system is from a group comprising metals, semiconductors, chemically active materials, polymers, insulators, nitrides, oxides, piezoelectrics, ferromagnetics, pyroelectrics, biological materials, organic materials, and combinations thereof. The method of generating the selected control contact region. 91. The method of claim 90, wherein the removal of the high surface area to volume ratio material layer is performed by chemical, physical, or combinations thereof. 95. The method of claim 94, wherein the removal of said high surface area to volume ratio material layer by chemical means has an etch rate of 25 micrometers or less per minute. 91. The system of claim 90, wherein the creation of at least one contact region between the first and second material systems comprises a MEMS device, a cantilever structure, a micro-switch structure, a micro-mirror structure, an actuator, a field emission structure, a bolometer structure A method of creating a controlled contact region providing manufacturing of a structure selected from the group comprising accelerometers, biomedical and medical devices, sorting and attachment structures, and electrochemical and electrochemical sensors. A method of making a chemical transport / chemical catalyst assembly, Forming a channel within or over a substrate comprising a reactant, an article, or both, wherein the channel and the catalyst structure are formed by claim 1. In the method of manufacturing a fuel cell, a) depositing a masking layer on the substrate; b) using a stencil layer to define the location of channel regions in the masking layer; c) covering said stencil layer of said defined and adjacent regions in said masking layer with a sacrificial layer material; d) lifting off the sacrificial layer material in the stencil coating area by dissolving or etching the stencil layer; e) depositing an anode material on the entire resulting surface for the layer formed in step (d); f) patterning the anode material to form an anode; g) depositing an electrolyte on the resulting surface for the layer formed in step (d); h) employing means for accessing said sacrificial layer; i) using means to etch or dissolve the sacrificial layer in the region to be the channel; j) using these regions of the sacrificial material removed as defining regions for subsequent or successive etching or dissolution of the underlying material to create the channel comprising fuel, oxidant or both; k) depositing and patterning the cathode material on the resulting surface for the layer formed in step (d); And l) depositing and patterning interconnects and contacts on the resulting surface for the layer formed in step (d) to provide electrical current flow and power generation for the fuel cell. Fuel cell manufacturing method comprising a. The method of claim 1, wherein the high surface area to volume ratio material performs a function of attaching, sorting, fixing, or a combination thereof.