KR20020069448A - Apparatus for Fast Packet Bus - Google Patents

Abstract

PURPOSE: A fast packet bus apparatus is provided to prevent the number of packet links from being restricted to the internal performance of a packet bus by realizing a fast packet bus and to minimize an instantaneous bottle neck state at an FPH(Frame relay and Packet Hardware) through a node that can temporarily store data. CONSTITUTION: A fast packet bus block(100) consists of a CIP(Communication Interworking Processor) block and CI(Communication Interworking) block(120). The CIP block, composed of a CIMA(Communication Interworking Maintenance Assembly) PBA, executes the management of the packet bus and the maintenance of the CI block(120). The CI block(120), composed of a CINA(Communication Interworking Node Assembly) PBA, provides data transmission paths generated between FPHs(200). The CI block(120) is divided into a node interface part and a data bus interface part. The node interface part transmits and receives data with FPHs(200) in a point-to-point method. The data bus interface part executes inter-CI switching and processing for the data received and stored in nodes(120).

Description

Fast Packet Bus Unit {Apparatus for Fast Packet Bus}

The present invention relates to a high speed packet bus device in an electronic switching system, and more particularly, to frame relay / packet hardware (FPH) for providing frame relay and packet services in an electronic switching system. The present invention relates to a structure of an apparatus that provides a transmission path of packet data generated between blocks, thereby showing a more improved characteristic on a packet bus.

The frame relay / packet hardware block (hereinafter abbreviated as FPH) block is a hardware block accommodated to provide frame relay / packet service through B and D channels to ISDN subscribers, and provides level 2 terminal function among related protocols. It performs the matching function inside the system.

In addition, FPH provides interworking with internal time-switching interworking to provide Packet Switched Public Data Network (PSPDN) interworking via frame relay or the X.75 protocol.

1 is a block diagram illustrating a conventional packet bus structure.

The conventional system is composed of a packet handler module (PHM: 410) consisting of three PBA, as shown in Figure 1 to provide 120 packet links per packet handler module 410, ASS-P Up to eight packet handler modules 410 may be mounted per system, providing up to 960 packet links per system.

The packet bus 400 is configured in the system for packet data transmission between the packet handler modules 410, which is formed in the form of a serial bus 420 having a unidirectional 10 Mbps.

However, in the case of the point-to-multi scheme in which a plurality of packet links are established between up to eight packet handler modules 410, when a maximum B and D channel is accommodated per packet handler module 410, data of up to 2 Mbps is bidirectionally transmitted. The handler module 410 should perform the transmission. Therefore, a bottleneck may occur in the packet bus 400 having the maximum unidirectional 10Mbps performance.

When eight packet handler modules 410 accept both ISDN B and D channels in order to establish the maximum possible 960 packet links, one packet handler module 410 transmits 2 Mbps of data in one direction and thus 2Mbps × 8 PHM = This results in a load of 16 Mbps being applied to the packet bus 400.

Even arithmetic calculations, the 10 Mbps limit performance packet bus 400 cannot handle data of up to 16 Mbps. Considering the overhead occurring inside the actual packet bus 400, only about 50% of packet links can be accommodated. In addition, as the number of Internet users increases, the number of packet links to be accommodated per system is increasing, which may be insufficient for 960 packet links.

Thus, instead of the packet handler module 410 accommodating 120 packet links, an FPH capable of accommodating 384 packet / frame relay links has been proposed as an alternative, and up to four FPHs may be mounted in the ASS-P. Therefore, the maximum number of 384 × 4 FPH = 1536 packet links should be increased, and the packet data to be processed on the packet bus has also increased significantly, causing a bottleneck in the packet bus as a serious problem.

As shown in FIG. 1, the conventional packet bus 400 is configured only in the form of a round robin unidirectional bus 420, so that only one packet handler module 410 has the right to occupy the bus by bus arbitration. Transmission is possible, so that the remaining packet handler modules receive their data in the receive mode.

Therefore, a problem arises in that the performance of the system is limited to the performance of the 10Mbps unidirectional bus 420.

The present invention has been devised to solve these problems, and realizes a high speed packet bus so that the number of packet links accommodated in the system is not limited to the internal performance of the packet bus, and can be stored in the FPH through a node capable of temporarily storing data. The goal is to provide a high-speed packet bus structure in an electronic switchboard that minimizes the instantaneous bottlenecks of the system.

1 is a block diagram illustrating a conventional packet bus structure.

2 is a block diagram illustrating a high speed packet bus apparatus according to a preferred embodiment of the present invention.

3 is a block diagram illustrating an operation of a communication interworking subblock according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: high speed packet bus 110: communication interworking processor

120: communication interworking 121: node

122: data bus 123: bus arbiter

124: unit to bus memory 125: bus to unit memory

126: frame address check circuit

200: Frame Relay / Packet Hardware (FPH)

In order to achieve the above object, the present invention provides a frame packet and a high-speed packet bus structure of an electronic switching system interworking with an FPH block providing a protocol of a level 2 terminal function as a hardware block for providing a packet service. Communication Interworking (CI) block that performs packet data processing, and Communication Interworking Processor (CIP) that manages packet buses. Communication Interworking Block consists of FPH and Point-to-Point. And a node matching unit for transmitting and receiving data in a (Point-to-Point) manner, and an internal data bus (D-Bus) matching unit for exchanging data stored in the node between communication interworking blocks.

The node performs the bus request and the seizure so that the data received from the FPH can be transmitted on the data bus. Temporary data storage is performed to prevent overflow.

The internal data bus is a round robin unidirectional bus, so only nodes that have the right to occupy can transfer data onto the data bus.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In addition, it should be noted that the same reference numerals are given to the same components, although belonging to different drawings for convenience of understanding.

2 is a block diagram illustrating a high speed packet bus apparatus according to a preferred embodiment of the present invention.

The high speed packet bus block 100 is composed of a communication interworking processor (CIP) block 110 and a communication interworking (CI) block 120 as a sub-block, as shown in FIG.

The communication interworking processor block 110 is composed of a communication interworking maintenance assembly (CIMA) PBA and performs management of packet buses and maintenance of the communication interworking blocks 120.

The communication interworking block 120 is composed of a communication interworking node interface board assembly (CINA) PBA, and provides a data transmission path generated between the FPHs 200.

The packet data processing of the actual packet bus 100 is involved in a communication interworking subblock, and the communication interworking subblock largely includes a node 121 matching unit for transmitting and receiving data with the FPH 200 in a point-to-point manner, and a node ( The data stored in 121 is divided into a matching part of an internal data bus 122 that exchanges and stores the received data with the communication interworking 120.

Only the node 121 that has acquired the right to occupy the internal data bus 122 as a round-robin unidirectional bus can transmit data on the data bus 122.

Preferably, a 25 MHz clock is used for a 16 bit parallel bus, resulting in a bus performance of 16 bits x 25 MHz = 400 Mbps.

The node 121 performs a bus request and occupancy so as to transmit data received from the FPH 200 on the data bus 122, and transmits and receives data of about 10 Mbps (1-bit serial communication) with the FPH 200 in both directions. Even if a temporary storage function to prevent the overflow until the bus occupied or received from the bus and transmitted to the FPH (200).

Preferably, node 121 temporarily stores data using a First In First Out (FIFO) of 32K bytes in both directions.

The actual communication interworking subblock 120 includes four nodes that function independently of each other and constitute a CINA PBA. Therefore, in order to accommodate four FPH blocks 200, the packet bus 100 may be configured with one CINA. In addition, in consideration of redundancy, in order to accommodate four FPH blocks 200, the packet bus 100 is preferably configured with two CIMAs, two CINAs, and one CIBB.

3 is a block diagram illustrating an operation of a communication interworking subblock according to an exemplary embodiment of the present invention.

The communication interworking subblock has a node and data bus matching structure as shown in FIG. 3 and the four nodes 121 operate independently in the CINA PBA.

The node 121 transmits data serially received from the external FPH 200 to the data bus 122 in the packet bus 100 in parallel with a unit to bus (UB) channel, and the data bus 122 Data is transmitted and received with the FPH 200 through a BU (Bus to Unit) channel that serially transmits data received in parallel to the FPH 200, and has independent FIFO memories 124 and 125, respectively.

The UB channel operates by receiving URXDATA, which is data from the external FPH 200, in accordance with the reception clock URXCLK and storing the URXDATA in the FIFO 124.

Data can be recognized as the start and end of valid data by a flag in the form of a high level data link control (HDLC) format. HDLC is the transport protocol used in the data link layer, which is the second layer of the OSI 7 layer model of data communication (ISO standard), and is mainly used in X.25 packet switching networks. In HDLC, data is made up of units called frames. The frame is sent over the network, verifying that it arrived successfully at the destination. The HDLC protocol embeds information within the data frame to control data flow and correct errors.

On the other hand, the transmission scheme is a full duplex point-to-point form, and if the start and end of the received data is valid data in a flag form, it is stored in the FIFO 124 unconditionally. In other words, regardless of the content of the data, if it meets the HDLC format, the data is received.

If a frame of data is stored in the FIFO 124 by the start flag and the end flag, and the FIFO 124 is not empty, the node requests the bus occupied by the data bus arbiter 123. Transition to the state.

When the bus arbitration circuit 123 acquires the bus occupancy right and receives the BRXALW [0..3] signal as shown in FIG. 3, the 16-bit parallel data is transmitted on the data bus 122. Here, BTXALW [0..3] represents the signals BTXALW0, BTXALW1, BTXALW2, and BTXALW3 at once, and is independently connected to four nodes 121 in the CINA PBA.

The data bus 122 is a unidirectional, half duplex, multi-drop type in which a plurality of nodes are commonly connected to each other, so that only one node may occupy the data bus 122 at one time. Bus arbitration is necessary to prevent collisions.

At this time, the bus arbitration is to determine the order (Arbitration) for the occupancy for each node, the node 121 is given the opportunity to occupy the bus once without priorities sequentially by the round robin method.

The synchronization signal and clock for bus arbitration are FRS * and ASTCLK shown in FIG. 3, and each node is synchronized by the FRS * signal, and a new bus cycle starts as ASTCLK is counted.

Although the bus occupancy order is determined, the 16-bit parallel transmission of data on the data bus 122 is performed by occupying the bus only when there is actual data to be transmitted.

D0-D16 in FIG. 3 is 17 bits as data, but D16 is not an actual data bit but a parity bit for determining a data transmission error.

When occupying a bus, the node sends a bus occupancy signal on the data bus 122 to inform all of the bus occupancy state so that other nodes do not occupy the bus.

In the case of the BU channel, all nodes not occupying the data bus 122 may receive all data on the bus in a reception mode.

Unlike the UB channel, all data are not received unconditionally, but only data selectively transmitted to the FPH 200 connected to the corresponding node is selectively received. As shown in FIG. 3, the reception permission signal is received by the Frame Address Checker circuit 126 in BREXEN [0..3] *.

The BRXEN [0..3] signal, like BRXALW [0..3], also represents BRXEN0 * through BRXEN3 *. The frame address check circuit 126 refers to the address field in the data of the data bus 122 in the HDLC format and determines whether to receive the corresponding data and informs the node with a BRXEN [0..3] * signal.

The connection between the node 121 and the FPH 200 is not variable but is a fixed path in the system configuration. Each node 121 is matched one-to-one with an address of the corresponding FPH 200.

The NODE [0..3] ADR signal is set in the frame address check circuit 126 upon CINA initialization with a matched address. The NODE [0..3] ADR signal also indicates NODE0ADR, NODE1ADR, NODE2ADR, and NODE3ADR. If the set NODE [0..3] ADR value and the address field value of the data received on the bus coincide, the BRXEN [0..3] * signal is transmitted to the node. When the node receives the BREXEN [0..3] * signal, the node receives 16-bit data on the data bus 122 and stores it first in the BU FIFO 125. The reason for using the FIFO is that the data bus 122 has a 400 Mbps. This is to prevent overflow due to inconsistency with the external matching speed of about 10Mbps.

In the BU channel, if there is data stored in the BU FIFO 125, it is read by the FIFO 125 in accordance with the transmission clock of the FPH 200, and then transmitted to the UTXDATA.

As such, the high-speed packet bus 100 has improved the performance by dramatically improving the multi-drop bus structure from the serial data bus to the 16-bit parallel bus structure, and also converting the serial data at the time of FPH 200 matching. To this end, FIFO memories 124 and 125, which are temporary storages, are provided in each node 121 so as to prevent bottlenecks and overflows in a specific portion.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will appreciate that the present invention may be modified without departing from the spirit and scope of the invention as defined in the appended claims. It will be appreciated that modifications or variations may be made. Therefore, changes in the future embodiments of the present invention will not be able to escape the technology of the present invention.

As described above, according to the present invention, the conventional problem that the number of packet links accommodated in the system is limited by the realization of the high speed packet bus is limited to the internal performance of the packet bus, and through a node having a first-in first-out (FIFO) memory. By preventing the bottleneck of the instantaneous data, there is an advantage that can provide a stable service by removing the instability caused by data loss.

Claims (9)

In the packet bus device of the electronic switchboard which interoperates with a Frame Relay / Packet Hardware (FPH) block providing a protocol of a level 2 terminal function as a hardware block providing a frame relay and a packet service, A communication interworking (CI) block that provides a data transmission path generated between the frame relay / packet hardware and performs packet data transmission processing in the packet bus; A communication interworking processor (CIP) for performing management of the communication interworking block; The communication interworking block, A node matching unit for transmitting and receiving data with the frame relay / packet hardware in a point-to-point manner; And an internal data bus (D-Bus) matching unit configured to exchange data received and stored at a node of the node matching unit between the communication interworking blocks. 2. The node of claim 1, wherein the node performs a bus request and occupies to transmit data received from the frame relay / packet hardware on the data bus, and receives data on and occupies the frame relay / packet hardware. A high speed packet bus apparatus, comprising: a memory that temporarily stores data to prevent overflow until transmission to packet hardware. 3. The high speed packet bus apparatus of claim 2, wherein the memory of the node is a first in first out (FIFO) memory having a size of 32K bytes in both directions. The high speed packet apparatus as claimed in claim 1, wherein the data bus is a round robin unidirectional bus and transmits only data obtained by the node. 5. The high speed packet apparatus as claimed in claim 4, wherein the data bus uses a 25 MHz clock and is a 16-bit parallel bus having a bus performance of 400 Mbps. The method of claim 1 or 5, wherein the data transmission channel between the node and the data bus, A unit to bus (UB) channel for serially transmitting data serially received from the frame relay / packet hardware to a data bus inside the packet bus; And a bus to unit (BU) channel for serially transmitting data received in parallel on the data bus in 16 bits to the frame relay / packet hardware. 7. The high speed packet apparatus of claim 6, wherein the data transmitted through the unit-to-bus channel is in the form of a high level data link control (HDLC) format. 7. The high speed packet apparatus according to claim 6, wherein the unit-to-bus channel transmission method is a full duplex point-to-point type. 7. The high speed packet apparatus of claim 6, wherein the unit-to-bus channel selectively receives data transmitted to frame relay / packet hardware connected to the node.