KR20020056698A - Pixel structure of fringe field switching mode liquid crystal display - Google Patents
Pixel structure of fringe field switching mode liquid crystal display Download PDFInfo
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- 239000010410 layer Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
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- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/40—Arrangements for improving the aperture ratio
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Abstract
본 발명은 개구율에 영향을 주지않는 게이트 실드바 위치에 캐패시턴스를 형성하고 공통전극에서 실드바의 모양을 변화시켜서 GCS(Gate Common Short)를 감소시킬 수 있도록 된 에프에프에스 모드 액정표시소자의 픽셀 구조에 관한 것으로, 게이트 라인, 공통라인과 제 1 및 제 2 ITO 전극을 포함하는 에프에프에스 모드 또는 평면 스위칭(InPlane Switching)모드 액정표시소자의 픽셀구조에 있어서, 픽셀 전극을 가운데 위치에 상부 ITO 전극의 폭보다 작게 형성된 공통전극과, 소스/드레인 층으로 게이트와 가깝게 형성된 실드바와, 상기 공통 전극과 픽셀 전극이 서로 돌출되게 형성하여 오버랩 면적을 증가시키고, 동시에 상기 실드 바가 있는 좌우 양쪽으로 형성한 Cst로 이루어진 것을 특징으로 하여 TFT LCD의 평면 스위칭(InPlane Switching), FFS 구조에서 공통 전극이 픽셀 가운데 위치하는 경우 Cst를 형성하기 위해 초래되는 개구율의 감소가 줄어들어 휘도의 저하가 줄어드는 효과가 있다.The present invention relates to a pixel structure of a FPS mode liquid crystal display device capable of reducing a gate common short (GCS) by forming a capacitance at a gate shield bar position that does not affect the aperture ratio and changing the shape of the shield bar at the common electrode. In a pixel structure of an FPS mode or an InPlane Switching mode liquid crystal display device including a gate line, a common line, and first and second ITO electrodes, the pixel electrode is positioned at a center position of the width of the upper ITO electrode. A small common electrode, a shield bar formed close to the gate by a source / drain layer, and the common electrode and the pixel electrode are formed to protrude from each other to increase an overlap area, and at the same time, Cst formed on both sides of the shield bar. InPlane Switching of TFT LCD, common electrode in FFS structure When the center position, the effect is reduced by reducing the decrease in the aperture ratio decrease in luminance caused to form Cst.
Description
본 발명은 에프에프에스 모드 액정표시소자의 픽셀 구조에 관한 것으로, 보다 상세하게는 개구율에 영향을 주지않는 게이트 실드바 위치에 캐패시턴스를 형성하고 공통전극에서 실드바의 모양을 변화시켜서 GCS(Gate Common Short)를 감소시킬 수 있도록 된 에프에프에스 모드 액정표시소자의 픽셀 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pixel structure of a FPS mode liquid crystal display device, and more particularly, to form a capacitance at a gate shield bar position that does not affect the aperture ratio, and to change the shape of the shield bar at the common electrode to achieve a GCS The pixel structure of the FSF mode liquid crystal display device can be reduced.
본 발명은 LCD(Liquid Crystal Display) 분야에 적용될 수 있는 것으로 FFS(Fringe Field Switch)구조에서 GCS(Gate Common Short)를 줄이고자 공통 전극을 픽셀 가운데 위치하는 방법은 휘도 저하가 유발되는 문제점이 있었다.The present invention can be applied to the field of LCD (Liquid Crystal Display), the method of positioning the common electrode in the center of the pixel to reduce the gate common short (GCS) in the FFS (Fringe Field Switch) structure has a problem that the luminance is caused.
도 1 은 종래 에프에프에스 모드 액정표시소자의 픽셀 구조를 나타낸 평면도로서, 이에 도시한 바와 같이, FFS(Fringe Field Switching)구조는 기존의 같은 층으로 게이트와 공통 전극이 인접한 경우는 공정 불량에 의한 GCS(Gate Common Short)가 많이 발생하므로 이를 개선하기 위해 공통 전극(14)을 픽셀 가운데 위치시킨 기술을 나타낸다.FIG. 1 is a plan view showing a pixel structure of a conventional FPS mode liquid crystal display device. As shown in FIG. 1, a FFS (Fringe Field Switching) structure has a conventional same layer and a GCS due to a process defect when a gate and a common electrode are adjacent to each other. Since a lot (Gate Common Short) occurs, the common electrode 14 is positioned in the center of the pixel to improve this.
그러나, 이 기술에서는 Cst를 형성하기 위해서 공통전극(14)과 픽셀 전극(24)이 오버랩(overlap)되는 면적이 필요하므로 픽셀 가운데 금속 전극과 픽셀 전극간이 중복되어 빛이 투과되지 못하는 영역이 존재하여 휘도의 감소가 불가피하게 되는 문제점 있었다. 또한 데이터 신호 전압에 의해 빛샘 현상을 막기 위한 게이트 실드 바(shield bar)(26)가 기존의 FFS구조에서와 마찬가지로 게이트 전극과 가깝기 때문에 게이트 남김(remain)으로 인한 GCS가 발생될 확률이 매우 높은 단점을 가지고 있다.However, in this technology, since the common electrode 14 and the pixel electrode 24 overlap with each other in order to form Cst, there is an area where the light cannot be transmitted because the metal electrode and the pixel electrode overlap between the pixels. There was a problem that a decrease in luminance is inevitable. In addition, since the gate shield bar 26 for preventing light leakage due to the data signal voltage is close to the gate electrode as in the conventional FFS structure, there is a high probability of generating GCS due to the gate remaining. Have
본 발명의 목적은 상기한 바와 같은 종래 액정표시장치에서의 문제점을 개선하기 위해 안출한 것으로, 개구율에 영향을 주지않는 게이트 실드바 위치에 캐패시턴스를 형성하고 공통전극에서 실드바의 모양을 변화시켜서 GCS(Gate Common Short)를 감소시킬 수 있도록 에프에프에스 모드 액정표시소자의 픽셀 구조를 제공하는데 있다.An object of the present invention is to solve the problems of the conventional liquid crystal display device as described above, by forming a capacitance at the gate shield bar position does not affect the aperture ratio and by changing the shape of the shield bar in the common electrode GCS ( In order to reduce the gate common short), it is to provide a pixel structure of a fs mode liquid crystal display device.
도 1 은 종래 에프에프에스 모드 액정표시소자의 픽셀 구조를 나타낸 평면도.1 is a plan view showing a pixel structure of a conventional fs mode liquid crystal display device.
도 2 는 에프에프에스 모드 액정표시소자의 TFT 및 픽셀영역을 나타낸 단면도.Fig. 2 is a cross-sectional view showing a TFT and a pixel region of a fs mode liquid crystal display device.
도 3 은 본 발명에 따른 에프에프에스 모드 액정표시소자의 픽셀 구조를 나타낸 평면도이다.3 is a plan view showing a pixel structure of a F-S mode liquid crystal display device according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10 : 게이트 라인 12 : 데이터 라인10 gate line 12 data line
50 : 홀 126 : 실드 바50: hole 126: shield bar
140 : 공통라인 142 : 공통전극140: common line 142: common electrode
상기한 바와 같은 목적을 달성하기 위한 본 발명의 바람직한 일실시예에 따르면, 게이트 라인, 공통라인과 제 1 및 제 2 ITO 전극을 포함하는 에프에프에스 모드 또는 평면 스위칭(InPlane Switching)모드 액정표시소자의 픽셀구조에 있어서,According to a preferred embodiment of the present invention for achieving the above object, the FPS mode or InPlane Switching mode of the liquid crystal display device including a gate line, a common line and the first and second ITO electrode In the pixel structure,
픽셀 전극을 가운데 위치에 상부 ITO 전극의 폭보다 작게 형성된 공통전극과, 소스/드레인 층으로 게이트와 가깝게 형성된 실드바와, 상기 공통 전극과 픽셀 전극이 서로 돌출되게 형성하여 오버랩 면적을 증가시키고, 동시에 상기 실드 바가 있는 좌우 양쪽으로 형성한 Cst로 이루어진 것을 특징으로 하는 에프에프에스 모드 액정표시소자의 픽셀구조가 제공된다.A common electrode having a pixel electrode smaller than the width of the upper ITO electrode at a central position, a shield bar formed close to the gate by a source / drain layer, and the common electrode and the pixel electrode are formed to protrude from each other to increase an overlap area, and simultaneously Provided is a pixel structure of a fs mode liquid crystal display device comprising Cst formed on both sides of a shield bar.
또한 본 발명에 있어서, 상기 공통 전극은 상기 게이트와 떨어져있고, 상기 실드 바의 모양은 ㅁ,ㅇ,ㅍ자 등으로 넓은 패턴으로 형성된 것을 특징으로 한다.In addition, in the present invention, the common electrode is separated from the gate, the shield bar is characterized in that formed in a wide pattern, e.
또한 본 발명에 있어서, 절연막 사이에 공통 전극과 데이터 라인과의 오버랩 되어 형성된 캐패시턴스 값을 줄이기 위해 상기 공통 전극의 모양이 가운데가 박스 모양으로 홀이 형성되어 면적을 감소시킨 구조를 갖는 것을 특징으로 한다.In addition, in the present invention, in order to reduce the capacitance value formed by overlapping the common electrode and the data line between the insulating film, the shape of the common electrode has a structure in which a hole is formed in the center of the box to reduce the area. .
본 발명에 따른 에프에프에스 모드 액정표시소자의 픽셀 구조의 특징을 열거하면, 첫째로, Cst형성 위치를 변화시켜 공통 전극이 픽셀 가운데 위치한 경우 개구율이 감소되어 이로 인한 휘도 저하를 줄이고자 개구율에 영향을 주지 않는 게이트 실드 바 위치에 캐패시턴스를 형성하였다.When enumerating the characteristics of the pixel structure of the fs mode liquid crystal display device according to the present invention, first, the aperture ratio is reduced when the common electrode is located in the pixel by changing the position of the Cst formation, thereby affecting the aperture ratio in order to reduce the luminance decrease. Capacitance was formed at the gate shield bar position, which is not known.
둘째로, 공통 전극에서 실드바의 모양을 변화시켜서 GCS를 줄였다.Second, GCS was reduced by changing the shape of the shield bar at the common electrode.
셋째로, 게이트 바가 짧기 때문에 실드 바 역할을 충분히 하지 못하므로 이를 보안하기 위해서 플로팅된 소스/드레인 금속을 사용하여 빛샘 방지용 실드 바를 형성하였다.Third, since the gate bar is short enough to serve as a shield bar, a floating bar / drain metal is used to form a shield bar for preventing light leakage.
넷째로, 공통전극과 데이터 라인과의 오버랩을 감소시켜서 데이터 라인에 발생되는 캐패시턴스 값을 줄였다.Fourth, the capacitance value generated in the data line was reduced by reducing the overlap between the common electrode and the data line.
도 2 는 에프에프에스 모드 액정표시소자의 TFT 및 픽셀영역을 나타낸 단면도로서, 이에 도시한 바와 같이, 유리기판(1)상에 형성된 게이트 금속(2)과 제1 절연층인 SiONx층(3)과, 제 2 절연층인 SiNx층(4)과, a-Si층(5) 및 n+a-Si층(6)이 있고, 소스/드레인 전극층(7)이 형성되어 있다. 참고부호 8은 패시베이션층으로서 이와 같이 하여 박막 트랜지스터 부분이 형성된다. 또한 공통 데이터 라인 부분은 유리 기판(1)상에 형성된 제 1 ITO(Indium Tin Oxide)(22)과, 공통 게이트 라인(14)이 형성되고 그 상부에 SiONx층(3)이 형성되고, 이후 실드바(26)가 형성되고, 제 2 ITO층(24)가 형성되어 있다. 이 공통 데이터 라인부분이 본 발명과 관련된 부분이다.FIG. 2 is a cross-sectional view illustrating TFTs and pixel regions of the FSF mode liquid crystal display device. As shown therein, a gate metal 2 formed on the glass substrate 1 and a SiONx layer 3 serving as a first insulating layer are shown. And a SiNx layer 4 as a second insulating layer, an a-Si layer 5 and an n + a-Si layer 6, and a source / drain electrode layer 7 is formed. Reference numeral 8 denotes a passivation layer, in which a thin film transistor portion is formed. In addition, the common data line portion includes a first indium tin oxide (ITO) 22 formed on the glass substrate 1, a common gate line 14, and a SiONx layer 3 formed thereon, and then a shield. The bar 26 is formed, and the second ITO layer 24 is formed. This common data line portion is a portion related to the present invention.
도 3 은 본 발명에 따른 에프에프에스 모드 액정표시소자의 픽셀 구조를 나타낸 평면도로서, 도 1 과 유사한 도면이다.FIG. 3 is a plan view illustrating a pixel structure of a F-S mode liquid crystal display device according to the present invention, and is similar to FIG. 1.
첫째로 본 발명에서는 공통전극은 데이터 전압의 레퍼런스(reference) 역할을 하므로 DC 바이어스가 인가되어 저항값에 크게 영향을 받지 않기 때문에 공통 전극(142)의 폭을 줄일 수 있다. 반면에 면적이 작아 충전 용량이 부족하게 된다. 이를 보안하여 충분히 큰 Cst 용량을 얻기 위해서 일반적으로 빛샘을 막기 위해 사용되는 데이터 라인(12) 옆에 있는 실드 바(126) 위치에 픽셀 전극(24)과 공통 전극 라인(140) 사이에 오버랩되는 면적을 증가시켜 Cst를 형성하여 개구율의 감소를 보안할 수 있도록 하였다.First, in the present invention, since the common electrode serves as a reference of the data voltage, the width of the common electrode 142 may be reduced because a DC bias is not applied and thus is not significantly affected by the resistance value. On the other hand, the small area leads to insufficient charging capacity. The area overlapping between the pixel electrode 24 and the common electrode line 140 at the shield bar 126 position next to the data line 12 which is generally used to prevent light leakage in order to secure this to obtain a sufficiently large Cst capacitance. Was increased to form Cst to secure the reduction of the aperture ratio.
두 번째로 게이트 박막 형성시 형성하는 금속 실드 바는 일반적으로 데이터 전압에 의해 인접한 픽셀 전극에 존재하는 액정이 구동되어 생기는 빛샘현상을 막기 위해서 H모양으로 형성한다. 그러나 가능한 빛샘 현상을 줄이기 위해 기존의 기술과 같이 실드 바를 게이트와 가깝도록 형성하면 공통 전극을 픽셀 가운데 위치시키더라도 GCS가 발생할 확률이 증가하게 된다. 따라서 본 발명에서는 공통 메탈 실드 바(126)를 짧게 설계 하였고, 가는 패턴을 가진 H자 모양 대신 패턴 불량에 유리한 ㅁ자 모양을 형성하여 포토리소그래피나 식각 불량으로 발생될 수 있는 GCS를 줄였다. 또한 공통 전극 대신에 소스/드레인 금속을 사용하여 게이트와 가깝게 실드 바(126)를 형성하여 효과적으로 빛샘 현상을 줄일 수 있다.Secondly, the metal shield bar formed during the formation of the gate thin film is generally formed in an H shape to prevent light leakage caused by driving liquid crystal present in adjacent pixel electrodes by data voltage. However, if the shield bar is formed close to the gate as in the conventional technique, to reduce the possible light leakage, the probability of generating GCS increases even if the common electrode is placed in the center of the pixel. Therefore, in the present invention, the common metal shield bar 126 is designed to be short, and instead of the H-shape having a thin pattern, a K-shape is formed to favor pattern defects, thereby reducing GCS that may be generated by photolithography or etching defects. In addition, instead of the common electrode, the source / drain metal may be used to form the shield bar 126 close to the gate to effectively reduce light leakage.
세 번째로 공통 금속과 데이터 라인과의 오버랩 면적이 크면 캐패시턴스 값이 커져 이로 인한 신호의 RC 딜레이가 커지기 때문에 바람직하지 않다. 또한 데이터 수리(repair) 영역이 줄어들고 데이터 구동 전압이 증가되는 단점이 초래된다. 이러한 점을 개선하기 위해 데이터 라인과 겹치는 공통 라인 전극에서 가운데를 박스 모양으로 구멍(50)을 뚫어서 공통 전극(140)과 데이터 신호(12)선과의 오버랩을효과적으로 줄여 원치 않는 캐패시턴스 성분을 줄였다.Thirdly, a large overlap area between the common metal and the data line is not desirable because the capacitance value increases, resulting in a large RC delay of the signal. In addition, there is a disadvantage in that the data repair area is reduced and the data driving voltage is increased. In order to improve this, the hole 50 is formed in the center of the common line electrode overlapping the data line, thereby effectively reducing the overlap between the common electrode 140 and the data signal line 12, thereby reducing unwanted capacitance components.
상기 도 3에서 Cst를 형성하기 위한 공통 전극의 면적이 픽셀전극의 면적 보다 넓고 또한 데이터 라인(12)의 폭이 공통라인과 겹치는 영역에서 점선처럼 중간부위를 줄였다(12-1).In FIG. 3, in the region where the common electrode for forming Cst is larger than the pixel electrode and the width of the data line 12 overlaps with the common line, the middle portion is reduced like a dotted line (12-1).
따라서, 상기한 본 발명에 따른 에프에프에스 모드 액정표시소자의 픽셀구조에 의하면, TFT LCD의 평면 스위칭(InPlane Switching), FFS 구조에서 공통 전극이 픽셀 가운데 위치하는 경우 Cst를 형성하기 위해 초래되는 개구율의 감소가 줄어들어 휘도의 저하가 줄어드는 효과가 있다.Therefore, according to the pixel structure of the FPS mode liquid crystal display device according to the present invention, InPlane Switching of TFT LCD, in the FFS structure of the aperture ratio caused to form Cst when the common electrode is located in the center of the pixel There is an effect that the decrease is reduced, the decrease in luminance is reduced.
또한, Cst를 픽셀 전극 가운데가 아닌 데이터 신호선 옆에 실드 바가 있는 자리에 형성하여 큰 용량을 갖는 Cst를 형성할 수 있는 효과가 있다.In addition, Cst is formed in a position where the shield bar is next to the data signal line instead of the center of the pixel electrode, thereby forming Cst having a large capacitance.
또한 게이트와 같은 게이트를 실드 바가 붙어서 형성되는 GCS를 줄일 수 있어 층간 절연이나 특별한 공정 추가 없이도 수율 향상을 기대할 수 있는 효과가 있다.In addition, it is possible to reduce the GCS formed by attaching a shield bar to a gate such as a gate, thereby improving yield without requiring interlayer insulation or a special process.
또한 빛샘 현상을 줄이기 위해 소스/드레인 공정시 데이터라인과 마찬가지로 플로팅된 금속을 형성하여 실드 바 역할을 하게 한다. 이로 인해 소스/드레인 실드 바가 게이트 라인에 구애받지 않고 가깝게 형성할 수 있어 빛샘 현상을 효과적으로 줄일 수 있다.In addition, to reduce light leakage, the floating metal is formed like a data line during the source / drain process to serve as a shield bar. This allows the source / drain shield bars to be formed close to the gate line, effectively reducing light leakage.
또한 기존 H모양을 갖는 게이트 실드 바 대신 넓은 면을 가진 ??자 모양을 형성하여, 가는 패턴 끝에서 포토리소그래피 및 식각 불량으로 발생될 수 있는 패턴 불량을 감소시킬 수 있고 따라서 GCS를 효과적으로 줄일 수 있는 효과가 있다.In addition, instead of the conventional H-shaped gate shield bar, a broad-shaped ?? shape is formed, thereby reducing pattern defects that may occur due to photolithography and etching defects at the end of the thin pattern, thereby effectively reducing the GCS. It works.
또한 공통 전극과 데이터라인 사이에 오버랩 되는 면적을 줄여서 데이터 라인에 기생하는 캐패시턴스 값을 줄여 RC 딜레이를 감소시킬 수 있는 효과가 있다.In addition, by reducing the overlapping area between the common electrode and the data line, the parasitic capacitance value of the data line can be reduced to reduce the RC delay.
아울러 상기한 본 발명의 바람직한 실시예는 예시의 목적을 위해 개시된 것이며, 당업자라면 본 발명의 사상과 범위 안에서 다양한 수정, 변경, 부가 등이 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구의 범위에 속하는 것으로 보아야 할 것이다.In addition, preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications, modifications and the like are within the scope of the claims It should be seen as belonging.
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CN101373301B (en) * | 2007-08-24 | 2010-08-18 | 北京京东方光电科技有限公司 | FFS type TFT-LCD array substrate structure and manufacturing method thereof |
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CN101373301B (en) * | 2007-08-24 | 2010-08-18 | 北京京东方光电科技有限公司 | FFS type TFT-LCD array substrate structure and manufacturing method thereof |
US9829759B2 (en) | 2015-03-10 | 2017-11-28 | Samsung Display Co., Ltd. | Liquid crystal display device |
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