KR20020053703A - Method of processing image data of high pixel density progressive ccd camera - Google Patents

Abstract

PURPOSE: A method for processing video data of a high pixel CCD(Charge Coupled Device) camera is provided to synchronize output signals of the camera, and to convert a frequency by adjusting to a synchronizing clock of display equipment, so as to transmit the video data outputted from the camera to be displayed on the display equipment with high pixel moving picture without pixel losses. CONSTITUTION: A camera clock inputting step generates a camera clock used as an operation clock of a high pixel CCD camera in a camera clock generator, and inputs the camera clock to the high pixel CCD camera. A display clock inputting step generates a display clock used as an operation clock of display equipment in a display clock generator, and inputs the display clock to a controller. A data generating step picks up an image of a subject to the high pixel CCD camera to generate video data and frame synchronizing signals. A synchronizing step synchronizes the video data and the frame synchronizing signals to the camera clock, for the input to the controller. A data storing step registers the video data in a frame memory, that is a storage device connected to the controller, by adjusting to the frame synchronizing signals. A frequency converting step reads the video data registered in the frame memory by adjusting to display synchronizing signals generated in the controller according to the display clock, and converts an output frequency of the video data to have a frequency same as vertical synchronizing signals of the display equipment. And a display step inputs and displays the read video data in the display equipment.

Description

Image data processing method of high-pixel CD-camera {METHOD OF PROCESSING IMAGE DATA OF HIGH PIXEL DENSITY PROGRESSIVE CCD CAMERA}

The present invention relates to an image data processing method of a high-pixel progressive CCD (charge coupled device) camera, and more particularly, to transfer image data captured by a high-pixel CCD camera to a display device without loss of pixels. An image data processing method of a high pixel CCD camera.

2 is a block diagram of a digital still camera system using a conventional high pixel CCD camera.

The digital still camera system includes a high pixel CCD camera 10, a TV encoder 20, a memory unit 30, a data path switch 40, a mode selection controller 50, and a display device 60. The unit 30 is composed of a frame memory 31, a flash memory 32, and a compression codec 33.

The operation process of the conventional digital still camera system configured as described above is as follows.

The video signal output from the high pixel CCD camera 10 is selected by the control signal of the mode selection controller 50 and the data path switch 40 is output as the video signal according to each mode.

In this case, the data path switch 40 captures the path A or the still image for displaying the video signal output from the high pixel CCD camera 10 on the TV monitor 61 and the B for displaying the PC monitor 62 or the like. You will select a path.

When the path A is selected, the video signal is output as an image signal suitable for a TV or LCD, and is output as a TV signal by the TV encoder 20.

When the path B is selected, the image data contained in the video signal is stored in the frame memory 31, and then the still image stored in the frame memory 31 is displayed on the TV monitor through the path C or the compression codec 33 The image compression (JPEC) is stored in the flash memory 32 and then transferred to the PC.

The image captured by the high-pixel CCD camera 10 is composed of pixels of an extended graphics array (XGA) level of 1024 × 768 (horizontal pixel x vertical pixel) of one frame. In order to display on the screen, the number of pixels should be limited to 720 × 480 (horizontal pixels × vertical pixels) in accordance with the TV pixel standard. Video can be displayed only when using a display device for a PC interface such as a panel or a projector.

However, the conventional digital still camera system can use the pixel count of a high pixel CCD camera only without capturing a still image and transferring it to a PC, so that only a still image can be displayed in a high pixel and a video can be displayed in a high pixel. There is no problem.

The technical problem to be solved by the present invention is to synchronize the output signal of the high pixel CCD camera and to convert the frequency to match the synchronous clock of the display device, the loss of pixels in the image data output from the high pixel CCD camera The present invention provides a video data processing method of a high pixel CCD camera for transmitting a video of a high pixel to be displayed on the display device, which is a display device for a PC interface.

1 is a configuration diagram showing a procedure for implementing the image data processing method of a high pixel CCD camera according to the present invention;

2 is a block diagram of a digital still camera system using a high-pixel CCD camera according to the prior art,

3 is a configuration diagram of a high pixel CCD camera system according to Embodiment 1 for implementing the present invention;

4 is a timing diagram for explaining the operation of the first embodiment;

5 is a configuration diagram of a high pixel CCD camera system according to Embodiment 2 of the present invention;

6 is a timing chart for explaining the operation of the second embodiment;

7 is a block diagram of a high pixel CCD camera system according to a third embodiment of the present invention;

8 is a configuration diagram of a high pixel CCD camera system according to Embodiment 4 of the present invention;

9 is a timing chart for explaining the operation of the third and fourth embodiments.

<Explanation of symbols of main parts in drawings>

10-High Resolution CCD Camera 20-TV Encoder

30-Memory 31-Frame Memory

32-Flash Memory 33-Compression Codec

34-1st frame memory 35-2nd frame memory

36-Buffer Memory 40-Data Path Switch

50-Mode selection controller 60-Display device

61-TV Monitor 62-PC Monitor

71-First Camera Clock Generator 72-Second Camera Clock Generator

73-First Display Clock Generator 74-Second Display Clock Generator

75-third display clock generator 80-control unit

Image data processing method of a high pixel CCD camera according to the present invention for solving the technical problem to be achieved by the present invention described above is a camera clock used as an operation clock of a high pixel CCD camera is generated in the camera clock generator is input to the high pixel CCD camera The camera clock input process is performed, the display clock used as an operation clock of the display device is generated by the display clock generator, and the display clock input process is inputted to the controller. The image of the subject is captured by the high pixel CCD camera, and the image data is synchronized with the frame. A data generation process in which a signal is generated, a synchronization process in which the image data and the frame synchronization signal are synchronized to the camera clock, and input to a controller, and a frame that is the storage device connected to the controller in accordance with the frame synchronization signal. To be written to memory An output frequency of the image data such that a data storing process and the image data written in the frame memory are read out according to the display synchronization signal generated by the controller according to the display clock to have the same frequency as the vertical synchronization signal of the display device. Is converted to a frequency conversion process, and a display process in which the read image data is input to and displayed on the display device.

Another feature of the present invention is characterized in that the frequency conversion process comprises the image data being written and read alternately in the first frame memory and the second frame memory.

In still another aspect of the present invention, the frequency conversion process includes a correction data storage process in which the image data is read from the first frame memory or the second frame memory and written to a buffer memory, and the control unit synchronizes the display device with a signal. A selection signal generation process of generating an output data selection signal for generating a pulse by detecting that the read operation of the first frame memory and the second frame memory are performed together in the same pulse section of the signal; And a data correction process in which the image data written in the buffer memory is read out.

Another feature of the present invention is characterized in that the display clock input process receives a clock from the camera clock generator and multiplies the input to the controller.

Another feature of the present invention is characterized in that the camera clock input process receives a clock from the display clock generator and divides and inputs the clock to the high pixel CCD camera.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(Example 1)

Figure 3 shows the configuration of a high pixel CCD camera system for implementing the image data processing method of a high pixel CCD camera according to an embodiment of the present invention.

A high pixel CCD camera system for achieving the present invention includes a high pixel CCD camera 10, a PC monitor 62, an output terminal of the high pixel CCD camera 10, and a controller 80 connected to an input terminal of the PC monitor 62. A first frame memory 34 and a second frame memory 35 connected to the control unit, a first camera clock generator 71 connected to the high pixel CCD camera 10, and the control unit 80. And a first display clock generator (73) connected thereto.

As shown in FIG. 1, the present invention comprises a camera clock input process, a display clock input process, a data generation process, a synchronization process, a data storage process, a frequency conversion process, and a display process.

The camera clock input process is a process of inputting a camera clock generated by the first camera clock generator 71 into an operation clock of the high pixel CCD camera 10.

The oscillator clock frequency of a typical high pixel CCD camera is about 30 MHz, and the camera clock is generated at 30 MHz, and a 15 kHz camera synchronous clock is generated in the high pixel CCD camera 10 according to the camera clock.

The display clock input process is a process of inputting the display clock generated by the first display clock generator 73 to the controller 80.

The display clock has a frequency of 60 MHz, and a display synchronous signal having a clock frequency of 60 kHz is generated in the controller 80 according to the display clock.

In the data generation process, an image of a subject is captured by the high pixel CCD camera to generate image data and a frame synchronization signal.

The synchronization process is a process in which the image data and the frame synchronization signal are synchronized to the camera clock and input to the controller 80.

The data storing process is a process in which the image data are alternately written to the first frame memory 34 and the second frame memory 35, which are storage devices connected to the controller 80 in accordance with the frame synchronization signal.

In the frequency conversion process, the image data written in the first frame memory 34 and the second frame memory 35 are read out in accordance with the display synchronization signal, thereby matching the vertical synchronization signal of the PC monitor 62. The output frequency of the image data is converted.

At this time, the reading of the image data is performed in accordance with the display synchronization signal, and alternately performed in the first frame memory 34 and the second frame memory 35 according to the frame synchronization signal.

The display process is a process in which image data read out in accordance with the display synchronization signal is input to the PC monitor 62 and displayed.

Next, the operation of the present invention for implementing the image data processing method of the high pixel CCD camera configured as described above will be described.

As shown in FIG. 3, the camera clock generated by the first system clock generator 71 and the display clock generated by the first display clock generator 73 are configured as the PC monitor 62 in which image data captured by the high pixel CCD camera 10 is captured. Determines the flow until it is displayed.

As shown in FIG. 4, the camera synchronous clock generated by the high pixel CCD camera 10 according to the camera clock input from the first system clock generator 71 is a frame synchronous signal having a clock frequency of 15 kHz. The display synchronous clock generated by the controller 80 according to the display clock input from the clock generator 72 is used as a vertical synchronization signal of the PC monitor 62 as a display synchronous signal having a clock frequency of 60 Hz.

The image data captured by the high pixel CCD camera 10 are input to the controller 80 in synchronization with the camera clock together with the frame synchronization signal, and according to the frame synchronization signal, the first frame memory 34 and the first frame. The data is written to the two frame memories 35 and read out in accordance with the display synchronous clock.

The first frame memory 34 and the second frame memory 35 alternately perform a write operation and a read operation according to the frame synchronization signal.

As shown in FIG. 4, A1 image data is written into the second frame memory 35 while A0 image data is read from the first frame memory 34, and A2 image is read while the A1 image data is read. Data is written to the first frame memory 34.

Since the display synchronous clock has a frequency corresponding to four times the camera synchronous clock, the first frame memory 34 and the second frame memory 35 write one write to one pulse of the camera synchronous clock. An action or four reads are performed.

At this time, the controller 80 alternately causes writing and reading operations of the first frame memory 34 and the second frame memory 35 according to the frame synchronization signal, and in the display synchronization clock in the reading operation. Control the process of repeating the read operation accordingly.

Therefore, by the control action of the control unit 80, the image data captured by the high pixel CCD camera 10 is output in accordance with the clock frequency of the vertical synchronization signal of the PC monitor 62 is continuous to the PC monitor 62 Is displayed as a high-resolution video.

(Example 2)

Figure 5 shows the configuration of a high pixel CCD camera system for implementing the image data processing method of a high pixel CCD camera according to another embodiment of the present invention.

A high pixel CCD camera system for achieving the present invention includes a high pixel CCD camera 10, a PC monitor 62, a controller 80, a first frame memory 34 and a second frame memory 35, and a first pixel. And a camera clock generator 71, a first display clock generator 73, and a buffer memory 36, which is a storage device connected to the controller 80.

The present invention comprises a camera clock input process, a display clock input process, a data generation process, a synchronization process, a data storage process, a frequency conversion process, and a display process. , Selection signal generation process, and data correction process.

The correction data storing process is a process in which image data written in the first frame memory 34 and the second frame memory 35 is read out and written in the buffer memory 36.

The selection signal generation process detects that the read operation of the first frame memory 34 and the read operation of the second frame memory 35 occur at the same pulse of the display clock to generate an output data selection signal for generating a pulse. The control unit 80 generates the process.

The data correction process is a process in which image data written in the buffer memory 36 is read out in accordance with the output data selection signal.

Next, different operations from those of the first embodiment of the present invention configured as described above will be described.

As shown in FIG. 6, a read operation of the first frame memory 34 and a read operation of the second frame memory 35 occur together at the same pulse interval of the display sync clock for each pulse of the camera sync clock. A0 + A1 video data, A1 + A2 video data, and the like in which video data are superimposed are displayed on the PC monitor 62.

As illustrated in FIG. 6, the controller 80 generates an output data selection signal for generating a pulse while the image data is overlapped.

The A0 image data written in the first frame memory 34 is read out in accordance with the first display synchronization signal in the same pulse section of the camera synchronization clock and simultaneously written in the buffer memory 36 and in accordance with the next frame synchronization signal. The A1 image data is read from the second frame memory 35 and simultaneously read from the buffer memory 36 in accordance with the output data selection signal.

In addition, A1 image data is read from the second frame memory 35 and written to the buffer memory 36 in accordance with the next display frame synchronization signal.

The image data read out from the buffer memory 36 according to the output data selection signal is the same as the image data read out from the first frame memory or the second frame memory according to the display synchronization signal of the same pulse section of the display clock. .

The image data read out from the buffer memory 36 may be alternately read out from the first frame memory or the second frame memory according to the frame synchronization signal of the same pulse section, and the PC monitor may be adapted to the output data selection signal. The overlapping phenomenon of the image data displayed on the display unit 62 and displayed on the PC monitor 62 is eliminated.

(Example 3)

7 illustrates a configuration of a high pixel CCD camera system for implementing an image data processing method of a high pixel CCD camera according to another exemplary embodiment of the present invention.

A high pixel CCD camera system for achieving the present invention includes a high pixel CCD camera 10, a PC monitor 62, a controller 80, a first frame memory 34 and a second frame memory 35, and a first pixel. And a second display clock generator 74 connected between the camera clock generator 71 and the first camera clock generator 71 and the controller 80.

The present invention comprises a camera clock input process, a display clock input process, a data generation process, a synchronization process, a data storage process, a frequency conversion process, and a display process.

The display clock input process is performed by the second display clock generator 74 receiving the camera clock from the first camera clock generator 71 and doubling the clock frequency of the camera clock. 80) is the process of typing.

Next, different operations from those of the first embodiment of the present invention configured as described above will be described.

As shown in FIG. 7, a camera clock having a frequency of 30 MHz generated by the first camera clock generator 71 is input to the synchronous clock of the high pixel CCD camera 10 and the second display clock generator 74. Also, the frequency is doubled and is input to the controller 80 as a display clock having a frequency of 60 MHz.

Since the display clock is generated by the frequency of the camera clock, the camera synchronous clock generated by the high pixel CCD camera 10 according to the camera clock, and the display synchronous clock generated by the controller 80 according to the display clock. It is possible to precisely synchronize the vertical synchronization by synchronizing the synchronization, and there is no phase change.

Therefore, as shown in FIG. 9, since the reading process of the first frame memory 34 and the second frame memory 35 does not occur together in the same pulse period of the display clock, the image displayed on the PC monitor 62 is displayed. The data is displayed as a high-resolution video without overlapping.

(Example 4)

8 illustrates a configuration of a high pixel CCD camera system for implementing an image data processing method of a high pixel CCD camera according to another exemplary embodiment of the present invention.

The high pixel CCD camera system for achieving the present invention includes a high pixel CCD camera 10, a PC monitor 62, a controller 80, a first frame memory 34 and a second frame memory 35, and the high pixel. And a second display clock generator 75 connected to the second camera clock generator 73 and the second camera clock generator 73 and the controller 80.

The present invention comprises a camera clock input process, a display clock input process, a data generation process, a synchronization process, a data storage process, a frequency conversion process, and a display process.

The camera clock input process includes a camera clock generated by the second camera clock generator 73 receiving a display clock from the third display clock generator 75 and dividing a clock frequency of the display clock by 1/2. It is a process of inputting to the high pixel CCD camera 10.

Next, different operations from those of the first embodiment of the present invention configured as described above will be described.

As shown in FIG. 8, the display clock having a frequency of 60 MHz generated by the third display clock generator 75 is input to the control unit 80 and also input to the second camera clock generator 72 to have a frequency of 30 MHz. The frequency is divided into a camera clock having a high pixel CCD camera 10 is input.

Since the frequency of the display clock is divided by the camera clock, the camera synchronous clock generated by the high pixel CCD camera 10 according to the camera clock and the display synchronous clock generated by the controller 80 according to the display clock. It is possible to precisely synchronize the vertical synchronization by synchronizing the synchronization, and there is no phase change.

Therefore, as shown in FIG. 9, since the reading process of the first frame memory 34 and the second frame memory 35 does not occur together in the same pulse section of the display clock, image data displayed on the PC monitor 62. Is displayed as a high-resolution video without being superimposed.

In the above-described embodiment, the display clock generator and the camera clock generator are implemented as separate components, but in the modification of the embodiment, the control unit may be implemented.

As such, the present invention is not limited to the above-described specific embodiments, and any person skilled in the art to which the present invention pertains may make various modifications without departing from the gist of the present invention as claimed in the claims. Of course, such changes are within the scope of the claims of the present invention.

The image data processing apparatus of a high pixel CCD camera according to the present invention is used to display image data output from the high pixel CCD camera through a signal synchronization interface between a high pixel CCD camera and a display device and to display devices such as a PC interface display device without loss of pixels. There is an effect that can be displayed as a video.

Another effect of the present invention is that it is easy to apply the use of a high-pixel CCD camera mainly used in digital still cameras as educational cameras, CCTV surveillance cameras, communication device cameras and the like.

Claims (5)

A camera clock input process generated by a camera clock generator used as an operation clock of a high pixel CCD camera and input to the high pixel CCD camera; A display clock input process in which a display clock used as an operation clock of the display device is generated by the display clock generator and input to the controller; A data generation process in which an image of a subject is captured by the high pixel CCD camera to generate image data and a frame synchronization signal; A synchronization process in which the image data and the frame synchronization signal are synchronized with the camera clock and input to a controller; A data storing process of writing the image data into a frame memory which is a storage device connected to the control unit according to the frame synchronization signal; A frequency conversion in which the output frequency of the image data is converted so that the image data written in the frame memory is read out in accordance with the display synchronization signal generated by the controller according to the display clock to have the same frequency as the vertical synchronization signal of the display device. process; And And a display process in which the read image data is input to and displayed on the display device. The method of claim 1, And the frequency conversion process includes writing and reading the image data alternately between the first frame memory and the second frame memory. The method of claim 2, The frequency conversion process includes a correction data storage process in which the image data is read from the first frame memory or the second frame memory and written to a buffer memory at the same time; A selection signal generation process of generating, by the controller, an output data selection signal for generating a pulse by detecting that the read operation of the first frame memory and the second frame memory are performed together in the same pulse section of the display device synchronization signal; And And a data correction process of reading out image data written to the buffer memory in response to the output data selection signal. The method according to claim 1 or 2, The display clock input process of receiving a clock from the camera clock generator, the image data processing method of a high pixel CCD camera, characterized in that the input to the controller. The method according to claim 1 or 2, The camera clock input process receives the clock from the display clock generator and divides and inputs the clock to the high pixel CCD camera.