KR20020050901A - Conductive lines and interconnections in semiconductor devices and forming method thereof - Google Patents

Abstract

PURPOSE: An interconnection and an interconnection connecting portion are provided to simultaneously reduce an interconnection resistance and an electromigration by forming a swollen shape on an upper surface of a damascene structured interconnection. CONSTITUTION: An interconnection and an interconnection connecting portion comprise insulating part made of a first, a second, and a third insulating layers(21,22,23) are formed on a semiconductor substrate(20), a hole formed by removing the lower portion of the insulating part for exposing a defined region of the semiconductor substrate(20), a trench having a defined interconnection pattern formed by selectively removing the upper portion of the insulating part, a barrier(24) formed in the hole and trench to contact the semiconductor substrate(20), a first conductive layer(25) having a hollowed portion completely filled into the hole and trench, and a second conductive layer is formed on only the first conductive layer(25) for forming a swollen portion at the hallowed portion of the first conductive layer(25).

Description

Wiring and wiring connecting portion of semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to wiring and wiring connection portions of semiconductor devices and a method of manufacturing the same. In particular, a via hole, which is a connection portion of an upper wiring to be connected to a lower conductive layer, and a trench in which an upper wiring is to be formed are formed in an insulating layer, and then a barrier layer and copper, etc. After forming the first conductive layer of the via hole and the inner surface of the trench, the surface of the insulating layer is subjected to CMP using the barrier layer as the polishing stop layer to the conductive layer, and then the second conductive layer is exposed to the first conductive layer by CVD. By selectively depositing only on the upper surface, the wiring is reinforced with convex top surface and reinforced conductive layer partially protruded over the insulating layer to prevent the change of wiring resistance and electron transfer phenomenon, reduce the parasitic capacitance change, and uniform insulation A damascene structure wiring and wiring connection part of a semiconductor device for securing the thickness of a layer and reducing defects, and a manufacturing method thereof.

The wiring connection part and wiring for the electrical connection between the elements of the semiconductor device and the formation technology thereof are formed by forming a plug in a contact hole or a via hole of an interlayer insulating layer, and then patterning the wiring on the plug. Deeper, low step coverage, short circuit between wirings, and thus yield of product is poor.

In order to improve this, a dual damascene structure has been proposed as a method of forming a contact plug and a wiring at the same time. However, such a structure and its manufacturing method are excellent in mitigating a step difference from the surroundings. Further improvements in step coverage and reduced resistance at the wiring connections are needed.

In addition, in the conventional art of forming copper metal wiring and wiring connection portions, a copper layer is formed as a conductive layer in a hole or a trench by electroplating, and then a CMP is applied to the copper layer to expose the surface of the insulating layer. The wiring connecting portion and the wiring are formed at the same time.

However, the chemical mechanical polishing (CMP) for the copper layer has a large difference in the polishing ratio between the copper / barrier layer and the insulating layer, so that the upper surface of the copper layer remaining in the trenches forming the respective wirings is centered by dishing. Intensity of the polishing resulted in a concave profile (see FIG. 1C), while erosion of a region having a large pattern density was intensified due to a partial difference in the pattern density, resulting in concave overall cross-sectional profile (FIG. 1D). Reference).

Therefore, in the related art, the resistance change due to the loss of the metal wiring and the thickness of the insulating layer are lowered, thereby increasing the parasitic capacitance between the wirings.

1A to 1D are process cross-sectional views showing a wiring of a semiconductor device and a method of forming a connection portion thereof according to the prior art.

Referring to FIG. 1A, a first insulating layer 11 is deposited on a semiconductor substrate 10 made of silicon or the like by an oxide film or the like by chemical vapor deposition (hereinafter, referred to as CVD).

Next, in order to use the etch stop layer on the first insulating layer 11, the second insulating layer 12 is thinly formed of an insulating material having a large etching selectivity with the first insulating layer. In this case, the second insulating layer 12 may be formed by depositing a nitride film by CVD.

Then, the third insulating layer 13 is deposited on the second interlayer insulating layer by using an interlayer dielectric layer 13 with an oxide film or the like. In this case, the third insulating layer 13 may be formed by combining tetra ethyl ortho silicate (TEOS) and spin on glass (SOG), and a main component thereof is SiO ₂ .

In the above description, the substrate 10 may be a semiconductor substrate having an impurity diffusion region (not shown) or a lower wiring.

In addition, contact portions H1 to via holes H1 and upper wirings which expose conductive regions of the substrate by patterning predetermined portions of the third, second and first insulating layers 13, 12, and 11 by photolithography. The pattern forms a recessed trench T1. That is, in a subsequent process, a plug for connecting conductive regions such as upper and lower wirings is formed in the via hole H1, and upper wirings are simultaneously formed in the trench.

At this time, the contact hole and the trench are patterned at the same time, the method can be carried out as follows.

First, the first hole defining the via hole forming portion is formed by removing the third and second insulating layers 13 and 12 to a predetermined depth.

In addition, an etching mask in which the upper wiring trench pattern is defined is formed on the third insulating layer 13 on the portion including the first hole, and then the third insulating layer 13 is removed by dry etching using the etching mask. To form a trench. Therefore, during the trench formation etching, the first insulating layer 11 under the first hole is simultaneously etched to simultaneously form the via hole H1 having the upper portion extended with the trench T1.

Referring to FIG. 1B, the barrier layer 14 is contacted with a physical vapor deposition (PVD) or ionized metal plasma (IMP) to contact the substrate 10 exposed through trenches and via holes on the remaining third insulating layer 13. Form by law. At this time, the barrier layer 14 is formed by depositing Ti, TiN, Ta, TaN and the like.

Then, the conductive layer 15 is formed on the barrier layer 14 to form the upper wiring. In this case, when the conductive layer is formed using Cu, a copper seed layer (not shown) for forming a copper bulk layer on the surface of the barrier layer 14 is also deposited by PVD method. After the formation, the copper bulk layer 15 is formed to a thickness that sufficiently fills the contact hole and the trench by electroplating using the copper seed layer. Thus, via holes were filled with a copper layer to simultaneously form interconnects and upper wiring forming layers.

Referring to FIG. 1C, a planarization process is performed on the formed copper bulk layer to expose the surface of the remaining third insulating layer 13 to form an upper interconnection electrically connected to the exposed conductive region of the substrate without a separate patterning process. At this time, the planarization process is performed by chemical mechanical polishing (CVD). At this time, a dishing phenomenon occurs in which the upper portion of the remaining conductive layer 150 is concave due to a difference in the polishing ratio between the copper and the oxide film, and the maximum thickness of the center of the center portion reaches 'D1'.

Meanwhile, referring to FIG. 1D, in the region where the pattern density of the upper wiring 150 is high, erosion of the third insulating layer 13 and the conductive layer 150 is simultaneously performed to concave the overall cross-sectional profile. Form, eroded up to 'E' in the center.

Therefore, the wiring connecting portion and the wiring forming method of the semiconductor device according to the prior art are parasitic between wirings due to the increase in resistance according to the dipping of the copper layer, which is the metal wiring, and the thickness of the third insulating layer, which is the inter metal dielectric layer. There is a problem that capacitance increases.

Accordingly, an object of the present invention is to form a via hole, which is a connection portion of an upper wiring to be connected to a lower conductive layer, and a trench, in which an upper wiring is to be formed, in an insulating layer, and then to form a barrier layer and a first conductive layer such as copper on the inner surface of the via hole and the trench. After forming, the surface of the insulating layer is subjected to CMP using the barrier layer as the polishing stop layer to the conductive layer, and then the second conductive layer is selectively deposited only on the exposed upper surface of the first conductive layer by CVD, so that the top surface is convex and insulated. The semiconductor is formed by reinforcing the conductive layer, which partially protrudes from the upper part of the layer, to prevent the change of the wiring resistance and the electron transfer phenomenon, to reduce the parasitic capacitance change, to secure the uniform thickness of the insulating layer, and to reduce the defects. A damascene structure wiring and wiring connection of a device and a method of manufacturing the same.

The wiring and wiring connection part of the semiconductor device according to the present invention for achieving the above object extends from an insulating layer formed on a semiconductor substrate, a hole to remove a portion of the insulating layer to expose a predetermined portion of the substrate A portion of the insulating layer is removed to form a trench having a predetermined wiring pattern, a barrier layer formed on an inner surface of the hole and the trench in contact with the exposed substrate, and a contact with the barrier layer in contact with the barrier layer. A first conductive layer that is completely buried and has a concave upper surface, and a second conductive layer partially protruded from the surface of the insulating layer and formed only on the upper surface of the first conductive layer so as to planarize the upper surface of the first conductive layer. .

Preferably, the first conductive layer is a copper layer formed by a plating method and the second conductive layer is formed of a copper layer formed by chemical vapor deposition (CVD), and the upper profile of the second conductive layer is flat or convex. Has

According to an aspect of the present invention, there is provided a method of manufacturing a wiring and wiring connection part of a semiconductor device, the method including forming a wiring insulating layer on a semiconductor substrate, and partially removing a lower portion of the insulating layer to expose a predetermined portion of the substrate. Forming a trench having a predetermined wiring pattern by partially removing a hole and an upper portion of the insulating layer, forming a trench in contact with the exposed substrate and forming a barrier layer on an inner surface of the hole and the trench; And forming a first conductive layer on the insulating layer in contact with the barrier layer and completely filling the holes and trenches, and performing chemical mechanical polishing on the first conductive layer using the insulating layer as an abrasive stop layer. Leaving only the first conductive layer inside the hole and the trench, and forming a second conductive layer only on the remaining upper surface of the first conductive layer. It comprises the step of forming a quarter-phase deposition.

Preferably, the first conductive layer is formed of copper formed by the plating method, the second conductive layer is formed of copper formed by the chemical vapor deposition, and the second conductive layer is formed on the trench upper surface by the chemical mechanical polishing. It is formed to a thickness that can supplement the first conductive layer removed further down.

1A to 1D are cross-sectional views illustrating a method of manufacturing wirings and wiring connectors of a semiconductor device according to the related art.

2A through 2F are cross-sectional views illustrating a method of manufacturing wirings and wiring connectors of a semiconductor device according to the present invention.

Figure 3 is a cross-sectional view of the wiring and wiring connection of the semiconductor device manufactured according to the present invention

The present invention forms a trench in which an via hole or a contact hole and a wiring pattern are engraved in an insulating layer for manufacturing a wiring and a wiring connection part having a damascene structure, and then forms a barrier layer so as to sufficiently fill the holes and trenches with a metal such as copper. The first conductive layer interposed on the lower portion is formed on the insulating layer, and the CMP using the insulating layer as the polishing stop layer is applied to the first conductive layer so as to remain only in the holes and trenches, and then the second conductive layer remains. Chemical vapor deposition (CVD) is formed only on the surface of the conductive layer to complete the wiring having a convex shape on the upper surface.

Therefore, unlike the prior art, in the present invention, since the upper surface of the wiring of the damascene structure is manufactured in a convex form, the resistance of the wiring is reduced, and at the same time, electromigration is prevented, and copper is reinforced, so that the metal wiring and the insulating layer are interposed. It is possible to reduce the capacitance change of.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are cross-sectional views illustrating a method of manufacturing wirings and wiring connectors of a semiconductor device according to the present invention.

Referring to FIG. 2A, the first insulating layer 21 is deposited on the semiconductor substrate 20 made of silicon by an oxide film or the like by chemical vapor deposition (hereinafter, referred to as CVD).

Next, in order to use the etch stop layer on the first insulating layer 21, the second insulating layer 22 is formed thin with an insulating material having a large etching selectivity with the first insulating layer. In this case, the second insulating layer 22 may be formed by depositing a nitride film by CVD.

The third insulating layer 23 is deposited on the second insulating layer 22 by an inter-metal dielectric 23 using an oxide film or the like. In this case, the third insulating layer 23 may be formed by combining tetra ethyl ortho silicate (TEOS) and spin on glass (SOG), and the main component thereof is SiO ₂ , and the formation thickness is an amount removed by buffing CMP. In consideration of this, it is formed to ensure a stable third insulating layer (23).

In the above description, the substrate 20 may be a semiconductor substrate having an impurity diffusion region (not shown) or a lower wiring.

In addition, contact portions H2 to via holes H2 and upper wirings which expose the conductive region of the substrate by patterning predetermined portions of the third, second and first insulating layers 23, 22, and 21 by a photolithography method. The pattern forms a recessed trench T2. That is, in a subsequent process, a plug for connecting conductive regions such as upper wiring and lower wiring is formed in the via hole H2, and upper wiring is simultaneously formed in the trench T2.

In this case, when the contact hole and the trench are patterned at the same time, the method may be performed as follows.

First, the first hole defining the via hole forming portion is formed by removing the third and second insulating layers 23 and 22 to a predetermined depth.

In addition, an etching mask in which the upper wiring trench pattern is defined is formed on the third insulating layer 23 on the portion including the first hole, and then the third insulating layer 23 is removed by dry etching using the etching mask. To form a trench. Therefore, when the trench is formed for etching, the first insulating layer 21 under the first hole is simultaneously etched to simultaneously form the via hole H2 having an extended upper portion with the trench T2. At this time, if the thicknesses of the third insulating layer and the first insulating layer are properly determined and formed, the formation of the second insulating layer, which is an etch stop layer, may be omitted.

Referring to FIG. 2B, the barrier layer 24 is contacted with a physical vapor deposition (PVD) or ionized metal plasma (IMP) to contact the substrate 20 exposed through trenches and via holes on the remaining third insulating layer 23. Form by law. In this case, the barrier layer 24 may be formed by depositing Ti, TiN, Ta, TaN, or the like, and may have a stacked structure thereof.

Then, the conductive layer 25 is formed to form the upper wiring on the barrier layer 24. At this time, when the conductive layer is formed using Cu, a copper bulk layer (Cu bulk) on the surface of the barrier layer 24 is formed. A copper seed layer (not shown) for forming a layer is formed by depositing a PVD method as well, and then copper to a thickness that sufficiently fills contact holes and trenches by electroplating using a copper seed layer. The bulk layer 25 is formed. Thus, via holes were filled with a copper layer to simultaneously form interconnects and upper wiring forming layers.

Referring to FIG. 2C, the planarization process is performed on the formed copper bulk layer by CMP to expose the surface of the third insulating layer 23 so that the remaining conductive layer for upper wiring is electrically connected to the exposed conductive region of the substrate without a separate patterning process. 250). At this time, the upper surface of the conductive layer 250 remaining due to the difference in the polishing ratio between the copper and the oxide film is concave recessed phenomenon, the maximum thickness of the center of the center is a 'D2'.

The barrier layer 240 remains so as to be interposed only between the conductive layer 250 and the via hole and the inner surface of the trench.

Referring to FIG. 2D, the additional conductive layer 26 is formed only on the upper surface of the remaining conductive layer 250. At this time, the additional conductive layer 26 forms copper by chemical vapor deposition (CVD). As a result, the leveling phenomenon can be compensated and the upper wiring can be realized with the flattened upper surface.

3 is a cross-sectional view of a wiring and a wiring connection part of a semiconductor device manufactured according to the present invention.

Referring to FIG. 3, a first insulating layer 21, a second insulating layer 22, which is an etch stop layer, and a third insulating layer are formed on a semiconductor substrate 20 made of silicon or the like on which elements such as transistors and capacitors are formed. 23) are formed in turn, and a via hole or a contact hole is formed to remove predetermined portions of the first insulating layer and the second insulating layer to expose the surface of the predetermined portion of the substrate 20, and extends to the via hole. A trench for a wiring pattern formed by removing a predetermined portion of the third insulating layer is formed. In this case, the second insulating layer may be omitted.

The via hole and the trench are filled with a conductive layer 250 made of copper, and a diffusion barrier layer 240 is disposed between the conductive layer 250 and the inner surface of the hole and the trench.

The additional conductive layer 26 is thinly formed on the upper surface of the conductive layer 250, and the additional conductive layer 26 protrudes slightly from the surface of the third insulating layer 23.

Therefore, the present invention manufactures the upper surface of the damascene structure in a convex form, thereby reducing the resistance of the wiring and at the same time preventing electromigration and reinforcing copper, thereby reducing the capacitance change between the metal wiring and the insulating layer. It has the advantage of letting.

Claims (8)

An insulating layer formed on the semiconductor substrate, A hole having a lower portion of the insulating layer removed to expose a predetermined portion of the substrate and a trench extending from the hole to partially remove the upper portion of the insulating layer to have a predetermined wiring pattern; A barrier layer in contact with the exposed substrate and formed in the interior surfaces of the holes and trenches, A first conductive layer in contact with the barrier layer and completely filling the holes and trenches, the upper surface being concave; And a second conductive layer formed only on the upper surface of the first conductive layer so as to partially protrude from the surface of the insulating layer and planarize the upper surface of the first conductive layer. The method according to claim 1, And wherein the semiconductor substrate has an impurity diffusion region or a lower wiring formed in the predetermined portion. The method according to claim 1, And the first conductive layer is a copper layer formed by a plating method, and the second conductive layer is a copper layer formed by chemical vapor deposition (CVD). The method according to claim 1, And the upper profile of the second conductive layer has a flat or convex shape. Forming a wiring insulation layer on the semiconductor substrate; Partially removing a lower portion of the insulating layer to expose a predetermined portion of the substrate, and extending from the hole to partially remove an upper portion of the insulating layer to form a trench having a predetermined wiring pattern; Forming a barrier layer in contact with the exposed substrate and in the inner surfaces of the holes and trenches; Forming a first conductive layer on the insulating layer in contact with the barrier layer and completely filling the holes and trenches; Performing chemical mechanical polishing on the first conductive layer using the insulating layer as a polishing stop layer to leave the first conductive layer only in the hole and the trench; And forming a second conductive layer by chemical vapor deposition only on the remaining upper surface of the first conductive layer. The method according to claim 5, And the first conductive layer is formed of copper formed by a plating method, and the second conductive layer is formed of copper formed by the chemical vapor deposition. The method according to claim 5, And the second conductive layer is formed to a thickness sufficient to supplement the first conductive layer removed below the upper surface of the trench by the chemical mechanical polishing. The method according to claim 5, The predetermined portion of the exposed substrate further comprises forming a lower wiring on the upper portion of the semiconductor substrate or forming an impurity diffusion region on the predetermined portion of the semiconductor substrate. .