KR20020049348A - Semiconductor Optoelectronic Device with a Non-rectangular Substrate - Google Patents

Abstract

PURPOSE: A photoelectronic semiconductor device having a non-rectangular substrate is provided to reduce abrasion and damage of a cutting tool and improve a yield of dicing process by preventing effectively a die chipping phenomenon. CONSTITUTION: A hexagonal crystal wafer(30) used as a substrate of a GaN-based photo-emission diode is prepared. An n-type GaN-based chemical semiconductor layer(31), an In-GaN-based active layer(32), a p-type GaN-based chemical semiconductor layer(33) are continuously formed on an upper portion of the hexagonal crystal wafer(30). A dry etch process is performed to remove partially the p-type GaN-based chemical semiconductor layer(33), the In-GaN-based active layer(32), and the n-type GaN-based chemical semiconductor layer(31). A p-type electrode(34) and an n-type electrode(35) are formed on the p-type GaN chemical semiconductor layer(33) and the exposed n-type GaN-based chemical semiconductor layer(31), respectively.

Description

Semiconductor Optoelectronic Device with a Non-rectangular Substrate}

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an optoelectronic device in which a semiconductor substrate is non-rectangular, and more particularly, to a semiconductor optoelectronic device having parallelograms or triangular substrates that belong to the same crystallographic plane family. will be.

Semiconductor optoelectronic devices such as light emitting diodes, lasers and photodetectors usually consist of several layers of epitaxial compound semiconductors grown on a single crystal substrate. The choice of single crystal substrate is selected by crystallographic considerations such as the crystal structure and lattice constants of the epitaxial compound layer and the single crystal substrate. In general, a single crystal substrate crystallized in the same form as the epitaxial compound semiconductor layer allows the epitaxial compound semiconductor layer to be grown quickly and easily thereon. In addition, the lattice coefficient of a single crystal substrate is as close to the lattice coefficient of the epitaxial compound semiconductor layer as possible to prevent the occurrence of tensile or compressive strain in the epitaxial semiconductor compound layer.

Recently, gallium nitrogen (GaN) -based compound semiconductor materials have been studied with attention due to their ability to generate green, blue and cyan light. Among possible applications of GaN-based compound semiconductor materials, GaN-based light generating diodes emitting blue light are commercially available. Based on the crystallographic considerations described above, GaN-based light emitting diodes are formed of sapphire (Al ₂ O ₃ ) substrates or silicon carbide (SiC) substrates, which usually belong to hexagonal crystals.

FIG. 1 is a plan view showing a sapphire or silicon carbide wafer 10 used as a GaN based light emitting diode substrate. A number of identical GaN based light emitting diodes (not shown) are installed together on the wafer 10 through suitable semiconductor processes. Usually such GaN based light emitting diodes consist of an array of right angle elements 11 called dice, with edge spaces measured in millimeters or less. To obtain an independent GaN based light emitting diode for packaging, the hexagonal crystal wafer 10 is cut or broken along a die edge 12 using a cutting tool such as a scriber with a diamond blade. .

Disadvantageously, however, the rectangular dicing process, i.e., cutting the wafer into rectangular dies, fails to produce a smooth and clean cut surface on the wafer 10, which causes the wafer 10 made of sapphire or silicon carbide to be cubic. This is because it is not crystallized in form. On the other hand, wear and damage on cutting tools is accelerated by the right angle dicing process. As a result, the right angle dicing process has at least three disadvantages. First, the process cost is high because of the high consumption of the cutting tool. Second, the manufacturing process is interrupted to replace the old cutting tool with a new cutting tool, and the processing time becomes longer. Finally, the yield of a right angle dicing process is lowered due to die chipping.

One object of the present invention is to provide a semiconductor optoelectronic device having a non-rectangular substrate cut from a wafer along the same crystallographic plane group of wafers. The non-rectangular substrate has a main surface on which a stacked semiconductor structure is formed and a side wall surface surrounding the main surface. The main surface is in the form of a polygon, in particular parallelogram or triangle, all of its interior angles being 60 or 120 degrees. The side walls all belong to the same crystallographic plane group.

According to the invention a wafer, such as a sapphire, silicon carbide or gallium phosphide wafer, is prepared first. Many semiconductor optoelectronic structures, such as light emitting diodes, on the main surface of a wafer are fabricated by arranging polygonal dice whose edges all extend along the same crystallographic plane group of wafers. In addition, all the cabinets of each polygonal dice are 60 or 120 degrees. Along the die edge, the cutting tool cuts or breaks the wafer into individual polygonal dice. Since all die edges extend along the crystallographic plane of the wafer, the cutting tool divides the wafer into dice smoothly and cleanly.

Therefore, the cutting tool easily produces a smooth and clean cut surface through the dicing process according to the present invention. Wear and damage to cutting tools are also reduced. The yield of the dicing process according to the invention is increased because die chiping is effectively avoided.

1 is a plan view showing a prior art arrangement of a semiconductor optoelectronic device on a wafer;

2a to 2c each show hexagonal crystals ( ), ( ), And ( } A schematic representing the plane,

3A to 3C are cross-sectional views sequentially illustrating steps of manufacturing a light emitting diode;

4 is a plan view showing the arrangement and orientation of parallelogram dice according to the invention on a wafer, and

5 is a plan view showing the arrangement and orientation of triangular dice according to the invention on a wafer.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

Hexagonal (or wurtzite) crystal wafers, such as sapphire and silicon carbide wafers, are commonly used as substrates for GaN-based semiconductor optoelectronic devices as described above. 2A-2C are schematic diagrams showing the crystallographic axis and plane of hexagonal crystals. As shown in FIGS. 2A-2C, the hexagonal crystal consists of three coplanar axes, a ₁ , a ₂ , and a ₃ and axes c perpendicular to the three axes, a ₁ , a ₂ , and a ₃ . It is defined based on the coordinate system to be. The angle between any of the three axes, a ₁ , a ₂ , and a ₃ , is 120 degrees. In summary, FIGS. 2A-2C show the hexagonal crystals ( ), ( ), And ( ).

A substrate for GaN-based semiconductor optoelectronic devices, wherein sapphire and silicon carbide wafers are < Sliced from crystals grown along the> direction ( A wafer is known.

In order to fabricate a GaN-based semiconductor optoelectronic device on the major surface of a (0001) wafer in accordance with the present invention, each die has all edges { } Designed in such a way that it extends along a plane because the plane is easy to cut with its bonding hands arranged. At this time { } The plane is ( Flat and equivalent to it ( ) Flat, ( ) Flat, ( ) Flat, and ( ) Plane group including the plane. This arrangement allows each die to follow its edges during the dicing process with a cutting tool ( Easily cut from the wafer. Therefore, wear and damage to the cutting tool is greatly reduced.

3A to 3C, the die arrangement and orientation on the hexagonal crystal substrate according to the present invention are illustrated by the manufacturing steps of the GaN based light emitting diode. In Fig. 3A, a hexagonal crystal wafer 30 is first prepared for use as a substrate of a GaN based light emitting diode. On the hexagonal crystal wafer 30, an n-type GaN-based compound semiconductor layer 31, an active layer 32 made of InGaN to generate blue light, and a p-type GaN-based compound semiconductor layer 33 are successively formed. . Next, a dry etching process is performed to partially remove the p-type GaN-based semiconductor compound layer 33, the active layer 32, and the n-type GaN-based compound semiconductor layer 31. As shown in FIG. 3B, the n-type GaN-based compound semiconductor layer 31 is partially exposed after dry etching.

As shown in FIG. 3C, the p-type electrode 34 and the n-type electrode 35 are formed on each of the p-type GaN-based compound semiconductor layer 33 and the exposed n-type GaN-based compound semiconductor layer 31. Thus, a GaN-based light emitting diode is completed.

In the same way, a number of identical GaN based light emitting diodes are fabricated by the arrangement of dice on a hexagonal crystal wafer. As mentioned above, ( ) When wafers are used, the edges of each die are all { } Are arranged to extend along a plane. As a result, each die is formed of a polygon whose interior angle is selected from both the group consisting of 60 and 120 degrees.

As an example of a polygonal dice according to the invention, FIG. 4 shows a parallelogram dice 41 arranged on a hexagonal crystal wafer 40. if ( ) Wafer 40 is used, each parallelogram dice 41 of the edge 410 are all { } Expand along the plane. As another embodiment of the polygonal dice according to the invention, FIG. 5 shows a triangular dice 51 arranged on a hexagonal crystal wafer 50. Similarly if ( ) Wafer 50 is used, the edges 510 of each triangular dice 51 are all { } Expand along the plane.

By the dicing process, the wafer 40 or 50 is cut or broken into separate parallelogram or triangular dice 41 or 51 using a cutting tool. Since the die edges all extend along a crystallographic plane that is easy to cut, the cutting tool produces smooth and clean cuts on wafers 40 or 50. As a result, the parallelogram or triangular dicing process according to the invention reduces wear and damage on the cutting tool. Thus, the rising process cost by replacing the cutting tool is reduced. The process time is also shortened because the interference from replacing old cutting tools with new ones is reduced. Moreover, the yield of the dicing process according to the invention is also increased because die chipping is effectively avoided.

Although the present invention has been described in detail with reference to an example of a semiconductor optoelectronic device having a hexagonal crystal substrate, it is also possible to apply the present invention to a semiconductor optoelectronic device having a zinclende crystal substrate such as a gallium phosphide (GaP) substrate. Do. In this case, the gallium phosphide wafer is usually < Sliced from crystals grown along the> direction, ( A wafer is known. According to the present invention ( ) In order to fabricate a semiconductor optoelectronic device on the main surface of the wafer, each die must have a { } Designed to extend along a plane, because the plane is easy to cut due to the arrangement of the joining hands. At this time { } The plane is ( ) And a plane equal to that plane ( ) Flat, ( ) Flat, ( ) Flat, ( ) Flat, and ( ) Plane group consisting of planes. This arrangement allows each die to be cut along its edge during the dicing process by the cutting tool ( ) Easily cut from the wafer. Thus, the cutting tool easily produces a smooth and clean cut surface during the dicing process, and the yield of the dicing process is increased because die chiping is effectively avoided.

The present invention has been described by the above embodiments and preferred embodiments, but is not limited to the disclosed embodiments. On the contrary, various modifications and similar configurations will be apparent to those skilled in the art. Accordingly, the following claims are to be understood to include configurations similar to all such variations.

Through the dicing process according to the present invention, a smooth and clean cut surface is easily produced. Wear and damage to cutting tools are also reduced. The yield of the dicing process according to the invention also increases due to the effective avoidance of die chipping.

Claims (12)

A main surface and a plurality of side wall surfaces surrounding the main surface, the main surface being a polygonal surface selected from the group consisting of 60 and 120 degrees of interior angle, each of the plurality of side walls belonging to the same crystallographic plane group, the substrate A semiconductor optoelectronic device comprising a stacked semiconductor structure formed on a major surface of the. The semiconductor optoelectronic device according to claim 1, wherein the substrate is made of a material selected from the group consisting of sapphire and silicon carbide. The method of claim 2, wherein the main surface is { } Belonging to a plane, and each of said plurality of side walls is { } Semiconductor optoelectronic devices belonging to a plane. The semiconductor optoelectronic device according to claim 1, wherein the substrate is made of gallium phosphide. The method of claim 4, wherein the main surface is { } Belonging to a plane, each of said plurality of sidewalls being { } Semiconductor optoelectronic devices belonging to a plane. The semiconductor optoelectronic device of claim 1, wherein the main surface has a parallelogram or triangle shape. Preparing a wafer having a major surface; Forming a laminated semiconductor structure on the main surface; And Cutting the wafer into at least one polygonal substrate along the same crystallographic plane group, wherein each interior angle of the at least one polygonal substrate is selected from the group consisting of 60 and 120 degrees. Manufacturing method. The method of claim 7, wherein preparing the wafer comprises preparing a wafer made of a material selected from the group consisting of sapphire and silicon carbide. The method of claim 8, wherein the main surface is { } In the plane and the crystallographic plane group is { } Method for manufacturing a semiconductor optoelectronic device that is a plane group. The method of manufacturing a semiconductor optoelectronic device according to claim 7, wherein the preparing of the wafer comprises preparing a wafer made of gallium phosphide. The method of claim 10, wherein the main surface is { } Belongs to a plane, and the crystallographic plane group is { } Method for manufacturing a semiconductor optoelectronic device that is a plane group. 8. The method of claim 7, wherein the at least one polygonal substrate is a parallelogram or triangle.