KR20020036697A - Nonvolatile Semiconductor Memory Device - Google Patents

Abstract

PURPOSE: To enable performing write-in, verifying, or the like for a storage element storing trimming information, replacement information, or the like without providing an exclusive circuit, in a non-volatile semiconductor memory in which electrical write-in and erasure can be performed like a flash memory. CONSTITUTION: In a non-volatile semiconductor memory consisting of plural memory cells varying threshold voltage by applying the prescribed voltage to a selected memory cell and storing information by difference of threshold voltage, and provided with a memory array in which one part of memory cells are made spare memory cells, the device is provided with a latch circuit (LT) connected to a bit line (MB) of the memory array (11) through a transmission switch (Qti), the memory array can store replacement information for replacing a defective bit by the spare memory cell, and replacement information is transferred to the latch circuit from the memory array through the transmission switch and held.

Description

Nonvolatile Semiconductor Memory Device

The present invention relates to a particularly effective technique applied to a method for setting redundancy relief information and trimming information such as voltage in an electrically recordable / erasable nonvolatile memory, and relates to an effective technique used for, for example, a flash memory.

The flash memory uses a nonvolatile memory device composed of a MOSFET having a two-layer gate structure having a control gate and a floating gate as a memory cell, and stores data by changing the threshold voltage of the MOSFET by changing an accumulated charge amount of the floating gate. Doing.

In such a flash memory, an internal power supply circuit having a boosting circuit such as a charge pump circuit is generally provided in order to generate a high voltage necessary for a write / erase operation to a memory cell. However, in the boosting circuit, a constant variation occurs in the generated voltage due to the variation of the elements constituting it. In addition, for the MOSFET constituting the memory device of the flash memory, parameters such as the thickness of the gate oxide film and the impurity concentration of the drain region, such as the thickness of the gate oxide film, vary depending on the process, and the like. It will fluctuate in range.

As described above, if the voltage generated in the boost circuit and the write / erase characteristics of the memory element change, the correct operation of the memory is not guaranteed. Therefore, there is a technique in which a trimming circuit is provided so that the generated voltage or the recording time can be finely adjusted at the stage after chip manufacturing. In addition, in a semiconductor memory general including a flash memory, a so-called redundant circuit is provided which improves the yield by replacing defective bits contained in the memory array with spare memory cells.

Conventionally, the level setting of the trimming circuit and the replacement information in the redundant circuit are generally performed using a fuse formed of a polysilicon layer (hereinafter referred to as a polysilicon fuse). However, in the method using the polysilicon fuse, an apparatus for cutting the polysilicon fuse by a laser or the like is required, and since it is impossible to change afterwards once, it is necessary to pay close attention. Another problem is that trimming cannot be performed after assembling in a package. For this reason, there has been proposed an invention relating to a trimming circuit and a redundant circuit in which a nonvolatile memory device constituting a memory array instead of a polysilicon fuse is used instead of the polysilicon fuse.

However, in the method of using a nonvolatile memory device instead of a polysilicon fuse, a memory device for fuse is generally provided separately from the memory array, so that a dedicated circuit for writing or verifying the memory device is required. There is a problem that the overhead of the circuit becomes large and the chip size is increased.

Therefore, instead of the polysilicon fuse, a switching element is used, a trimming register for holding trimming information for controlling the switching element is provided, and a relief register for storing the replacement information is provided, thereby trimming and replacing information. Is stored in a predetermined area in the memory array, and has been proposed to read out from the memory array at reset and set it in a trimming register or a relief register (Japanese Patent Laid-Open No. 11-297086).

However, in this prior application, it is not clear in which area of the memory array the trimming information or the relief register is stored, and when storing it in the normal use area, there is a problem that the storage capacity that a user can use becomes small. At the same time, there is a possibility that the user may accidentally rewrite the data recorded in this trimming information storage area. If the trimming information is rewritten, a problem arises in that the normal operation of the memory is not guaranteed. The trimming information and the relief register are provided in the controller and are configured to be transferred to the register in a normal read operation.

SUMMARY OF THE INVENTION An object of the present invention is to record, verify, and the like into a memory device that stores trimming information, replacement information, and the like, in an electrically recordable and erasable nonvolatile memory device such as a flash memory, without providing a dedicated circuit. To make it work.

Another object of the present invention is to provide an electrically recordable / erasable nonvolatile memory device such as a flash memory, without reducing the usable storage capacity and to avoid accidental rewriting of data by the user. have.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

1 is a block diagram showing an embodiment of a flash memory as an example of an effective nonvolatile semiconductor memory device to which the present invention is applied;

2 is a circuit diagram showing an example of the configuration of a fuse replacement memory area of a memory array, a fuse register, and a peripheral circuit thereof;

3 is a timing chart showing latch timing of a fuse register in the flash memory of the embodiment;

4 is a flowchart showing a specific recording procedure of data into a fuse replacement memory area in the flash memory of the embodiment;

5 is a flowchart showing a specific recording procedure of data into a fuse replacement memory area after assembling a package in the flash memory of the embodiment;

6 is a flowchart showing a procedure from test to shipment after wafer processing of the flash memory of the embodiment;

7 is a plan explanatory view showing an example of a chip layout of a flash memory to which the present invention is applied;

8 is a circuit arrangement drawing showing an example of the configuration of a bank constituting a memory array in the flash memory of the embodiment;

9 is a block diagram showing an example of the configuration of a fuse register and a read side distribution circuit;

10 is a block diagram showing an example of the configuration of a fuse register and a write side distribution circuit;

11 is a circuit configuration diagram showing a schematic configuration of a reading router constituting a distribution circuit on the reading side;

12 is a circuit configuration diagram showing a schematic configuration of a recording router constituting a distribution circuit on the recording side;

Fig. 13 is a cross-sectional explanatory diagram showing an example of a structure of a flash memory memory cell to which the present invention is applied and an example of a bias voltage at the time of writing and erasing.

(Explanation of the sign)

11memory array

11A normal memory area

11B fuse replacement memory area (set value storage area)

12 address register

13X decoder

14Y decoder

15 Sense Amplifiers & Data Registers

16 recording circuits

17Y gate circuit

19 control circuit

20 Internal Power Supply Circuit

21 trimming circuit

25 fuse register

26 timing generating circuit

27 power-on reset circuit

30 I / O buffer circuit

31 write buffer memory

32 address buffer circuit

Brief descriptions of representative ones of the inventions disclosed herein will be given below.

In other words, the replacement information for the redundant circuit and the adjustment information of the voltage trimming circuit are stored in a part of the memory array, and the information is transferred to the latch circuit or the register when the power supply rises.

More specifically, in the nonvolatile semiconductor memory device having a memory array comprising a plurality of memory cells for changing data by applying a predetermined voltage to a selected memory cell and storing data by a difference in threshold voltage. A part of the memory array is used as a spare memory cell, and a latch circuit connected to the bit line of the memory array via a transfer switch is provided, and at least the defective bit is replaced by the spare memory cell. The replacement information can be stored, and the replacement information can be transferred to the latch circuit through the transfer switch and maintained in the memory array.

According to the above means, since it is not necessary to use a polysilicon fuse for storing replacement information for redundant circuits in a part of the original memory array, it is possible to flexibly set the replacement information and trimming information of the memory cell. For example, it is possible to record, verify, or the like to a memory device that stores replacement information or the like without using a dedicated device or providing a dedicated circuit.

Preferably, the memory array is provided with a set value storage area configured to be restricted in access in the normal operation state and to be recordable in a predetermined operation mode, and to store the replacement information in the set value storage area. . As a result, it is possible to prevent the user from rewriting the replacement information or the like by mistake without reducing the storage capacity available to the user.

Further, the replacement information stored in the memory array is configured to be transmitted to and held in the latch circuit through the transfer switch when power is turned on. As a result, when normal operation is possible, the replacement information can be kept in the latch circuit.

The latch circuit has a normal and reverse phase input terminal, and a pair of input terminals are connected to any two bit lines of the memory array, and at least connected to the two bit lines. Based on the complementary data stored in the two memory cells, the storage information is inserted and held. As a result, the latch circuit can insert data for differentially holding the data, thereby increasing the reliability of the holding data.

The transfer switch may be configured to be turned on by the reset signal supplied at the time of power supply to transfer and retain the replacement information stored in the memory array to the latch circuit. In a nonvolatile semiconductor memory device such as a flash memory, a terminal for inputting a reset signal from the outside may be provided. Therefore, the external reset signal transmits and maintains replacement information to the latch circuit to control the transfer switch. There is no need to install any new circuits or terminals.

In addition, a power-on reset circuit for detecting a rise in the power supply voltage and generating a reset signal may be provided, and the transfer switch may be configured to conduct with the reset signal generated by the power-on reset circuit. As a result, before the reset signal is externally supplied, the replacement information can be transferred to the latch circuit and held, and the replacement information is latched even if the system is configured not to input the reset signal to the semiconductor memory. Can be transferred to the circuit and maintained.

Further, an internal power supply circuit for generating a voltage used for writing and erasing data into the memory cells in the memory array, and a trimming circuit for adjusting the level of the voltage generated by the internal power supply circuit are provided. And storing the adjustment information and the replacement information of the trimming circuit, and transferring the trimming circuit to the latch circuit through the transfer switch. As a result, even when setting the adjustment information of the trimming circuit, it is not necessary to use the polysilicon fuse, thereby increasing the reliability and storing the adjustment information or the like without using a dedicated device or installing a dedicated circuit. It is possible to record and verify furnaces.

Further, a plurality of memory cells are connected to each bit line of the set value storage area, and the same data is stored in a plurality of memory cells connected to the same bit line, and the latch circuit includes the plurality of memories in which the same data is stored. The data is determined and held based on the signal read from the cell. As a result, the setting information held in the latch circuit is determined based on the storage information of the plurality of memory cells, thereby increasing the reliability of the hold data of the latch circuit.

Further, the plurality of memory cells connected to the same bit line are provided with decoder circuits which are connected to respective selection signal lines and which selectively drive these selection signal lines, and the selection signal lines are provided in the memory cells of the set value storage area. Data is sequentially written by being driven at the selection level sequentially, and the storage information of a plurality of memory cells connected to the same bit line is simultaneously transferred to the latch circuit by being driven at the selection level. In general, nonvolatile semiconductor memory devices require more current than reading. However, as described above, writing is performed in order by sequentially selecting the selection signal lines, and reading is performed in a sequential manner. Compared with this, there is no need to increase, and the reading can be performed in a short time.

In addition, an external terminal to which an externally supplied reset signal is input, the transmission switch is in a conductive state based on a reset signal generated by the power-on reset circuit or a reset signal input from the external terminal. The data stored in the set value storage area is transferred to the latch circuit for holding. As a result, the reset signal supplied from the outside and the data generated internally or stored in the set value storage area by the set signal can be transferred to the latch circuit for holding, thereby ensuring reliable data transfer.

Further, the latch circuit is provided with a switch element for enabling predetermined data to be set for the test. If no information is written to the memory cell, the state of the memory cell becomes unstable and the data to be transmitted to the latch circuit is not specified. Therefore, the test itself cannot be performed. However, by configuring the latch circuit with predetermined information, You can enter the test operation. Then, on the basis of the test result, replacement information or adjustment information may be recorded in the memory cell.

According to another invention of the present application, a threshold voltage is changed by applying a predetermined voltage to a selected memory cell, and the memory array is provided with a plurality of memory cells for storing data by a difference in threshold voltage and at the same time a spare memory cell is provided. And a latch circuit connected to a bit line of the memory array through a transfer switch, wherein the memory array stores at least replacement information for replacing a bad bit with the spare memory cell. In the nonvolatile semiconductor memory device configured to transfer the replacement information from the memory array to the latch circuit through the transfer switch, writing and reading from the wafer state to the memory array are performed to detect bad bits, Substitution information for substituting the defective bit into the spare memory cell is written into a predetermined memory cell of the memory array. Thereafter, the wafer is cut for each nonvolatile semiconductor memory chip and sealed in a package, and the package is read and written to the memory array again in this package state to detect a bad bit, thereby detecting the detected bad bit. The replacement information for substituting the memory cell in the memory array is recorded in a predetermined memory cell of the memory array, and the normal information is extracted. As a result, rescue after assembly of the package, which has not been possible in the past, becomes possible, and the yield of the product is improved.

Preferably, the replacement information recorded in the memory cell can be read outward. When the replacement information is written into the memory array in the package state, the replacement information already recorded in the memory array is read, and the information obtained by combining with the replacement information related to the newly detected bad bit is read. It is possible to write to predetermined memory cells of the memory array. As a result, it is not necessary to store the replacement information recorded in the wafer state until after the assembly of the package, and there is no possibility of accidentally recording information of another product due to a mistake in data management.

A nonvolatile semiconductor memory device comprising: an internal power supply circuit for generating a voltage used for writing and erasing data into said memory array; and a trimming circuit for adjusting the level of voltage generated by said internal power supply circuit. Determine the adjustment information of the trimming circuit by detecting the voltage generated in the internal power supply circuit in both the wafer state and the package state, and record the adjustment information of the trimming circuit together with the replacement information in the set value storage area. do. As a result, even in the case of setting the adjustment information of the trimming circuit, adjustment after assembly of the package, which has not been possible in the past, becomes possible, and the yield of the product is improved and the performance such as the recording time of the product is improved.

Another invention of the present application is a memory array provided with a spare memory cell comprising a plurality of memory cells for storing data by varying the threshold voltage by applying a predetermined voltage to the selected memory cell, and A nonvolatile semiconductor memory device having a sense amplifier sequence for amplifying a potential of a bit line in a memory array, wherein the pad array for input / output of write data and read data of the memory array is arranged along one side of a semiconductor chip on which the memory array is formed. And a latch circuit sequence is arranged between the data input / output pad array and the memory array. The latch circuit string is connected to a bit line of a memory array via a transfer switch, and replacement information for replacing a defective bit of the memory array stored in the memory array with the spare memory cell replaces the transfer switch. To be transmitted and maintained. Further, a distribution circuit is arranged between the latch circuit sequence and the data input / output pad sequence to distribute write data to the sense amplifier sequence and to distribute read data from the sense amplifier to each pad. This simplifies the installation of the wiring between the memory array and the latch circuit and between the latch circuit string and the distribution circuit.

Preferably, a set value storage area for storing the replacement information is provided on the latch circuit string side of the memory array. As a result, the distance between the set value storage area storing the replacement information and the latch circuit string in which the replacement information is transmitted is kept short, and the information can be accurately transmitted even at power up.

The memory array is composed of a plurality of banks, and a sense amplifier string is arranged between two banks, and between the bank closest to the data input / output pad sequence and the data input / output pad sequence among the banks. The latch circuit string and the distribution circuit are arranged in the. As a result, even when there are a plurality of sense amplifier strings, the latch circuit strings and the distribution circuits can be easily arranged in one place, and the chip size can be reduced.

Embodiment of the Invention

EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described using drawing.

Fig. 1 shows a block diagram of an embodiment of a flash memory as an example of a nonvolatile memory device to which the present invention is applied. Although not particularly limited, each circuit block shown in FIG. 1 is formed on one semiconductor chip such as single crystal silicon.

In FIG. 1, 11 is a memory array in which memory cells as a nonvolatile memory device composed of a MOSFET having a floating gate FG and a control gate CG separated by an insulating film as shown in FIG. Denotes an address register for holding an externally input address signal, 13 denotes an X decoder for selecting one word line corresponding to an X address inserted into the address register 12 from among word lines in the memory array 11; A Y decoder that decodes the Y address inserted into the address register 12, 15 is a sense amplifier string & data register that amplifies the potential of the bit line of the memory cell array 11 and holds externally written data; Is a recording session for recording the memory array 11 based on the recording data held in this sense amplifier string & data register 15. And 17 on the basis of the decoded signal of the Y decoder 14, a Y-gate circuit for connecting the data line in the memory array 11 in the sense amplifier and the column data register 15.

18 is an erasing control circuit for selecting a block as an erasing unit during erasing, and 19 is a process corresponding to the command based on a control signal or a command (command) code supplied from a control device such as an external microprocessor. A control circuit (sequencer) that sequentially forms and outputs control signals for each circuit in the memory for executing the circuit, 20 is a write voltage, an erase voltage, a read voltage, and a verification based on an externally supplied power supply voltage (Vcc). It is an internal power supply circuit that generates the voltage required inside the chip such as voltage. In the flash memory of this embodiment, a data input / output buffer circuit 30 for inserting an externally inputted write data signal and command code or outputting a data signal read out from the memory array 11 and amplified by a sense amplifier to the outside is provided. ) Is installed.

The control circuit 19 is provided with a command register CMD for holding a command code input from the outside. When the command code is supplied, the control circuit 19 decrypts the command code and automatically executes a corresponding process. The control circuit 19 includes, for example, a ROM (read only memory) μ-ROM in which a series of micro-command groups required to execute a command is stored, and the micro-commands corresponding to the input command code are executed in sequence so as to be internal to the chip. And to form a control signal for each circuit of the circuit. The control circuit 19 is provided with a status register STR that reflects an internal state.

Incidentally, the internal power supply circuit 20 generates a booster circuit such as a charge pump, a reference power generation circuit for generating a reference voltage such as a write voltage, an erase voltage, a read voltage, a verify voltage, and the like according to an operation state of a memory. A power switching circuit for selecting a desired voltage and supplying it to the X decoder 13, the recording circuit 16, and the like, and a power control circuit for controlling these circuits are provided. A trimming circuit 21 for adjusting the generated voltage is provided.

The data input / output buffer circuit 30 is connected to the input / output terminals I / O0 to I / O15, and is configured to input and output data and commands in units of 16 bits or 8 bits, for example, by time division. In addition, a write buffer memory 31 is provided which can hold the write data which is input from the outside and written into the memory cell connected to one word line. 1, 32 is an address buffer for inserting an externally input address signal ADD, 41 is a power supply voltage terminal to which a power supply voltage Vcc is applied from the outside, and 42 is the same as the ground potential Vss. The power supply voltage terminal (ground terminal).

As a control signal input to the flash memory of this embodiment from an external CPU or the like, for example, a reset signal RES, a chip select signal CE, a write control signal WE, an output control signal OE, a command input or a data input are input. The command enable signal CDE, the system clock SC, and the like are shown. Commands and addresses are inserted into the command register CMD and the address register 12 by the data input / output buffer circuit 30 and the address buffer 31 in accordance with the command enable signal CDE and the write control signal WE. The write data is inserted into the data input / output buffer circuit 30 in synchronization with the system clock SC when the command enable signal CDE indicates data input. In this embodiment, the ready / busy R / B indicating whether or not externally accessible is made to the external terminal 43 according to a predetermined bit of the status register STR reflecting the state inside the memory. It is configured to output.

Further, in the flash memory of this embodiment, in addition to the normal memory area 11A, the fuse replacement memory area 11B serving as a set value storage area made of the same nonvolatile memory element is provided in the memory array 11, The fuse register 25 holding the set value read out from the fuse replacement memory area 11B, the timing generating circuit 26 for generating the control timing signal of the fuse register 25, and the rise of the power supply voltage are detected. A power-on reset circuit 27 for generating a reset signal POR for activating the timing generating circuit 26 is provided. The information stored in the fuse replacement memory area 11B includes information on replacement of the spare memory cell in the redundant circuit, trimming information in the internal power supply circuit 20, and how many volts of the voltage the memory operates. Product specification information indicating the product specification.

Although not shown in FIG. 1, the memory array 11 is provided with a spare memory string constituting a redundant circuit. Regarding the row direction, a spare memory row is provided for replacing a memory row including a bad bit. The X decoder 13 is provided with a redundant decoder for switching memory rows in accordance with the replacement information stored in the fuse replacement memory area 11B. In the data input / output buffer circuit 30, when an address specifying a memory string including bad bits is externally input, the data input / output buffer circuit 30 stores the data in the memory array 11 in accordance with the replacement information stored in the fuse replacement memory area 11B. A circuit for converting a defective memory string into a spare memory string is provided. These replacement information stored in the fuse replacement memory area 11B is once inserted into the fuse register 25 and supplied to the X decoder and the data input / output buffer circuit 30 to be provided for switching to the reserved memory row or the reserved memory column. do.

The trimming information stored in the fuse replacement memory area 11B is provided for adjustment in the trimming circuit 21 inserted into the fuse register 25 and accompanying the internal power supply circuit 20, so as to adjust the generated voltage. Adjustment and adjustment of the recording pulse width are performed. The specification information stored in the fuse replacement memory area 11B is inserted into the fuse register 25 and supplied to the control circuit 19, and the timing of the control signal supplied from the control circuit 19 to each circuit is, for example, Adjustments are made so as to delay when the power supply voltage is low and to accelerate when the power supply voltage is high.

2 shows a schematic configuration of the fuse replacement memory area 11B, the fuse register 25 and the peripheral circuits of the memory array 11. The fuse replacement memory area 11B of the memory array 11 has the same configuration as the normal memory area 11A, and a plurality of memory cells MC are arranged in a matrix in the fuse replacement memory area 11B. The control gates of the same row memory cells are connected to common word lines WL1 to WL16, respectively. Although not particularly limited, 2048 + 64 memory cells (hereinafter, referred to as one sector) are arranged in the row direction. Here, "64" of "2048 + 64" is the number of spare memory columns for redundant circuits.

The memory cells MC in the same column of the fuse replacement memory area 11B are connected to common sub bit lines SBi, SBi + 1, ..., in 16 units, and the sub bit lines SBi, SBi. + 1 …… are connected to the main bit lines MBi, MBi + 1 …… common with the normal memory area 11A via the selection switch MOSFETs Qsi, Qsi + 1 ……. Here, the symbols i and i + 1 appended to the sub bit line SB and the main bit line MB are codes for identifying the bit lines of the respective columns. In this embodiment, i is 1 to ( 2048 + 64).

Note that the selection switch MOSFETs Qsi, Qsi + 1 ... are not X decoders 13 that generate on / off control signals of the same selection switch MOSFETs Qs in the normal memory area 11A, but are tested. It is controlled on and off by an X decoder 13B which is activated by a control signal such as a mode signal TEST, and the like is applied to a Y gate circuit, a sense amplifier string, and a write circuit for a normal memory area 11A during the test mode. In this way, recording and erasing are performed through the main bit lines MBi, MBi + 1, ..., common to the normal memory area 11A.

The source of each memory cell in the fuse replacement memory area 11B is the same as the normal memory area 11A, and 16x (2048) having 16 memory cells in the column direction and word lines WL1 to WL16 in common. It is connected to the common source line SL which supplies a ground potential in +64 units (this is called 1 memory block in this specification). The switch SW is provided in the source line SL, and the ground potential can be applied to the source of the memory cell or the source can be opened. Each word line WL1 to WL16 of the fuse replacement memory area 11B is configured such that any one of them is selectively selected by the X decoder 13B.

However, the X decoder 13B operates as the original decoder only in the test mode by the control signal TEST, and is deactivated in the normal operation other than the test mode to fix the word line to the non-selection level. When the power supply rises, the word lines WL1 to WL16 of the fuse replacement memory area 11B are set to the selected level. These operations will be described later in detail.

In addition, the other end of the sub bit lines SBi, SBi + 1 …… of the fuse replacement memory area 11B forms a fuse register 25 through the transfer MOSFETs Qti, Qti + 1 ……. It is connected to the input / output node of (LT). In this embodiment, replacement information and trimming information are actually stored in the memory sequence of the fuse replacement memory area 11B in part of 2048 (for example, 512 pieces). Therefore, the transfer MOSFETs Qti, Qti + 1 …… and the latch circuit LT are provided not in all of the subbit lines SBi, SBi + 1 ……, but in two or four crossings. The bit lines, in which the transfer MOSFETs Qti, Qti + 1 ..., and the latch circuit LT are not provided, and the memory cells connected thereto are in an unused state. Instead of leaving it in an unused state, it may be left without forming it in advance.

In this embodiment, two sub bit lines SBi and SBi + 1 in which the fuse replacement memory area 11B are adjacent to each other are paired, and one of the bit lines SBi is a latch circuit LT. Is connected to one (reverse) input / output node (n1), and the other bit line (SBi + 1) is connected to the other (normal) input / output node (n2) of the latch circuit (LT). ), And is configured to insert data of the memory cells of the fuse replacement memory area 11B into the latch circuit LT in a differential manner.

The sub-bit lines SBi, SBi + 1, ..., of the fuse replacement memory area 11B are connected with load MOSFETs Qdi, Qdi + 1, ... serving as a load to the memory cells. As the word line WL of the replacement memory area 11B is at a selection level for data loading to the latch circuit and the transfer MOSFETs Qti, Qti + 1, ... are conducted, the load MOSFETs Qdi, Qdi + 1 ... is turned on. These load MOSFETs Qdi, Qdi + 1 ...... and the transfer MOSFETs Qti, Qti + 1 ...... may be turned on by the same timing signal .phi.1. However, Qd and Qt do not necessarily have to be turned on at the same timing.

The latch circuit LT includes a flip-flop FF formed by cross-coupling input / output terminals of a pair of CMOS inverters, a power switch MOSFET Qp1 and an N-MOS side connected to the P-MOS side of the flip-flop. And a potential supplied to the input / output nodes n1 and n2 when Qp1 and Qn1 are turned on by the timing signal φ1 and the signal inverted by the inverter INV. If the difference between the signals is amplified and Qp1 and Qn1 are turned off by? 1, the operation is performed so that the hold state is maintained.

In addition, when no information is recorded in the memory cell of the fuse replacement memory area 11B, the state of the memory cell becomes unstable, and since the data transmitted to the latch circuit is not specified, the test itself cannot be performed. Therefore, in this embodiment, a register MOSFET for setting trimming data is provided in the control circuit 19, and at the same time, a switch MOSFET for enabling setting of predetermined data for testing in the latch circuit LT ( Qri) is provided, and in the test mode before the trimming information is determined, the data set in the trimming register TMR is transferred to the latch circuit LT and supplied to the trimming circuit 21 for testing. After the information is written into the fuse replacement memory area 11B, it is configured to use the data transferred from the fuse replacement memory area 11B to the latch circuit LT.

Instead of providing a switching switch for selectively transferring the data set in the trimming register TMR or the data set in the latch circuit LT to the trimming circuit 21, or instead of installing the trimming register TMR, a test is performed. Before starting, the provisional trimming data for test can be transmitted to the latch circuit LT directly from the outside, or a reset switch element is provided in the latch circuit LT, so that all of the setting data is set to "0." It may be configured to be in the state "."

Next, the operation at the time of power up of the fuse replacement memory area 11B and the latch circuit LT will be briefly described using the timing chart of FIG. When the power supply voltage Vcc of the flash memory chip rises as shown in Fig. 3A, the power-on reset circuit 27 detects this and generates a power-on reset signal POR as shown in Fig. 3B. . Then, the timing signal φ1 as shown in FIG. 3C is output from the timing generation circuit 26, and the X decoder circuit 13B causes the word lines WL1 to ˜1 of the fuse replacement memory region 11B to be output. At the same time, the WL16 is changed to the selection level at the same time, and the load MOSFETs Qdi, Qdi + 1 …… and the transfer MOSFETs Qti, Qti + 1 …… are turned on.

As a result, a current flows from the load MOSFETs Qdi, Qdi + 1 …… to the memory cells in the fuse replacement memory region 11B, and the sub-bit line SBi depends on the state (threshold voltage level) of the memory cell at that time. , SBi + 1 ...) changes. Then, the potential difference between the paired sub-bit lines SBi, SBi + 1 ...... is transmitted to the corresponding latch circuit LT, respectively.

The transfer MOSFETs Qti, Qti + 1 ...... are turned on to allow data to be transferred from the fuse replacement memory area 11B to the latch circuit LT.

On the other hand, following the rise of the timing signal φ1 to the high level, the timing signal φ2 as shown in FIG. 3D is output from the timing generating circuit 26, and this signal φ2 becomes the high level. When the latch circuit LT is inactive, the potential difference between the sub-bit lines SBi, SBi + 1 ... is transmitted to the nodes n1, n2, and the timing signal φ2 changes to the low level. Accordingly, the latch circuit LT is activated, so that the potential difference between the nodes is amplified and maintained by the latch circuit LT.

In addition, in this embodiment, the timing generating circuit 26 generates the timing signals φ1 and φ2 even when the reset signal RES is externally inputted to generate the memory cells in the fuse replacement memory region 11B. Is configured to reload the fuse setting data stored in the corresponding latch circuit LT, respectively. In this manner, the fuse setting data is loaded into the fuse register 25 by the power-on reset signal POR and the external reset signal RES, respectively, so that the reliability of the retention data of the fuse register 25 can be improved.

Although not particularly limited, in the flash memory of this embodiment, a positive high voltage (e.g., + 10V) is applied to the control gate CG (word line WL) at the time of writing, as shown in Fig. 13A. In the applied state, 0 V is applied to the source of the memory cell to which the threshold voltage is to be raised and 6 V is applied to the drain, for example, to cause a drain current to flow through the channel, and the generated hot electron is injected into the floating gate FG to increase the threshold voltage. . Therefore, the bit line to which the memory cell (for example, data " 1 ") to which the threshold voltage is to be raised is connected to the sub bit line SB in accordance with the write data. At this time, in this embodiment, the potential of the well region WELL is -2V in this embodiment, but may be another potential (for example, 0V). On the other hand, 0 V is applied to the sub-bit line SB to which memory cells (for example, data "0") that do not want to increase the threshold voltage are connected. At the time of writing, the source of each selected memory cell is 0V. In addition, this writing operation is performed in units of 8-bit bytes or units of 16-bit words, for example. However, it is also possible to record while shifting by 1 bit.

On the other hand, during data erasing, as shown in FIG. 13B, a negative high voltage (eg, -16V) is applied to the control gate CG (word line WL) and a constant voltage of 0 to 10V is applied to the well region. Is applied to extract negative charges from the floating gate (FG) of the memory cell by the FN tunnel phenomenon to lower the threshold voltage. At the time of erasing, the drain (subbit line SB) and the source (common source line SL) are open, i.e., floating in potential.

Next, a specific recording procedure of data (fuse setting value) in the fuse replacement memory area 11B will be described with reference to the flowchart of FIG. This flowchart shows the control procedure by the control circuit 19 of the flash memory.

Although not particularly limited, in the flash memory of this embodiment, data is written into the fuse replacement memory area 11B by inputting a predetermined command code (fuse replacement memory area access command) that is not open to the user in the test mode. It is configured so that reading can be performed. Therefore, the data is set in the fuse replacement memory area 11B according to this flowchart, for example, by using a tester at the time of probe inspection. In addition, even in the test mode, the write command, the read command, and the erase command in common with the normal operation are valid, and the write or read is started by the input of the command.

The flowchart of Fig. 4 is started by inputting a test command and a fuse replacement memory area access command to a flash memory from an external tester or the like. When the control circuit 19 decodes the command input in the test mode and recognizes that the command is a fuse replacement memory area access command, the control circuit 19 deactivates the X decoder 13A of the normal memory area 11A, and the fuse replacement memory area ( The fuse replacement memory area 11B is selected by activating the X decoder 13B of 11B) (step S1).

Next, the control circuit 19 applies the negative voltage (e.g., -16V) to all the word lines WL1 to WL16 of the fuse replacement memory area 11B by the X decoder 13B, and at the same time the erase circuit 18 The sub bit line SB and the common source line SL are opened (floating), and all memory cells of the fuse replacement memory area 11B are once erased (the threshold corresponding to the data "0"). The voltage is low) (step S3).

Thereafter, the word lines WL1 to WL16 are sequentially set to the selection level (potential slightly lower than the middle of the high and low threshold voltages of the memory cell) for verification reading, and the sense amplifier string & data register 15 Is activated to read the data, and it is determined by an external tester whether the threshold voltage Vth of all the memory cells in the fuse replacement memory area 11B is lower than the erase verification voltage VWE1 (step S3). If any one of the memory cells has a threshold voltage higher than that of VWE1, the process returns to step S2 to perform the erase operation again. Further, in this embodiment, the verification readout is configured to be performed continuously in writing without a command. However, the verification readout may be performed by inputting a verification command externally.

On the other hand, when it is determined in step S3 that the threshold voltages Vth of all the memory cells are lower than VWE1, the process proceeds to step S4 to write data to the fuse replacement memory area 11B. Further, before this writing, a so-called rewrite operation may be performed in which the threshold voltage of the memory cell in which the threshold voltage is excessively lowered in the erase operation is slightly raised. The recording in step S4 is performed by setting the write command to the command register CMD and setting the write data, that is, the fuse set value to the sense amplifier string & data register 15.

As a result, the control circuit 19 applies the high voltage (for example, 16V) in order to the word lines WL1 to WL16 of the fuse replacement memory area 11B by the X decoder 13B, and at the same time, the switch SW Is turned on to apply 0V to the common source line SL, and to the sub-bit line SB to which a memory cell intended to increase the threshold voltage corresponding to data " 1 " set in the sense amplifier string & data register 15 is connected. For example, a voltage (0 V) for preventing writing is applied to a sub-bit line SB to which a memory cell to which 6 V is not desired and a threshold voltage corresponding to data "0" is not connected is connected. In other words, in this embodiment, the same data is sequentially written to sixteen memory cells in the same column.

In this embodiment, when the recording data of the memory cells in the odd column is the original setting data, the complementary data is recorded in the memory cells of the even column. When the current supply capability of the internal power supply circuit 20 is sufficient, or when the memory capacity of the fuse replacement memory area 11B is small, the plurality of word lines are set as the selection level to target the plurality of memory rows. It is also possible to record simultaneously.

Subsequently, the word lines WL1 to WL16 are sequentially set to a selection level (potential between the high and low threshold voltages of the memory cell) for verifying and reading the word lines WL1 to WL16, and the sense amplifier string & data register 15 is activated. The data is read, and it is determined whether or not the threshold voltage Vth of the memory cell corresponding to the write data "1" is higher than the write verify voltage VWV (step S5). When there are memory cells with a threshold voltage lower than VWV among the memory cells to be written, the process returns to step S4 to perform writing again. Note that the recorded data at this time is the recorded data reproduced by an external tester or the like on the basis of the data read by the verification (data set with only unrecorded bits set to "1"). If it is determined in step S5 that the threshold voltage Vth of all the memory cells corresponding to the write data "1" is higher than the verification voltage VWV, the fuse setting process is terminated.

As described above, in the flash memory of the present embodiment, the same data is recorded in 16 memory cells in the same column. When the power supply rises, the fuse replacement memory area 11B word lines WL1 to WL16 are set to the selected level so that the memory data of all the memory cells is transferred to the latch circuit LT of the fuse register 25 and stored. Data obtained by majority vote of the stored data of the memory cell is stored. In addition, complementary data is stored in the odd and even columns, and the latch circuit LT of the fuse register 25 amplifies differentially to latch the data.

When the power supply rises, the power supply voltage is not determined and the level of the read data in the memory cell is not sufficient, so that the high reliability value is maintained in the fuse register 25 by taking a majority vote as described above and differentially detecting it. do. As described above, when the reset signal RES is input from the outside after the power is completely raised, the set value from the memory array 11 to the fuse register 25 is again loaded, so that the subsequent holding data is more reliable. It becomes. However, in the flash memory of this embodiment, it is possible to load a relatively reliable set value into the fuse register 25 even when the reset signal RES is not input or before input.

In the flash memory of this embodiment, even after the chip is assembled into a package, data setting and setting values can be changed in the fuse replacement memory area 11B. 5 shows a specific recording procedure of data (fuse set value) to the fuse replacement memory area 11B after assembling the package. This procedure is almost the same as the procedure at the probe inspection of FIG. 4. The only difference is that the data is read (step S1-1) from the fuse replacement memory area 11B before the step S2 of FIG. 4 is erased. The external tester can synthesize the reset data from the read data and the new setting data.

Since the flash memory has a structure in which data is erased in units of memory blocks, when a bad bit is newly detected after package assembly and it is necessary to rewrite the data in the fuse replacement memory area 11B, the already set value is recorded. It is reasonable to read and to take the logical sum with the new setpoint and synthesize the reset data. In the flash memory of the embodiment, when rewriting the fuse replacement memory area 11B, the reset data can be easily synthesized by reading the setting data already stored before erasing the data. This has the advantage that the data recorded in the fuse replacement memory area 11B in the wafer stage need not be stored for each chip, and there is no possibility of accidentally combining data with other chips.

6 shows a procedure from test to shipment after the wafer process of the flash memory to which the present invention is applied.

When the flash memory to which the present invention is applied ends in the wafer process, the probe inspection is first performed in the wafer state (step S11). Then, on the basis of the inspection result, it is determined whether or not remedies are possible, and if possible, setting of replacement information to the fuse replacement memory area and setting of trimming information are performed (steps S12 and S13). Then, a probe test (step S14) is performed to see if the set value is valid. If not, the process returns to step S13 and the fuse replacement memory area is set again. If so, the process proceeds to step S15.

In step S15, each chip is cut out from the wafer and assembled into a package. Then, a screening test using a tester is performed (step S16). Based on the test results, it is determined whether or not a new relief is necessary and whether or not the trimming information needs to be changed. If necessary, the replacement information is set in the fuse replacement memory area and the trimming information is set (steps S17, S18). ). Then, a retest (step S19) is performed to determine whether or not the set value is valid. If not, the process returns to step S18 to set the fuse replacement memory area again, and if it is, it is shipped as a good product.

As described above, in the flash memory to which the present invention is applied, remedy after assembly of the package and resetting of trimming information (step S18), which have not been possible in the past, can be performed, thereby improving product yield and reliability, Since the optimization can be performed more accurately, there is an advantage that the recording time is shortened.

7 shows an example of a chip layout of a flash memory to which the present invention is applied. In the figure, reference numeral 100 denotes a semiconductor chip such as single crystal silicon, 11 denotes a memory array formed on the chip 100. In this embodiment, the memory array 11 is composed of four banks BNK1 to BNK4. The Y gate circuit 17, the sense amplifier string 15 and the recording circuit 16 are disposed between BNK1 and BNK3 and between BNK2 and BNK4, respectively, and at the same time, an X decoder ( 13 is disposed outside the control circuit 19, the internal power supply circuit 20, the address register 12, the Y decoder 14, the erase circuit 18, and the timing generating circuit 26 in FIG. The peripheral circuit 50 of the back is arrange | positioned.

Pad rows PD1 and PD2 are provided along both sides of the chip 100, of which PD1 is mainly a pad for data input / output, and PD2 is mainly a pad for address input. Although not shown, an input / output buffer is disposed in the vicinity of each pad. In addition, in the present embodiment, the fuse replacement memory area 11B and the fuse register 25 are provided on the side close to the pad string PD1 of the bank BNK1. Between PD1, the write data inserted by the input buffer is distributed to the sense amplifier string & data register 15 in accordance with the data read from the fuse register 25 to the fuse replacement memory area 11B. A circuit 60 for distributing the read data amplified by the amplifier string to the data input / output pads is provided.

For example, as shown in FIG. 8, each bank is divided into 16 I / O sets (IOS0 to IOS15) in 128 columns along the row direction, and 16 bits in total by 1 bit in each I / O set by one column address. Is configured to be read or written to the common data line CDL. Hereinafter, the column address which designates one out of 128 columns is called a unit address. Each of the 16 I / O sets IOS0 to IOS15 is provided with two redundant relief circuits RDD1 and RDD2 each consisting of 32 preliminary memory columns. In Fig. 8, reference numeral RDD3 denotes a redundant rescue circuit composed of spare memory rows in the word line direction.

9 shows an example of the configuration of the fuse register 25 and the distribution circuit 60. In the figure, DOB0 to 7, DOB8 to 15 are data output buffers connected to data input / output terminals (I / O0 to 7, I / O8 to 15, respectively), and SEL10 and SEL20 are data set in the fuse register 25. The selector selects the data corresponding to the bank address BA and the unit address UA and supplies them to the read routers RRT1 and RRT2.

As a result, when the replacement information corresponding to the address is held in the fuse register 25 when the memory array is accessed by access, the replacement information is automatically set by the selector SEL10 and SEL20 for the read router RRT1. , RRT2). In addition, in this embodiment, when there is no bad bit, information corresponding to "none" is stored in the corresponding fuse replacement memory area 11B, which is read into the fuse register 25 when the power supply rises. .

The information supplied from the fuse register 25 to the selectors SEL10 and SEL20 is, for example, 7 bits, 3 bits of which are information indicating a location of a bad bit of 8 bits of data, and 2 bits of each I of the memory array. The information specifying the sense amplifier to be used among the four sense amplifiers provided corresponding to the / O set, and the remaining two bits are information (enable bits) indicating whether or not replacement information for redundancy relief is set. There are two bits for the enable bit in order to ensure accuracy, and in principle, only one bit is required. Also, information specifying the sense amplifier is not necessary depending on the configuration of the peripheral circuit.

As shown in Fig. 9, the number of signal lines from the data input / output terminals I / O0 to 7, I / O8 to 15 to the read routers RRT1 and RRT2 is 16, but the read routers RRT1 and RRT2 are used. The number of signal lines from to the memory array 11 is 18, 16 of which are common data lines corresponding to the regular memory strings, and the remaining two are redundant common data lines corresponding to the spare memory strings.

The reading routers RRT1 and RRT2 are configured to output correct read data by switching the regular common data line and redundant common data line in accordance with the setting data held in the fuse register 25. The readout routers RRT1 and RRT2 are provided in correspondence with each of the I / O sets of the memory arrays supplied from the fuse register 25 through the lower bits A0 and A1 of the address and the selectors SEL10 and SEL20. Of the four sense amplifiers, two bits of information specifying the sense amplifier to be used are compared, and when they match, the normal common data line and the redundant common data line are switched. This replacement is performed based on three bits of information indicating the position of the bad bit when the enable bit in the seven bits supplied from the fuse register 25 described above is at an effective level, and the data to be replaced is input and output. Output to terminals I / O0 ~ 15.

In Fig. 10, the write data input from the data input / output terminals (I / O0 to 7, I / O8 to 15) is converted into a regular common data line and redundant common data line according to the data set in the fuse register 25. An example of the configuration of the distribution circuit 60 including the write routers WRT1 and WRT2 for switching the circuits and skipping the signal lines corresponding to the transmission or defective memory columns and shifting them to adjacent signal lines is shown.

The circuit on the recording side of FIG. 10 is almost the same as the circuit on the reading side of FIG. The other is that the direction of data is reversed, and the recording buffer memory 31 which holds the recording data between the data input buffers DIF0 to 7, DIF8 to 15 and the routers WRT1 and WRT2 for recording. ) Is installed. The write buffer memory 31 is configured to have a storage capacity of 2048 bits corresponding to the number 2048 of regular memory cells of one sector. In recording, one sector of data is externally inserted into the recording buffer memory 31 in units of 16 bits, and the sense amplifier string & data is stored in the recording buffer memory 31 through the recording routers WRT1 and WRT2. The register 15 is configured to transmit 2048 + 64 bits of data including redundant bits.

As described above, in the flash memory of the present embodiment, the fuse register 25 is disposed on the side close to the data input / output terminals I / O0 to 7, I / O8 to 15, and the fuse register 25 and the pad are also used. Since the distribution circuit 60 is provided between the columns PD1, the wiring can be easily installed and the wiring length is also shortened. In addition, since the distribution circuit 60 is disposed in the vicinity of the fuse resistor 25, there is an advantage that the signal can be transmitted and distributed smoothly. In other words, the distribution circuit 60 may be located in the vicinity of the sense amplifier column. However, in the case where the sense amplifier columns are distributed in two or more places as in the present embodiment, the distribution circuit is also distributed, so that the wiring is complicated. Although it is installed on the side close to the data input / output terminals I / O0-7, I / O8-15, it can concentrate in one place and can install wiring easily by this.

The recording buffer memory 31 shown in FIG. 10 may be disposed between the data input / output terminals I / O0 to 7, I / O8 to 15 and the recording routers WRT1 and WRT2. The peripheral circuit 50 shown may be disposed at the pad row PD1 side, that is, at the upper left corner of the chip 100.

11 shows a schematic configuration of the read router RRT1. In the drawing, SEL1 to SEL8 are selectors for passing 1 bit of a 2-bit input signal, 61 is to decode the setting data supplied from the fuse register 25 through the selector SEL10 to decode the selectors SEL1 to SEL8. The decoder generates the switching control signals S1 to S8. Among the selectors SEL1 to SEL8, any Bi (i = 0) of each bit B0 to B7 of 1 byte of data read from the memory array and supplied through the common data line CDL is input to the input terminals of the SEL1 to SEL7. , 1, 2, ..., ..., and redundant bits Br in the redundant memory columns of redundant recovery circuit RD1 or RDD2 are commonly input. Then, the selector corresponding to the bad bit among the selectors SEL1 to SEL8 is switched by the control signals S1 to S8 of the decoder 61, and the redundant bit Br is selected instead of the bad bit, so that the total of 8 bits is selected. It is output as signals D0 to D7.

In FIG. 11, as an example, the signal selected by the selectors SEL1 to SEL8 when the bit B5 is defective is indicated by a thick line. That is, the selectors SEL1 to SEL5 and SEL7 and SEL8 of the selectors SEL1 to SEL8 select bits B0 to B4 and B6 and B7 of the normal memory string, respectively, and the selector SEL6 selects the redundant bit Br. The shape is shown.

Similarly, the read router RRT2 is supplied with 9 bits of read data (B8 to B15, Br) including redundant bits, and 8 bits are selected and output according to the setting data of the fuse register 25. . If no defect is included in the regular 8 bits, no replacement information is set in the fuse register 25, and the decoder 61 generates the switching control signals S1 to S8 for selecting the regular 8 bits. To the selectors SEL1 to SEL8.

As shown in Fig. 12, the recording routers WRT1 and WRT2 are configured such that the data transfer directions of the reading routers RRT1 and RRT2 are reversed.

As mentioned above, although the invention made by this inventor was demonstrated concretely based on the Example, it cannot be overemphasized that this invention is not limited to the said Example and can be variously changed in the range which does not deviate from the summary. For example, in the embodiment, the flash memory has been described in which the threshold voltage of the memory cell is lowered by erasing and the threshold voltage of the memory cell is raised by writing. However, the present invention raises the threshold voltage of the memory cell by erasing. Therefore, the present invention can also be applied to a flash memory of lowering the threshold voltage of the memory cell.

In the above embodiment, the writing to the memory device having the floating gate is performed by hot electrons generated by flowing the drain current, and the erasing is performed by using the FN tunnel phenomenon. The same applies to a flash memory configured to be used. Also, in the above embodiment, the case where the bad memory bit is re-entered by the router in accordance with the replacement information has been described in the above embodiment. However, the spare memory string is changed to the address of the spare memory string as in the spare memory row. It is also possible to configure the Y decoder to select.

In the above description, the case where the invention made by the present inventors is mainly applied to the flash memory which is the background of use is applied. However, the present invention is not limited thereto, and the present invention is not limited thereto. The semiconductor memory device can be widely used for a semiconductor memory having a nonvolatile memory device for storing memory.

The effects obtained by the representative ones of the inventions disclosed herein will be briefly described as follows.

That is, according to the present invention, in an electrically recordable / erasable nonvolatile memory device such as a flash memory, recording or verification, etc., to a storage element that stores trimming information, replacement information, and the like can be performed without providing a dedicated circuit. At the same time, the memory capacity available to the user can be reduced, and the user can avoid accidentally rewriting the data.

Claims (17)

A nonvolatile semiconductor memory device having a memory array comprising a plurality of memory cells that change a threshold voltage by applying a predetermined voltage to a selected memory cell and store data by a difference in the threshold voltage. At the same time a part of the memory array is used as a spare memory cell, A latch circuit connected to a bit line of the memory array via a transfer switch, wherein the memory array can store replacement information for replacing at least a bad bit with the spare memory cell, and the replacement information is stored in the memory array. And a nonvolatile semiconductor memory device configured to be transferred from the array to the latch circuit through the transfer switch so as to be retained. The method of claim 1, The memory array is provided with a set value storage area configured to be restricted in access in a normal operation state and to be recordable in a predetermined operation mode, and to store the replacement information in the set value storage area. Volatile Semiconductor Memory. The method of claim 2, And the substitution information stored in the memory array is transmitted to and held by the latch circuit through the transfer switch when power is turned on. The method of claim 3, wherein The latch circuit has input terminals of normal and reverse phase, each input terminal of which is connected to any two bit lines of the memory array, and at least two memories connected to the two bit lines. A nonvolatile semiconductor memory device, comprising: storing and inserting storage information based on complementary data stored in a cell. The method of claim 4, wherein And the transfer switch is configured to transfer and maintain replacement information stored in the memory array to the latch circuit, which is conducted by a reset signal supplied at power-on, to the latch circuit. The method of claim 5, And a power-on reset circuit for generating a reset signal by detecting a rise in power supply voltage, wherein the transfer switch is configured to be conducted by a reset signal generated by the power-on reset circuit. Device. The method of claim 6, An internal power supply circuit for generating a voltage used for writing and erasing data into the memory cells in said memory array, and a trimming circuit for adjusting the level of the voltage generated by said internal power supply circuit, and storing in said memory array. And the data transmitted to the latch circuit through the transfer switch are adjustment information and replacement information of the trimming circuit. The method of claim 7, wherein A plurality of memory cells are connected to each bit line of the set value storage area, and the same data is stored in a plurality of memory cells connected to the same bit line, and the latch circuit is used in the plurality of memory cells in which the same data is stored. A nonvolatile semiconductor memory device, characterized in that it is configured to hold data based on a read signal. The method of claim 8, The plurality of memory cells connected to the same bit line are provided with decoder circuits which are connected to separate selection signal lines, respectively, and selectively drive these selection signal lines, and the selection signal lines are sequentially selected in the memory cells of the set value storage area. The information is sequentially written by being driven at a level, and the storage information of a plurality of memory cells connected to the same bit line is simultaneously transferred to the latch circuit as the selection signal lines are simultaneously driven to the selection level. Semiconductor memory device. The method of claim 6, An external terminal to which an externally supplied reset signal is input, and the transfer switch is in a conductive state based on a reset signal generated by the power-on reset circuit or a reset signal input from the external terminal, and stores the set value. A nonvolatile semiconductor memory device, characterized in that it is configured to transfer and hold information stored in an area to said latch circuit. The method of claim 10, And the latch circuit comprises a switch element for enabling predetermined data to be set for a test. By applying a predetermined voltage to the selected memory cell, the threshold voltage is changed and a plurality of memory cells for storing data according to the difference in the threshold voltage, and a memory array provided with a spare memory cell and a bit line of the memory array And a latch circuit connected through a transfer switch, wherein the memory array stores at least replacement information for replacing a bad bit with the spare memory cell, and the substitution information is stored in the memory array through the transfer switch. A method of manufacturing a nonvolatile semiconductor memory device configured to be transmitted to a circuit and held therein, After writing and reading from the memory array in the wafer state to detect a bad bit, and writing replacement information for replacing the detected bad bit with the spare memory cell in a predetermined memory cell of the memory array, The wafer is cut for each nonvolatile semiconductor memory chip and enclosed in a package, and in this package state, writing and reading into the memory array are performed to detect bad bits, and the detected bad bits are transferred to the spare memory cells. A method of manufacturing a nonvolatile semiconductor memory device, characterized in that for extracting replacement information for replacement in a predetermined memory cell of said memory array and extracting the normal recording. The method of claim 12, At the time of recording the replacement information into the memory array in the package state, the information obtained by reading the replacement information already recorded in the memory array and combining the replacement information with the newly detected bad bit is combined with the memory array. A method of manufacturing a nonvolatile semiconductor memory device, characterized in that writing to a predetermined memory cell. The method of claim 13, A method of manufacturing a nonvolatile semiconductor memory device comprising an internal power supply circuit for generating a voltage used for writing and erasing data into said memory array, and a trimming circuit for adjusting the level of voltage generated by said internal power supply circuit. And detecting the voltage generated by the internal power supply circuit in the wafer state or the package state to determine the adjustment information of the trimming circuit, and recording the adjustment information of the trimming circuit together with the replacement information in the set value storage area. A method of manufacturing a nonvolatile semiconductor memory device. A memory array comprising a plurality of memory cells that store data by changing a threshold voltage by applying a predetermined voltage to a selected memory cell and storing data due to a difference in threshold voltage, and a potential at a bit line in the memory array. A nonvolatile semiconductor memory device having a sense amplifier train for amplifying A pad array for input / output of write data and read data of the memory array is disposed along one side of the semiconductor chip on which the memory array is formed, and a bit of the memory array is interposed between the data input / output pad array and the memory array. A latch circuit sequence, which is connected to a line via a transfer switch and replaces defective bits of the memory array stored in the memory array with the spare memory cell, is transferred and held through the transfer switch; A nonvolatile semiconductor, wherein a distribution circuit is arranged between the latch circuit sequence and the data input / output pad sequence to distribute write data to the sense amplifier sequence and to distribute read data from the sense amplifier to each pad. Memory. The method of claim 15, A nonvolatile semiconductor memory device, characterized in that a set value storage area for storing said replacement information is provided on said latch circuit string side of said memory array. The method of claim 16, The memory array is composed of a plurality of banks, each of which has a sense amplifier string disposed therebetween, and between a bank closest to the data input / output pad row and the data input / output pad row among the banks. And a latch circuit array arranged thereon.