KR20020002164A - Method of forming isolation layer of semiconductor device - Google Patents
Method of forming isolation layer of semiconductor device Download PDFInfo
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- KR20020002164A KR20020002164A KR1020000036649A KR20000036649A KR20020002164A KR 20020002164 A KR20020002164 A KR 20020002164A KR 1020000036649 A KR1020000036649 A KR 1020000036649A KR 20000036649 A KR20000036649 A KR 20000036649A KR 20020002164 A KR20020002164 A KR 20020002164A
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- film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000002955 isolation Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 150000004767 nitrides Chemical class 0.000 claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 239000000126 substance Substances 0.000 claims abstract description 11
- 238000007517 polishing process Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims description 16
- 230000002265 prevention Effects 0.000 claims description 13
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000000903 blocking effect Effects 0.000 abstract 5
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 소자분리막 형성방법에 관한 것으로써, 보다 자세하게는 반도체기판 내에 트렌치부를 형성하고, 상기 트렌치부를 산화막으로 채운 후, 그상부에 디싱방지막을 형성함으로써, 이에 화학적 기계적 연마공정을 이용한 평탄화공정을 시행할 때, 디싱현상이 방지되어 반도체소자의 특성 및 신뢰도를 향상시킬 수 있도록 한 반도체 소자분리막의 형성방법에 관한 것이다.The present invention relates to a method of forming a semiconductor device isolation film, and more particularly, to form a trench in a semiconductor substrate, fill the trench with an oxide film, and then form a dishing prevention film thereon, thereby forming a planarization process using a chemical mechanical polishing process. The present invention relates to a method of forming a semiconductor device isolation film that prevents dishing from occurring to improve characteristics and reliability of a semiconductor device.
최근에는 반도체장치의 고집적화 추세에 따라 미세화 기술 중의 하나인 소자분리기술의 연구개발이 활발하게 진행되고 있다.Recently, according to the trend of high integration of semiconductor devices, research and development of device isolation technology, which is one of the miniaturization technologies, has been actively conducted.
소자분리영역을 형성하는 것은 모든 제조공정 단계의 초기 단계 공정으로 활성영역의 크기와 후공정 단계의 공정마진을 좌우한다.Forming the device isolation region is an early stage process of all manufacturing process stages and determines the size of the active region and the process margin of the post process stage.
이러한 소자분리영역의 형성방법 중에서 특히, 트렌치 소자분리방법은 반도체기판의 소정 부분을 식각하여 트렌치를 형성한 후, 상기 트렌치 내부에 절연물질을 채움으로써 소자를 분리하는 방법을 말하는데, 이와 같은 트렌치 소자분리방법을 이용한 반도체 소자분리막의 형성방법이 도 1 내지 도 3에 도시되어 있다.Among the method of forming the device isolation region, in particular, the trench isolation method refers to a method of separating a device by etching a predetermined portion of a semiconductor substrate to form a trench, and then filling an insulating material in the trench. A method of forming a semiconductor device isolation film using a separation method is illustrated in FIGS. 1 to 3.
우선, 도 1에 도시된 바와 같이 반도체기판(10) 상부에 질화막(20)을 형성하고, 그 상부에 트렌치부 형성용 감광막패턴(30)을 형성한다.First, as shown in FIG. 1, the nitride film 20 is formed on the semiconductor substrate 10, and the photoresist pattern 30 for forming the trench is formed on the semiconductor substrate 10.
이후, 도 2에 도시된 바와 같이 상기 감광막패턴(30)을 식각마스크로 하여 상기 질화막(20)을 식각해내어 상기 반도체기판(10)의 소정 부분을 노출시킨 후, 노출된 부분의 반도체기판(10)을 소정 깊이까지 식각하여 트렌치부(T)를 형성한다.Thereafter, as illustrated in FIG. 2, the nitride film 20 is etched using the photoresist pattern 30 as an etch mask to expose a predetermined portion of the semiconductor substrate 10, and then the exposed semiconductor substrate ( 10) is etched to a predetermined depth to form the trench portion T.
이후 상기 감광막패턴(30)을 제거하고, 상기 결과물 상부에 산화막(40)을 증착하여 트렌치부(T)를 채우고, 도 3에 도시된 바와 같이 상기 질화막(20)이 노출될 때까지 화학적 기계적 연마공정을 이용한 평탄화공정을 실시한다.Thereafter, the photoresist layer pattern 30 is removed, the oxide layer 40 is deposited on the resultant to fill the trench T, and chemical mechanical polishing is performed until the nitride layer 20 is exposed as shown in FIG. 3. The planarization process using a process is performed.
하지만, 상기와 같은 방법으로 반도체의 소자분리막을 형성할 때 질화막(20)과 산화막(40) 간의 식각선택비의 차이로 인해 산화막(40)이 더 빨리 연마되어 도 3에 도시된 바와 같이 트렌치부(T)를 채운 산화막(40)의 표면이 다른 부분보다 낮아지는 디싱(Dishing;D)현상이 발생함으로써, 반도체 소자분리막이 그 기능을 안정적으로 수행할 수 없게 되는 문제점이 있었다.However, when forming the device isolation film of the semiconductor in the same manner as above, the oxide film 40 is polished faster due to the difference in the etching selectivity between the nitride film 20 and the oxide film 40, so that the trench portion is shown in FIG. 3. Since the surface of the oxide film 40 filled with (T) is dished (D), which is lower than other portions, the semiconductor device isolation film may not perform its function stably.
상기와 같은 문제점을 해결하기 위한 본 발명의 목적은 반도체기판 내에 트렌치부를 형성하고, 상기 트렌치부를 산화막으로 채운 후, 그 상부에 디싱방지막을 형성함으로써, 이에 화학적 기계적 연마공정을 이용한 평탄화 공정을 시행할 때, 디싱현상이 방지되어 반도체소자의 특성 및 신뢰도를 향상시킬 수 있도록 한 반도체 소자분리막의 형성방법을 제공하는데 있다.An object of the present invention for solving the above problems is to form a trench in a semiconductor substrate, fill the trench with an oxide film, and then form a dishing prevention film thereon, thereby performing a planarization process using a chemical mechanical polishing process. The present invention provides a method of forming a semiconductor device isolation film that prevents dishing to improve characteristics and reliability of a semiconductor device.
도 1 내지 도 3은 종래의 반도체 소자분리막의 형성방법을 설명하기 위해 도시된 도면들이다.1 to 3 are diagrams for explaining a conventional method of forming a semiconductor device isolation film.
도 4 내지 도 9는 본 발명에 따른 반도체 소자분리막의 형성방법을 설명하기 위해 도시된 도면들이다.4 to 9 are diagrams for explaining a method of forming a semiconductor device isolation film according to the present invention.
＊도면의 주요부분에 대한 부호의 설명＊＊ Description of symbols for main parts of the drawings ＊
100 ; 반도체기판 110 ; 질화막100; Semiconductor substrate 110; Nitride film
120, 140 ; 산화막 130 ; 디싱방지막120, 140; Oxide film 130; Dishing prevention film
T ; 트렌치부 D ; 디싱T; Trench portion D; Dishing
상기와 같은 목적을 달성하기 위한 본 발명은 반도체기판 상부에 질화막을 형성하는 단계와; 상기 질화막 상부에 트렌치부 형성용 감광막패턴을 형성하고, 상기 감광막 패턴을 식각마스크로 하여 상기 질화막을 식각해내어 상기 반도체기판의 소정 영역을 노출시키는 단계와; 상기에서 노출된 부분의 반도체기판을 소정 깊이까지 식각해내어 트렌치부를 형성하고, 상기 감광막 패턴을 제거하는 단계와; 상기 결과물 상부에 제 1 산화막 및 디싱방지막을 차례로 형성한 후, 상기 트렌치부의 상부에 형성되어 있는 디싱방지막이 소정 두께 남아있도록 상기 디싱방지막 및 제1 산화막을 차례로 식각해내는 단계와; 상기 결과물 상부에 제 2 산화막을 형성한 후, 상기 트렌치부의 상부에 형성되어 있는 디싱방지막까지 제거되도록 화학적 기계적 연마공정을 이용하여 평탄화공정을 시행하는 단계와; 이후, 상기 반도체기판 상부에 형성되어 있는 질화막을 식각해내는 단계; 를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object comprises the steps of forming a nitride film on the semiconductor substrate; Forming a photoresist pattern for forming trench portions on the nitride film, and etching the nitride film using the photoresist pattern as an etching mask to expose a predetermined region of the semiconductor substrate; Etching the exposed semiconductor substrate to a predetermined depth to form a trench, and removing the photoresist pattern; Sequentially forming a first oxide film and a dishing film on the resultant, and subsequently etching the dishing film and the first oxide film so that the dishing film formed on the trench portion remains a predetermined thickness; Forming a second oxide film on the resultant, and then performing a planarization process by using a chemical mechanical polishing process to remove even the dishing prevention film formed on the trench portion; Thereafter, etching the nitride film formed on the semiconductor substrate; Characterized in that comprises a.
이때, 상기 제 1 산화막 및 제 2 산화막은 HDP 산화막을 CVD방식을 이용하여 형성하고, 상기 디싱방지막은 질화막인 것을 특징으로 한다.In this case, the first oxide film and the second oxide film is formed by the HDP oxide film using a CVD method, the dishing film is characterized in that the nitride film.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다. 또한, 본 실시예는 본 발명의 권리범위를 한정하는 것이 아니며 단지 예시로 제시된 것이다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is merely presented as an example.
도 4 내지 도 9는 본 발명에 따른 반도체 소자분리막의 형성방법을 설명하기 위해 도시된 도면들이다.4 to 9 are diagrams for explaining a method of forming a semiconductor device isolation film according to the present invention.
우선 도 4에 도시된 바와 같이, 반도체기판(100) 상부에 질화막(110)을 형성한 후, 그 상부에 트렌치부 형성용 감광막패턴(미도시)을 형성한다.First, as shown in FIG. 4, the nitride film 110 is formed on the semiconductor substrate 100, and then a photoresist pattern (not shown) for forming a trench is formed thereon.
이후, 상기 감광막패턴을 식각마스크로 하여 상기 질화막(110)을 식각해내어 반도체기판(100)의 소정부분을 노출시킨 후, 상기에서 노출된 반도체기판(100)을 소정 깊이까지 식각하여 트렌치부(T)를 형성한다.Thereafter, the nitride layer 110 is etched using the photoresist pattern as an etch mask to expose a predetermined portion of the semiconductor substrate 100, and then the exposed semiconductor substrate 100 is etched to a predetermined depth to form a trench portion ( Form T).
그리고 상기 결과물 상부에 제 1 산화막(120) 및 디싱방지막(130)을 차례로 형성한다.The first oxide layer 120 and the dishing prevention layer 130 are sequentially formed on the resultant.
이후, 도 5에 도시된 바와 같이, 상기 제 1 산화막(120)이 노출될 때까지 상기 디싱방지막(130)과 제 1 산화막(120)을 차례로 식각해낸다.Thereafter, as shown in FIG. 5, the dishing prevention layer 130 and the first oxide layer 120 are sequentially etched until the first oxide layer 120 is exposed.
그러면 도 5에 도시된 바와 같은 식각라인이 형성되는데, 그 이유는 표면각도에 따라 식각정도가 달라지기 때문이다.Then, an etching line as shown in FIG. 5 is formed because the degree of etching varies depending on the surface angle.
즉, 도 9에 도시된 바와 같이 경사면은 평면에 비해 식각정도가 커지는데, 도 4에서 보면 디싱방지막(130) 및 제 1 산화막(120)의 일부분이 경사면을 가지도록 증착되어 있어 상대적으로 식각정도가 큰 경사면으로 증착된 디싱방지막(Ⅰ)은 전부 제거되고, 평면으로 증착된 디싱방지막(Ⅱ)은 남게 되면서 도 5에 도시된 바와 같은 식각라인이 형성되는 것이다.That is, as shown in FIG. 9, the inclined surface has a larger degree of etching than a plane. In FIG. 4, a portion of the dishing preventing film 130 and the first oxide film 120 is deposited to have an inclined surface. The dishing prevention film (I) deposited on the larger inclined surface is completely removed, and the dishing prevention film (II) deposited in the plane remains, and the etching line as shown in FIG. 5 is formed.
이후, 도 6에 도시된 바와 같이 상기 결과물 상부에 제 2 산화막(140)을 형성한 후, 상기 트렌치부의 상부에 형성된 디싱방지막(130')이 제거되도록 화학적 기계적 연마를 시행하면 도 7에 도시된 바와 같은 디싱현상이 방지된 결과물이 생기게 되는데, 이는 상기에서 식각되지 않고 남아있던 상기 디싱방지막(130')으로 인해 디싱현상이 방지되기 때문이다.Thereafter, as shown in FIG. 6, after the second oxide layer 140 is formed on the resultant, chemical mechanical polishing is performed to remove the dishing prevention layer 130 ′ formed on the trench portion. As a result, the dishing is prevented, which is because the dishing is prevented due to the dishing film 130 ′ which remains unetched.
이후, 도 8에 도시된 바와 같이 상기 질화막(110)을 제거한다.Thereafter, as shown in FIG. 8, the nitride film 110 is removed.
상기한 바와 같은 본 발명에 따른 반도체 소자분리막의 형성방법은 디싱방지막을 형성하여 디싱현상이 방지될 수 있도록 함으로써, 반도체소자의 특성 및 신뢰도를 향상시킬 수 있는 이점이 있다.The method of forming the semiconductor device isolation film according to the present invention as described above has the advantage of improving the characteristics and reliability of the semiconductor device by forming a dishing prevention film to prevent dishing phenomenon.
상기와 같은 반도체 소자분리막의 형성방법은 화학적 기계적 연마공정을 이용한 평탄화공정 시에도 응용될 수 있다.The method of forming the semiconductor device isolation layer as described above may be applied to a planarization process using a chemical mechanical polishing process.
상기한 바와 같은 본 발명은 반도체 소자분리막에 관한 것으로써, 특히 반도체기판 내에 트렌치부를 형성하고, 상기 트렌치부를 산화막으로 채운 후, 그 상부에 디싱방지막을 형성함으로써, 이에 화학적 기계적 연마공정을 이용한 평탄화공정을 시행할 때, 디싱현상이 방지되어 반도체소자의 특성 및 신뢰도를 향상시킬 수 있는 이점이 있다.As described above, the present invention relates to a semiconductor device isolation film, in particular, by forming a trench in a semiconductor substrate, filling the trench with an oxide film, and then forming a dishing prevention film thereon, thereby forming a planarization process using a chemical mechanical polishing process. When implementing the method, the dishing phenomenon is prevented and there is an advantage that can improve the characteristics and reliability of the semiconductor device.
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| KR1020000036649A KR20020002164A (en) | 2000-06-29 | 2000-06-29 | Method of forming isolation layer of semiconductor device |
Country Status (1)
| Country | Link |
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| KR (1) | KR20020002164A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6991993B2 (en) | 2003-01-24 | 2006-01-31 | Samsung Electronics Co., Ltd. | Method of fabricating trench isolation structure of a semiconductor device |
| KR100815962B1 (en) * | 2006-10-11 | 2008-03-21 | 동부일렉트로닉스 주식회사 | Manufacturing method of semiconductor device |
| CN114683162A (en) * | 2020-12-29 | 2022-07-01 | 中芯集成电路（宁波）有限公司 | Planarization process method |
-
2000
- 2000-06-29 KR KR1020000036649A patent/KR20020002164A/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6991993B2 (en) | 2003-01-24 | 2006-01-31 | Samsung Electronics Co., Ltd. | Method of fabricating trench isolation structure of a semiconductor device |
| KR100815962B1 (en) * | 2006-10-11 | 2008-03-21 | 동부일렉트로닉스 주식회사 | Manufacturing method of semiconductor device |
| CN114683162A (en) * | 2020-12-29 | 2022-07-01 | 中芯集成电路（宁波）有限公司 | Planarization process method |
| CN114683162B (en) * | 2020-12-29 | 2023-09-12 | 中芯集成电路（宁波）有限公司 | Planarization process method |
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