KR20010096789A - Sigma-delta modulator with efficient clock speeds - Google Patents

Abstract

The present invention relates to a sigma delta modulator, and in particular, to form a sequence of three switched capacitor integrators, 1 MHz in the first integrator, 4 MHz in the second and third integrators as a synchronization signal, but implements the integrator The operational amplifier has a fully differential two-stage structure, and the differential structure improves the DC gain of the op amp by 6 dB, reduces the offset voltage, and at the same time, A fully differential amplifier set to; A common mode feedback circuit for sensing an intermediate value of the output signal swing of the fully differential amplifier and outputting a constant DC voltage to stabilize the entire operational amplifier; A latch comparator for generating a synchronization signal of each of the switched capacitor integrators; And a non-overlapping clock generator for reducing the glitches of the clock generated by the latch comparator and sampling the signal in a stable state to improve the resolution by using a master clock and a clock divided by four for the clock of the switched capacitor integrator. A new structure of a 3.3V CMOS sigma delta modulator for a Sigma-Delta A / D converter with high resolution (> 16 bit), operating in the voice signal band (0 to 20 kHz).

Description

Sigma-Delta Modulator with Efficient Clock Speed {SIGMA-DELTA MODULATOR WITH EFFICIENT CLOCK SPEEDS}

The present invention relates to a 3.3V CMOS sigma delta modulator for a Sigma-Delta A / D converter having a high resolution (> 16 bit) and operating in the voice signal band (0-20 kHz). The structure designed in the present invention consists of three switched capacitor integrators, comparators, and non-overlapping clock generators to improve the signal-to-noise ratio. A sigma delta modulator for performing appropriate clock usage accordingly.

In general, the recently proposed oversampling method is one of the ADC / DAC circuit implementation methods that are recently attracting attention.

The oversampling method is basically higher in resolution than a general data converter, but may be used in applications of low resolution and high resolution since conversion rate is low. Referring to Examples 1 to 3 below, It may be used in the field of speech signal processing as mentioned in, and referred to in digital audio as mentioned in references 4 to 6, or in digital radio as mentioned in reference 7, and in references 8 to 11 As can be seen, applications for IF (Intermediate Frequency) signal processing are also possible.

A lowpass Sigma-Delta modulator structure is adopted for voice signal processing, and the structure for IF signal processing is a bandpass type.

[Reference 1]

Jorge Grilo, Edward MacRobbie, Raouf Halim and Gabor Temes, A 1.8V 94dB Dynamic Range Modulator for Voice Applications, ISSCC96, pp. 230-231, Feb., 1996.

[Reference 2]

Eric J. van der Zwan and E. Carel Dijkmans, A 0.2mW CMOS Modulator for Speech Coding with 80dB Dynamic Range, ISSCC96, pp.232-233, Feb., 1996.

[Reference 3]

Jiri Nedved, Jozef Vanneuville, Dorine Gevaert and Jan Stvenhans, A Transistor-Only Switched Current Sigma-Delta A / D Converter for a CMOS Speech CODEC, IEEE J, Solid-State Circuits, vol 30, pp 819-822, July 1995.

Ref. 4

Shahriar Rabii and Bruce A. Wooley, A 1.8V Digital-Audio Sigma-Delta Modulator in 0.8um CMOS, IEEE J, Solid-State Circuits, vol 32, pp 783-795, June 1997.

Ref. 5

Ka Y. Leung, Eric J. Swanson, kafai Leung and Sarah S. Zhu, A 5V 118dB Analog-to Digital Converter for Wideband Digital Audio, ISSCC97, pp. 218-219, Feb., 1997.

Ref. 6

Tapani Ritoniemi, Eero Pajarre and Ville Eerola, A Stereo Audio Sigma-Delta A / D-Converter, IEEE J, Solid-State Circuits, vol 29, pp 1514-1521, Dec. 1994.

Ref. 7

Stephen Jantzi, Kenntth Martin and Adel Sedra, A Quadrature Bandpass Modulator for Digital Radio, ISSCC97, pp. 216-217, Feb., 1997.

[Reference 8]

Adrian K. Ang and Bruce A. Wooley, A Two-Path Bandpass Modulator for Digital IF Extraction at 20 MHz, IEEE J, Solid-State Circuits, vol 32, pp 1920-1934, Dec. 1997.

Ref. 9

feng Chen and Bosco Leung, A 0.25mW Low-Pass Passive Sigma-Delta Modulator with Built-In Mixer for a 10-MHz IF Input, IEEE J, Solid-State Circuits, vol 32, pp 774-782, June 1997.

Ref. 10

Gopal Raghvan, Joseph F. Jensen, Robert H. Walden and William P. Posey, A Bandpass Modulator with 92 dB SNR and Center Frequency Continuously Programmable from 0 to 70 MHz, ISSCC97, pp. 214-215, Feb., 1997.

Ref. 11

Bang-Sup Song, A Fourth-Order Bandpass Delta-Sigma Modulator with Reduced Number of Op Amps, IEEE J, Solid-State Circuits, vol 30, pp 1309-1314, Dec. 1995.

The techniques presented in the above-mentioned references, as mentioned previously, do not overcome the limitation that the oversampling method is basically higher resolution than the general data converter, but the conversion rate falls. With the limitations in place, the focus is on how to apply them to commercial technology. Moreover, the demand for data converters is increasing greatly in the field of information and communication in recent years. Especially in the age of multimedia, there is an urgent need for highly integrated voice signal processing circuits.

Therefore, the structure of the sigma delta modulator used as the hardware implementation of the oversampling method described above has a limitation in utilizing the advantage of high resolution because the signal-to-noise ratio and the conversion speed are lowered due to the low conversion rate. A method for solving the problem has not been proposed yet.

Accordingly, an object of the present invention is to provide a sigma delta modulator capable of improving the signal-to-noise ratio and the conversion speed while adopting a basic sigma delta modulator structure.

Another object of the present invention is to provide a sigma delta modulator that optimizes the clock used in a switched capacitor integrator and does not require additional circuitry and thus does not affect power consumption or chip area.

1 is a circuit diagram illustrating the overall operation principle of a sigma delta modulator with improved resolution by using a master clock and a clock divided by four in a clock of a switched capacitor integrator according to an exemplary embodiment of the present invention.

2 is a circuit diagram of a fully differential amplifier used in a modulator in accordance with an embodiment of the present invention.

3 is a circuit diagram of an in-phase mode feedback circuit.

4 is a circuit diagram of a latch comparator having a clock to synchronize with.

5 is a circuit diagram of a non-overlapping clock generator.

In order to achieve the above object of the present invention, a feature of the present invention is to sequentially form three switched capacitor integrators in a sigma delta modulator, 1 MHz for the first integrator, and 4 MHz for the second and third integrators. It is used as a synchronization signal, but the op amp implements the integrator has a fully differential two-stage structure, the differential structure can improve the DC gain of the op amp by 6 dB, reduce the offset voltage and at the same time the amplification degree A fully differential amplifier set to; A common mode feedback circuit for sensing an intermediate value of the output signal swing of the fully differential amplifier and outputting a constant DC voltage to stabilize the entire operational amplifier; A latch comparator for generating a synchronization signal of each of the switched capacitor integrators; And a non-overlapping clock generator for reducing the glitches of the clock generated by the latch comparator and sampling the signal in a stable state to improve the resolution by using a master clock and a clock divided by four for the clock of the switched capacitor integrator.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing the overall operation principle of a sigma delta modulator with improved resolution by using a clock divided by a master clock and a clock divided by a clock of a switched capacitor integrator according to an embodiment of the present invention, and FIG. FIG. 3 is a circuit diagram of an in-phase mode feedback circuit, FIG. 4 is a circuit diagram of a latch comparator having a clock to synchronize, and FIG. 5 is a circuit diagram of a non-overlapping clock generator.

The circuit of the present invention shown in FIG. 1 is operated in the voice signal band (0 to 20 kHz) and is 3.3V for a Sigma-Delta A / D converter with high resolution (> 16 bit). CMOS Sigma Delta Modulator is a new structure. That is, the design structure shown in FIG. 1 consists of three switched capacitor integrators, a comparator, and a non-overlapping clock generator. The clock speed needs to be determined, and the clock used for the switches of the integrators (1 to 3) is optimized for the capacity of the integrating capacitor of the integrator.

The signal processing speed is improved by using 1 MHz for the first integrator (1) and 4 MHz for the second and third integrators (2, 3). In addition, it is necessary to derive the pole value in order to offset the unnecessary zero characteristic. The operational amplifiers used in the first to third integrators 1 to 3 exhibit a DC gain of 40 dB or more, a good frequency characteristic, and power consumption within 5 mW at a 3.3 V supply, to improve the symmetry and amplification of the circuit. Design in a fully differential structure. Also, in order to stabilize the output of the fully differential amplifier shown in FIG. 2, a common mode feedback circuit is inevitably required, and the variation of the Vcmfb voltage requires less than 20 mV.

The voltage comparator needs a circuit that can compare the 1mV difference, and the non-overlapping time of the non-overlapping circuit must maintain 2nS. The proposed circuit has a single 3.3V supply and the total power consumption is less than 20mW.

Referring to the fully differential operational amplifier for the switched capacitor integrator shown in Figure 2 below, the operational amplifier used in the switched capacitor integrator has a fully differential two-stage structure. The differential scheme improves the op amp's DC gain by 6 dB and reduces the offset voltage, making it suitable for sigma delta modulators that require high resolution. The amplification degree of the operational amplifier can be defined as Equation 1 below.

The requirements and simulation results of the operational amplifier used in the switched capacitor integrator are shown in Table 1 below.

Operational amplifier Specification 1st stage operational amplifier DC gain (> 40 dB) Slew rate (> 3.3 V / us) Phase margin cutoff Frequency offset Voltage supply voltage (3.3 V) Power consumption 2nd and 3rd stage operational amplifier DC gain (> 40 dB) Slew rate (> 13.2 V / us) Phase margin cutoff Frequency offset Voltage supply voltage (3.3 V) Power consumption

In response to the requirements and simulation results of the operational amplifier used in the switched capacitor integrator shown in Table 1, Equation 1 may be redefined as Equation 2 and Equation 3 below.

At this time, the clocks used in the switched capacitor integrator are 1 MHz and 4 MHz. Therefore, the slew rate required for driving is obtained as in Equations 4 and 5 below.

In addition, the compensation capacitor value at this time is obtained from Equation 6 below from the slew rates represented by Equations 4 and 5.

A common mode feed back circuit (hereinafter referred to as a CMFB circuit) shown in FIG. 3 is an additional circuit required for a fully differential operational amplifier. That is, the CMFB circuit is an intermediate part of an operational amplifier output signal swing. It senses the value and outputs a constant DC voltage to stabilize the entire op amp.

At this time, the implementation method of the CMFB circuit is various. The proposed circuit according to the present invention has a structure as shown in FIG. 3 to reduce the number of transistors and power consumption.

Suppose Vout + and Vout- swing with Vcm + vout +/- . Since the sum of the currents flowing through the differential pairs is 11uA each, the Vcmfb voltage value does not change. That is, it is not necessary to supply current. However, if Vout + and Vout- swing at Vcm + ΔV + vout +/- , the Vcmfb voltage is changed to supply the current Δi generated by ΔV. Since the Vcmfb voltage changes the current source of the op amp, the operating point of the output node of the amplifier is changed by -ΔV to stabilize the output signal.

In order to design the CMFB circuit, it is necessary to first determine the Vcmfb voltage. Usually, it is used as the gate voltage of the tail current of the differential stage or as the gate voltage of the active load of the output stage. The proposed circuit is designed with Vcmfb = 2V to use as gate voltage of active load of amplifier. The Vcm value is the operating point voltage of the op amp output stage. If the amplifier has an offset of 50mV, the Vcm value should also have an offset voltage of 50mV. In the proposed circuit, Vcm = Vcc / 2 = 1.65V was used because the simulation result of the operational amplifier has an offset voltage within several mV.

Sigma delta modulators are also insensitive to the performance of comparators. Therefore, comparators used in modulators are more important to reduce power consumption and chip area than comparable performance. The modulator used in the present invention has the advantage of not requiring a separate latch circuit as a latch comparator.

Therefore, the comparator according to the present invention is constructed as shown in FIG. 4, the power consumption is 0.1 mW, and the minimum comparison voltage is 1 mV or less. As the reference numbers mn4 and mn5 are connected to the drain of each other, the gate is more sensitive to the input voltage. When the clock is low, it is compared. When it is high, all current flows to the reference number mn3, and Vout +/- becomes zero. Therefore, no separate latch circuit is needed.

In the present invention, the clock means Φ 3 in the overall circuit diagram.

Finally, the non-overlapping circuit used in the present invention is constructed as shown in the accompanying FIG. 5, and the non-overlapping circuit, which is one of the important parts of the switched capacitor circuit, reduces the glitches of the clock and samples the signal in a stable state. To do that.

The non-overlapping time of the general non-overlapping clock generator is 2 ~ 5 nsec. to be.

The experimental results show that the nonoverlapping time is about 2ns and the delay time is about 3ns.

The present invention is not limited to the above embodiments and can be variously modified and implemented by those skilled in the art without departing from the technical gist of the present invention.

Providing the sigma delta modulator according to the present invention configured and operated as described above, the clock speed of the switched capacitor integrator can be improved by modeling the circuit and determining the appropriate capacitor capacity, and the band of interest from the derivation of the pole using modeling. It was possible to offset the effect of the zero point existing outside. In addition, as the effective bits of the internal ADCs and DACs increase, the signal-to-noise ratio increases.

Through the above circuit and design of the decimation filter, a complete ADC can be realized. The implementation of the digital filter may be implemented as a programmable logic device (PLD) using VHDL or an on-chip as an ASIC chip as a cell library using a Synopsys tool.

The sigma delta A / D converter using the proposed modulator structure can be effectively used for digital audio, digital radio and IF signal processing.

Claims (1)

In the sigma delta modulator, Three switched capacitor integrators are sequentially formed, and 1 MHz is used for the first integrator and 4 MHz is used for the second and third integrators as a synchronization signal. The differential scheme improves the op amp's DC gain by 6 dB, reduces the offset voltage, and increases its amplification. A fully differential amplifier set to; A common mode feedback circuit for sensing an intermediate value of the output signal swing of the fully differential amplifier and outputting a constant DC voltage to stabilize the entire operational amplifier; A latch comparator for generating a synchronization signal of each of the switched capacitor integrators; And A non-overlapping clock generator for reducing the glitches of the clock generated by the latch comparator and sampling the signal in a stable state improves the resolution by using a master clock and a clock divided by four for the clock of the switched capacitor integrator. Sigma Delta Modulator.