KR20010081704A - Equalization circuit for sense amplifier - Google Patents

Abstract

PURPOSE: An equalizing circuit is provided to reduce the power consumption and the layout area by using the power of a sense amplifier not using an external power in order to equalize bit lines. CONSTITUTION: The equalizing circuit includes a bit line connection control unit(11A) for breaking connection of bit lines(BLBL,BLTL) with a cell array. An equalizing circuit(12A) is connected between the bit line connection control unit(11A) and a sense amplifier(13). The equalizing circuit(12A) equalizes the bit lines(BLBL,BLTL) using the voltage of the sense amplifier(13) without using an additional external power. The sense amplifier(13) amplifies a minute signal from the bit lines(BLBL,BLTL) to output the amplified signal as a given level. An input/output line connection control unit(14) transmits the output signal of the sense amplifier(13) to the outside or receives a signal from the outside.

Description

Equalization circuit of sense amplifiers {EQUALIZATION CIRCUIT FOR SENSE AMPLIFIER}

The present invention relates to a design technology of an equalization circuit applied to a sense amplifier for amplifying and outputting a weak signal outputted from a memory cell array to a predetermined level, and in particular, a sense for reducing power consumption and layout area of an equalization circuit. The equalizing circuit of the amplifier.

1 is an isometric circuit diagram of a sense amplifier according to the prior art, and as shown therein, a bit line connection control section 1A for intermittently connecting bit line BLBL and BLTL connections with a cell array side; An equalization circuit section 2A connected between the bit line connection control section 1A and a sense amplifier 3 to be described later to precharge the bit lines BLBL and BLTL to a predetermined level of voltage; A sense amplifier (3) for amplifying and outputting a weak signal input through the bit lines (BLBL) and (BLTL) to a predetermined level; An input / output line connection controller (4) for transmitting an output signal of the sense amplifier (3) to the outside or receiving a signal from the outside; The bit lines BLBL and BLTL are shared with the bit line connection control unit 1A and the equalization circuit unit 2A, but control signals of logic opposite to the bit line connection control unit 1A and the equalization circuit unit 2A It consists of a bit line connection control unit 1B and an equalization circuit unit 2B driven by SHR) and BLEQB. The operation thereof is as follows.

When the switching control signal SHL is supplied to " high ", the NMOS transistors NM1 and NM2 of the bit line connection controller 1A are turned on, respectively, and the cells are turned on through the bit lines BLBL and BLTL. An array (not shown) and a sense amplifier are connected.

The weak signal read from the cell array is transferred to the sense amplifier 3 through the NMOS transistors NM1, NM2, and bit lines BLBL, BLTL of the bit line connection controller 1A. And amplified to a predetermined level. For example, if the read data is "high", it is pulled up to the level of the voltage CSP, and if the read data is "low", it is pulled down to the level of the voltage CSN.

At this time, when the selection signal YS of the input / output line connection control unit 4 is supplied to " high ", the NMOS transistors NM8 and NM9 are turned on by this. Accordingly, the data sensed through the sense amplifier 3 is output to the outside.

When the read data sensing operation of the cell array is terminated through such a series of processes, the equalization control signal BLEQB is supplied to the equalization circuit unit 2A as "high" so that the NMOS transistors NM3-NM5 are turned on. The lines BLBL and BLTL are precharged with the precharge voltage VBLR.

On the other hand, since the cell array different from the above is connected to the sense amplifier 3 through the bit lines BLBL, BLTL, the bit line connection control unit 1B and the equalization circuit unit 2B, the sense amplifier 3 In the corresponding mode, the data inputted through them is sensed and output as described above.

However, the precharge voltage VBLR supplied to the equalization circuits 2A and 2B is a voltage supplied from a separate power supply installed outside.

As described above, in the equalizing circuit of the sense amplifier according to the prior art, the equalizing circuit unit receives the precharge voltage VBLR from an external power supply to equalize the bit line, thereby increasing power consumption and layout by increasing wiring. There was a defect that the area was widened.

Accordingly, an object of the present invention is to provide an equalization circuit of a sense amplifier that uses the power of the sense amplifier without using an external power source to equalize the bit line.

1 is an equalization circuit diagram of a sense amplifier according to the prior art.

2 is an equalization circuit diagram of a sense amplifier according to the present invention.

Figure 3 is a graph comparing the power consumption according to the present invention.

*** Description of the symbols for the main parts of the drawings ***

11A and 11B: bit line connection controller 12A and 12B: equalization circuit

13: sense amplifier 14: input / output line connection controller

2 is a diagram illustrating an embodiment of an equalization circuit of a sense amplifier for achieving the object of the present invention. As shown therein, a bit line connection control unit for intermitting bit line (BLBL) and (BLTL) connection with a cell array side is shown. 11A; The equalization between the bit line connection control unit 11A and the sense amplifier 13 to be described later, in equalizing the bit lines BLBL and BLTL, does not require a separate external power source. An equalization circuit section 12A for equalizing using a voltage of; A sense amplifier 13 for amplifying and outputting a weak signal input through the bit lines BLBL and BLTL to a predetermined level; An input / output line connection controller 14 for transmitting an output signal of the sense amplifier 13 to the outside or receiving a signal from the outside; The bit lines BLBL and BLTL are shared with the bit line connection control unit 11A and the equalization circuit unit 12A, but control signals of logic opposite to the bit line connection control unit 11A and the equalization circuit unit 12A A bit line connection control unit 11B and an equalization circuit unit 12B driven by SHR) and (BLEQB) will be described in detail.

When the switching control signal SHL is supplied to " high ", the nMOS transistors NM1 and NM2 of the bit line connection control unit 11A are turned on, respectively, and the cells are turned on through the bit lines BLBL and BLTL. An array (not shown) and a sense amplifier are connected.

The weak signal read from the cell array is transferred to the sense amplifier 13 through the NMOS transistors NM1, NM2, and bit lines BLBL and BLTL of the bit line connection controller 11A. Amplify to level. For example, if the read data is "high", it is pulled up to the level of the voltage CSP, and if the read data is "low", it is pulled down to the level of the voltage CSN.

At this time, when the selection signal YS of the input / output line connection control unit 14 is supplied "high", the n-MOS transistors NM8 and NM9 are turned on by this. Accordingly, the data sensed through the sense amplifier 13 is output to the outside.

On the other hand, since the cell array different from the above is connected to the sense amplifier 13 through the bit lines BLBL, BLTL, the bit line connection control unit 11B, and the equalization circuit unit 12B, the sense amplifier 13 In the corresponding mode, the data inputted through them is sensed and output as described above.

When the read data sensing operation of the cell array is terminated through such a series of processes, the equalization control signal BLEQB is supplied to the equalization circuit unit 12A as "high", so that the MOS transistors NM3-NM5 are turned on. The bit lines BLBL and BLTL are precharged. Unlike the conventional method, the voltage CSN of the sense amplifier 13 is used.

That is, when the sense amplifier 13 performs the equalizing function after the voltage CSN and CSP are used to pull up or pull down the read data when the sensing amplifier 13 performs the sensing operation, the sense amplifier 13 performs the equalizing function. Since 13 is at rest, the voltages CSN and CSP are not used.

In view of this, the equalization circuits 12A and 12B precharge the bit lines BLBL and BLTL by using the voltages CSN and CSP in the idle state. It does not require, and the power consumption can be reduced.

Referring to the simulation result of FIG. 2, the peak current is 5.6 mA and rms is 537 μA when the precharge voltage VBLR is supplied from an external power supply and precharges the bit lines BLBL and BLTL. As shown in the present invention, when precharging the bit lines BLBL and BLTL using the voltages CSN and CSP of the sense amplifier 13, the peak current is 2mA and the rms is improved to 156μA. have.

As described in detail above, the present invention has the effect of reducing power consumption and layout area by using a sense amplifier power source instead of using an external power source to equalize a bit line.

Claims (1)

A bit line connection controller for controlling a bit line connection with the cell array side; A sense amplifier configured to pull up or pull down a weak signal input through the bit line; And an equalizing circuit unit configured to equalize using the pull-up and pull-down voltages of the sense amplifier when the bit line is equalized, without using an external power supply.