KR20010030241A - Active matrix type liquid crystal display element and method for manufacturing the same - Google Patents

Abstract

PURPOSE: To improve the uniformity of a display screen and to obtain a high picture quality liquid crystal panel by having a parasitic capacitance region section where a pixel output wiring section and a scanning line input section overlap and making the parasitic capacitance have intrasurface distribution. CONSTITUTION: Scanning lines 101 and signal lines 102 are approximately orthogonally cross each other and a TFT element 103 has a parasitic capacitance 106 region section where pixel output wiring section and scanning line input section overlap each other. And, flicker suppressing means are provided in the distribution condition of the capacitors 106 along the scanning line direction to suppress flicker phenomenon of display screen caused by the fact that field through voltages of active matrix type liquid crystal display elements are different at the input and its opposite sides of scanning line signals of the lines 101. Since the values of the capacitors 106 are not uniform, the variation, in the intrasurface distribution of the field through voltages becomes small, flicker is suppressed and liquid crystal display elements having higher picture quality are obtained. The flicker suppressing means are provided by the specifications of an exposure mask during the production process of the liquid crystal display elements.

Description

ACTIVE MATRIX TYPE LIQUID CRYSTAL DISPLAY ELEMENT AND METHOD FOR MANUFACTURING THE SAME

TECHNICAL FIELD The present invention relates to an active matrix liquid crystal display element used in an OA device, an AV device, or the like, and a manufacturing method thereof. In particular, it relates to a liquid crystal display device of high picture quality and high definition in large areas.

Currently, display elements using liquid crystals include a view finder or color TV of a video camera or a high definition projection-type TV, a personal computer, a word processor, BACKGROUND ART Applications have been applied in various fields such as information display terminals such as liquid crystal monitors, and development and commercialization are more actively performed. In particular, an active matrix type twisted nematic (TN) liquid crystal display using a thin film transistor (hereinafter referred to as TFT) as a switching element has a great feature that high contrast is maintained even when displaying a large capacity. In particular, the current market is very demanding for large-capacity full-color displays for laptop personal computers, notebook computers or engineering workstations, and developed in response to them. Commercialization is actively underway.

In the active matrix type, in the liquid crystal driving method compared with the conventional direct matrix type, switching elements such as TFTs are provided on pixel electrodes arranged on the matrix, respectively. It is a method of independently supplying an electric signal for controlling the optical characteristic of the liquid crystal to each pixel electrode via a switching element. In principle, this driving method has a small cross talk, which can be seen in a simple matrix method, and is very suitable for large screen, high definition, and multi-tone reproduction of a liquid crystal display device.

However, even in such an active matrix type liquid crystal display device, since the display element is made to have a large screen and high definition, a decrease in picture quality is inevitable to some extent. In particular, the parasitic capacitance generated in the overlapping areas of the scanning line input unit and the pixel output wiring unit is the capacitance component of the scanning line according to the large screen of the display element and the gate / drain capacitance component of the TFT which is the switching element. There arises a problem that the uniformity of the display screen called the in-plane distribution of the flicker deteriorates due to the delay of the scan line signal due to parasitic capacitance. This problem is described below.

5 shows a general equivalent circuit of an active matrix liquid crystal display element. The plurality of scanning lines 101 and the plurality of signal lines 102 are arranged orthogonal to each other, and TFT 103 serving as a switching element is provided at their intersections. In the figure, three scanning lines 101 and three signal lines 102 are shown, but this number is much smaller than it actually is. The storage capacitor 105 is formed to improve the retention characteristic of the pixel voltage applied to the liquid crystal capacitor 104. In the TFT 103, parasitic capacitance 106 (Cgd) is present between the gate and the drain.

6 shows a cross-sectional structure diagram of a general TFT. The TFT includes a gate electrode 201 (scanning line), a source electrode 202 (signal line), and a drain electrode 203 (pixel output wiring portion). An insulating layer 207 is provided between the gate electrode 201 and the drain electrode 203 so that an overlap region 204 of the gate and drain electrodes exists. This overlapping region 204 causes parasitic capacitance 106 (Cgd) between the gate and the drain of the TFT.

Although not shown in FIG. 6, the liquid crystal is disposed on the side opposite to the gate electrode 201 of the source electrode 202 and the drain electrode 203, that is, above the drain electrode 203 or the like in FIG. 6. This is arranged, and a signal is applied to the liquid crystal via the FET having the above electrode. In addition, a counter electrode is disposed on the side of the liquid crystal facing the FET.

7 is a signal waveform diagram showing the operation of the active matrix liquid crystal display device shown in FIG. 1. A gate voltage 301 (scan line signal) supplied to the gate electrode of the TFT 103 via the scan line 101 shown in FIG. 5 and a signal voltage 302 applied to the source electrode 202 of the TFT 103. And the relative time relationship between the pixel voltage 303 and the waveform change. The pixel voltage is a voltage taken out of the pixel electrode. As shown in FIG. 7, when the gate voltage 301 of the TFT is turned on by the scan line signal of the selected scan line, the signal voltage 302 is supplied to the pixel electrode via the TFT. On the other hand, when the gate voltage changes from the ON (HIGH) state to the OFF (LOW) state, the pixel voltage 303 is changed by the parasitic capacitance 106 (Cgd). The change ΔVp of the pixel voltage 303 is called a feed through voltage. If the amplitude of the gate voltage 301 is Vg, the value of the liquid crystal capacitor 104 is Clc, and the value of the storage capacitor 105 is Cst, the feed-through voltage ΔVp can be expressed by Equation (1).

ΔVp = Vg · (Cgd / Ct)

Provided that Ct = Clc + Cst + Cgd

In addition, in order to compensate for the inappropriate feed-through voltage ΔVp occurring at the pixel electrode, a voltage adjusted to an appropriate value is generally applied to the counter electrode. However, even if the voltage applied to the counter electrode is properly adjusted, the capacitance component C and the resistance component R of the scan line 101 cannot be ignored due to the increase in the size of the liquid crystal panel and the number of pixels. The problem of signal delay due to this still remains.

8 shows the change in the pixel voltage when there is a delay in the gate voltage (voltage of the scan line 101). In this case, the signal voltage is supplied to the pixel electrode in the ON state of the gate voltage. When the gate voltage changes from the ON state to the OFF state, the same phenomenon as above occurs, but if a signal delay occurs, the gate voltage 301 changes and the pixel voltage is affected by the parasitic capacitance 106 (Cgd). At the same time, charging of the signal voltage to the pixel electrode occurs simultaneously because the TFT is not turned OFF in an instant. At this time, the size of the voltage applied to the counter electrode and the liquid crystal applied voltage difference in the plane of the liquid crystal display screen also depend, but flicker occurs in the liquid crystal display, causing deterioration in image quality of the liquid crystal display element.

In recent years, various methods have been developed and proposed in order to eliminate inadequate flicker caused by the enlargement and high definition of liquid crystal display devices. Basically, the problem is how to make the feed-through voltage ΔVp of Equation 1 small. In order to reduce the feed-through voltage ΔVp, a method of increasing the storage capacitance Cst is considered, as will be apparent from Equation (1). However, in this method, the driving capability of the TFT must also be high along with it, so that the device size must be increased. Therefore, this method is not effective because it relates to the increase in the parasitic capacitance 106 (Cgd) as a result. In addition, in order to reduce the feed-through voltage ΔVp, as shown in Equation 1, it is considered to reduce the parasitic capacitance 106 (Cgd) of the TFT, and many developments and proposals of concrete processes for actually reducing the parasitic capacitance have been published. have. However, even if the parasitic capacitance can be made to be virtually negligible by improvement and improvement of the manufacturing process of the liquid crystal display element and the TFT, it is practically difficult to exclude the capacitance component of the TFT channel portion. Therefore, when high definition of the display element progresses and a high speed is required for the operation of the TFT, the driving capability of the TFT must be increased, and further, the size of the TFT must be increased. This is not an effective countermeasure in relation to increasing the parasitic capacitance of the TFT.

As a conventional technique for avoiding an increase in feedthrough voltage in an active matrix system using a TFT as a switching element, one disclosed in Japanese Patent Application Laid-Open No. 9-258261 (hereinafter, referred to as Prior Art 1) is known. In the prior art 1, a liquid crystal panel including a TFT in which the size of the TFT is enlarged as the terminal of the gate bus line is expanded, and the source electrode is connected to the pixel electrode, and the size of each pixel electrode is defined as the gate bus line (see The shrinkage is disclosed as it becomes a terminal of the scanning line of the invention.

However, since the technical idea disclosed in Prior Art 1 is to change the size of the TFT, it is difficult to find a preferable liquid crystal driving condition throughout the active matrix liquid crystal display element.

Further, the width W of the channel of the switching element TFT on the input side and the terminal side of the gate line (scan line) to which the gate signal (scan line signal) is supplied to suppress the flicker occurring in the active matrix liquid crystal display element. The technical idea of controlling the ratio of and length L, W / L, is disclosed, for example, in Japanese Patent Application Laid-Open No. 5-232512 (hereinafter, referred to as Prior Art 2). The prior art 2 shows that the drain current of the switching element TFT becomes large at the terminal of the gate line, the on-resistance is reduced, the time constant of the switching element is reduced, and the delay time due to the line resistance of the gate line is reduced. By correcting, the charging characteristics are aligned.

Also in the prior art 2, the ratio of the channel width W and the length L of the switching element TFT connected to the gate line to be the same as the prior art 1, W / L is the terminal side (termination) than the input terminal side of the gate signal. In the same meaning as in the above), it is difficult to find preferable liquid crystal driving conditions, and thus lacks practicality.

Further, in an active matrix liquid crystal display device using TFTs, Japanese Patent Application Laid-open No. 5-232509 (hereinafter referred to as technical idea of suppressing flicker by varying auxiliary capacitance at the input side of the gate signal and the terminal side thereof) , Prior art 3).

Prior art 3 eliminates the problem that the luminance signal or partial flicker occurs due to the coupling of the gate signal supplied from the gate line to the input terminal side and the terminal side due to the charging characteristic or the parasitic capacitance C _GS . The storage capacitor is made larger at the input terminal side of the scanning line and smaller at the terminal (terminal) side.

Disclosed in the prior art 3 to eliminate the problem that the gate signal supplied from the gate line is the luminance gradient or partial flicker due to the coupling down by the charging characteristic or parasitic capacitance (C _GS ) at the input side and the terminal side thereof. That is, the auxiliary capacitance is made larger on the input side and smaller on the terminal side.

Furthermore, in the liquid crystal display device, in order to suppress the flicker, it is necessary to make the capacitance between the gate electrode and the source electrode small on the input side of the signal line and large on the terminal (termination) side of JP 11-84428 A. (Hereinafter, prior art 4).

The prior art 4 adjusts the gate-source capacitance by the above-described configuration to reduce the difference between the pixels of the potential drop component of the pixel electrode. Such a prior art 4 discloses a configuration similar to the technical idea of the present invention.

That is, Fig. 27 (a) of the prior art 4 shows the TFT of the pixel on the input terminal side and Fig. 27 (b) of the prior art 4 shows the TFT of the far side (terminal) from the input terminal, respectively, and the adjustment pattern on the source electrode SD1. Providing I2 is disclosed. Furthermore, it is disclosed that this adjustment pattern I2 is provided away from the portion defining the channel length L and the channel width W of the thin film transistor TFT.

However, prior art 4 does not disclose arranging the source electrode and the drain electrode substantially parallel to those shown in the present invention. In addition, it is not disclosed to arrange these two electrodes so as to be substantially orthogonal to the gate electrode. Moreover, in order to adjust the parasitic capacitance which arises in a gate electrode and a drain electrode, opposing a source electrode means adjusting the length of the side of the drain electrode of an opposite side, or adjusting a width of the drain electrode on a drain electrode on a gate electrode. It does not show providing a space part in the vicinity of.

The present invention provides an active matrix liquid crystal display device and a manufacturing method which can cope with an increase in size and high definition of a liquid crystal display device and improve the uniformity of a display screen such as luminance distribution and flicker distribution, which are a major problem in the design of a panel. It aims to do it.

1 is an equivalent circuit diagram of an active matrix liquid crystal display device in Example 1 and Example 2 of the present invention;

2 (a) and 2 (b) are plan views of the TFTs provided in Embodiment 1 of the present invention;

3 is a view showing a measurement result of an opposing voltage optimum value of an active matrix liquid crystal display device of the present invention;

4A and 4B are planar layout views of a TFT according to Embodiment 2 of the present invention;

5 is an equivalent circuit diagram of a general active matrix liquid crystal display device;

6 is a sectional view of a typical TFT

7 is a waveform diagram showing an operation of a general active matrix liquid crystal display device;

8 is a waveform diagram illustrating a change in pixel voltage when there is a signal delay in a general gate voltage.

Explanation of symbols for the main parts of the drawings

101: scanning line 102: signal line

103: TFT 104: liquid crystal capacitance

105: storage capacity 106: parasitic capacity

107: pixel electrode

201: gate electrode 202: source electrode

203: drain electrode

204: overlapping portion of the gate electrode and the drain electrode

205: pixel electrode 206: pixel output wiring portion

207: insulating film

In order to solve the above problems, a plurality of switching elements including a plurality of scan lines, a plurality of signal lines, a plurality of pixel electrodes, a scan line input unit, a signal line input unit, and a pixel output wiring unit are disposed on a substrate, and the signal line input unit and The pixel output wiring portions are arranged to face each other and substantially parallel to each other, and are arranged in a matrix form substantially perpendicular to the scan line, and the pixel electrode and the switching element are provided near the intersection of the scan line and the signal line. The scan line is connected to the scan line input part of the switching element, the signal line is connected to the signal line input part of the switching element, and the pixel matrix is connected to the pixel output wiring part of the switching element. The active matrix liquid crystal display Party is an active matrix type liquid crystal display device installed flicker suppression means for suppressing the flickering of the display screen in the vicinity of the pixel output line portion due to the feedthrough voltage is different from the scanning line of the input side and the terminal side.

According to this, since the width of the pixel output wiring is widened on the scanning line and on the side not facing the signal wiring portion, the parasitic capacitance of the flicker suppressing means is not affected without affecting the channel width and channel length of the TFT. Can be adjusted.

Moreover, one of this invention is an active-matrix type liquid crystal display element in which the flicker suppression means of Claim 1 is arrange | positioned at the side away from the signal line input part in a part of the said pixel output wiring part. According to this, the parasitic capacitance of a flicker suppressing means can be adjusted so that the magnitude | size of the channel width and channel length of TFT may not be disturbed.

In another aspect of the present invention, in the active matrix liquid crystal display device according to claim 1, the parasitic capacitance of the flicker suppression means is adjusted in the space prepared in the vicinity of the pixel output wiring portion on the scanning line in the wiring width of the pixel output wiring portion. It is an active matrix liquid crystal display element formed by adjusting the. According to this, since the space part for adjusting parasitic capacitance is arrange | positioned in the vicinity of the pixel output wiring part previously, setting of parasitic capacitance is easy.

In still another aspect of the present invention, in the claims 1 to 3, the scan line is connected to the gate electrode of the TFT, the signal line is connected to the source electrode, and the pixel output wiring part is connected to the drain electrode, respectively. Parasitic capacitance adjustment is an active matrix liquid crystal display element which is performed by adjusting the wiring width of the part which drains from the said source electrode in a part of drain electrode. According to this, although the wiring width of a drain electrode is adjusted, since it does not affect the source electrode side, it does not affect the magnitude | size of the channel width and channel length of TFT.

In still another aspect of the present invention, in the active matrix liquid crystal display device according to claim 1, the parasitic capacitance of the flicker suppression means is adjusted in addition to the space portion prepared near the pixel output wiring portion on the scanning line. It is an active matrix liquid crystal display element which adjusts wiring width. According to this, since the space part for adjusting wiring width is prepared previously, parasitic capacitance can be adjusted easily.

In still another aspect of the present invention, in the active matrix liquid crystal display device according to claim 1, the size of the parasitic capacitance from the input end side of the scanning line to the terminal side in the flicker suppressing means is small at the input end side. It is an active matrix liquid crystal display element largely selected on the terminal side. According to this, the feed-through voltage of flicker generation can be adjusted by having a desired magnitude | size or predetermined relationship at the input terminal side and the terminal side.

Furthermore, another invention of the present invention is the active matrix liquid crystal display device according to claim 5, wherein the capacitance adjustment in the flicker suppression means is divided for each block from the input end side of the scanning line to the terminal side thereof. to be. According to this, flicker can be suppressed to the level which is satisfactory practically without adjusting parasitic capacitance of TFT individually.

Moreover, this invention is a manufacturing method of the active-matrix type liquid crystal display element in which the flicker suppression means was provided by changing exposure conditions, when manufacturing the active matrix liquid crystal display element in any one of Claims 1-6. According to this, the flicker countermeasure can be taken in the manufacturing process of an actual liquid crystal display element, without increasing a process.

Moreover, another invention of this invention is a manufacturing method of the active-matrix type liquid crystal display element provided with the flicker suppression means in the specification of an exposure mask, when manufacturing the active-matrix liquid crystal display element in any one of Claims 1-6. According to this, since the wiring width of a pixel output wiring part is set by the exposure mask, the magnitude | size of a parasitic capacitance can be adjusted reliably.

EMBODIMENT OF THE INVENTION Hereinafter, each Example of this invention is described, referring drawings.

(Example 1)

1 shows a part of an equivalent circuit of an active matrix liquid crystal display device of Embodiment 1 of the present invention. The scanning lines 101 and the signal lines 102 are arranged in a substantially orthogonal manner. The scanning line 101 is connected to a row driver (not shown), and gate electrodes of the plurality of switching elements (TFTs) 103 are connected to the corresponding scanning lines 101, respectively.

The gate electrode voltage supply to each of the gates of the plurality of TFTs 103 is performed through the scanning line 101 from the left side (the input side of the scan line) to the right side (the terminal side of the scan line) as shown in FIG. In Fig. 1, two upper and lower TFTs 103 arranged on the left side, that is, switching elements 103 (m-1, n) and 103 (m, n) are arranged on the input side of the scanning line and on the right side thereof. The two upper and lower TFTs 103 arranged, that is, the switching elements 103 (m-1, n + 1) and 103 (m, n + 1) are arranged on the terminal side of the scanning line. However, in FIG. 1, these four TFTs 103 are shown by drawing manufacture, and the actual display element arrange | positions the switching element 103 much more than these.

The plurality of signal lines 102 are connected to a column driver (not shown), and the source electrodes of the plurality of switching elements 103 corresponding thereto are connected to the plurality of signal lines 102, respectively.

Further, each drain electrode of the plurality of switching elements 103 is connected to the corresponding pixel electrode 107, respectively, and furthermore, between the storage electrode 105 and the liquid crystal capacitor 104 between the pixel electrode 107 and the counter electrode (not shown). To form.

The switching element (TFT) 103 is, for example, a thin film transistor including amorphous silicon as a semiconductor layer. The parasitic capacitance 106 is interposed between the drain electrode and the gate electrode of the TFT 103 due to its structure. The technical idea of the present invention is not to reduce or eliminate the parasitic capacitance 106, but to actively use it, but the arrangement and size of the gate electrode 201 are designed in advance so that the size can be set to a desired value. .

The (m-1, n) th TFT 103 is arranged electrically connected to the (m-1) th scan line 101 and the nth signal line 102. The (m, n) -th TFT 103 is disposed in electrical connection with the m-th scanning line 101 and the n-th signal line 102. The (m-1, n + 1) th TFT 103 is disposed in electrical connection with the (m-1) th scan line 101 and the (n + 1) th signal line 102. The (m, n + 1) th TFT 103 is disposed in electrical connection with the mth scan line 101 and the (n + 1) th signal line 102.

FIG. 2 shows a plan view of the TFT 103 provided in Embodiment 1 shown in FIG. FIG. 2A shows arbitrary (m-1, n) th and (m, n) th of the plurality of TFTs 103 arranged in the matrix shape of FIG. 1, and FIG. (M-1, n + 1) th and (m, n + 1) th of 103).

In Figs. 2A and 2B, scanning line signals (gate signals) are applied from left to right, with these drawings in mind. That is, the TFT shown in Fig. 2A is disposed on the signal input side, and the TFT shown in Fig. 2B is disposed on the terminal side (terminal side).

The difference between (a) and (b) in FIG. 2 is such that the area of the overlapping portion 204 of the gate electrode 201 and the drain electrode 203 of the TFT, that is, the parasitic capacitance 106 is set to a predetermined value, One side of the drain electrode 203 that is not opposed to the electrode 202 is adjusted so that the width W2 is adjusted. In other words, in the present invention, a space portion for adjusting the size of the drain electrode is clearly prepared on the scanning line, i.e., in the vicinity of the surface opposite to the signal line of the pixel output wiring portion on the gate electrode 201. Here, the space portion is an area where no wiring or element exists on the same layer as the scan line (gate electrode 201) and signal line (source electrode 202), that is, the insulating film 207. In other words, the flicker suppressing means for adjusting the parasitic capacitance of the present invention includes the drain electrode 203 corresponding to the pixel output wiring portion, and the gate electrode 201 prepared for adjusting the wiring width W2 of the drain electrode 203. It is comprised by having a space part provided through the insulating film 207 in the figure.

In addition, one end of the drain electrode 203 is disposed on the same line as the one end of the gate electrode 201 or beyond it. That is, the drain electrode 203 is provided to exceed the width W1 of the gate electrode 201. As a result, the adjustment range of the parasitic capacitance 106 caused between the gate electrode 201 and the drain electrode 203 can be widened.

In addition, the entirety of the source region S and the drain region D of the TFT is disposed so as not to come out of the gate electrode 201. As a result, since the drain electrode 203 can be extended to the end of the gate electrode 201, the adjustment range of the parasitic capacitance 106 can be further extended.

In addition, adjustment and setting of the parasitic capacitance 106 between the gate and the drain of the TFT may be increased in the unit of the TFT 103 from the input end side of the scanning line 101 to the terminal side, or in the unit of the TFT 103. May be a block unit of a liquid crystal display element, and for example, the parasitic capacitance 106 between the gate and the drain of the TFT 103 in each section is divided by dividing from the input end side of the scanning line to the terminal side (end). You may make it substantially constant. That is, the size of the parasitic capacitance 106 may be set to three types.

As shown in FIG. 2, the gate electrode 201 shares a part of the scan line 101. In addition, part of the signal line 102 is shared by the source electrode 202. The drain electrode 203 is connected to the drain region D and shares a part of the pixel output wiring portion 206. One end of the pixel output wiring portion 206 represents the overlapping portion 204 of the gate electrode 201 and the drain electrode 203 connected to the pixel electrode 205 in an oblique portion. The overlapping portion 204 of the gate electrode 201 and the drain electrode 203 is a parasitic capacitance region portion of the TFT 103 and forms part of the flicker suppression means of the present invention.

FIG. 2 shows that the source electrode 202 (signal line 102) and the drain electrode 203 are disposed opposite or parallel to at least in the vicinity of the gate electrode 201, and these two electrodes may be the gate electrode 201. It is arrange | positioned substantially orthogonally to (the scanning line 101). The source electrode 202 is connected to the source region S of the TFT 103 formed of an amorphous silicon layer, for example, and the drain electrode 203 is connected to the drain region D, respectively. As is apparent from FIG. 2, the electrode width W1 of the gate electrode 201 is set to a width wider than the electrode width W2 of the drain electrode 203. The area of the overlapping portion 204 of the gate electrode 201 and the drain electrode 203 is represented by the product of the electrode width W1 and W2. Therefore, if the electrode width W1 of the gate electrode 201 is set as large as possible (width), the electrode width W2 of the drain electrode 203 can be made small when the same area is required.

The gate electrode 201 is formed on an insulating substrate such as glass, for example. Referring to FIG. 6, the gate electrode 201 is formed on, for example, an insulating substrate (not shown). Since only one electrode of the storage capacitor 105 (not shown) is formed on this insulating substrate, the electrode width W1 of the gate electrode 201 may be considered by considering only one size of the storage capacitor electrode. Therefore, according to another example, the width and length of the gate electrode can be set so as not to depend on the sizes of the source electrode 202 and the drain electrode 203. In addition, if the electrode width W1 of the gate electrode 201 is made as large as possible (wide), the secondary effect of flattening the liquid crystal display element almost equally can be obtained.

That is, the present invention is to set the electrode width W1 of the first gate electrode 201 as large as possible. The second source electrode 202 and the drain electrode 203 are disposed substantially parallel to each other, but are disposed substantially perpendicular to the gate electrode 201. The parasitic capacitance between the third gate electrode 201 and the drain electrode 203 is adjusted by adjusting the width of the drain electrode 203 in the longitudinal direction of the gate electrode.

Next, the case where the value of the parasitic capacitance 106 is specifically set and adjusted is demonstrated. In the present embodiment, in the step of forming the thin film pattern constituting the drain electrode 203 of the TFT 103, by changing the exposure stage scan speed or exposure amount during exposure and controlling the reduction correction value, Fig. 2 As shown in Fig. 2, an active matrix liquid crystal display device having a pattern in which the parasitic capacitance region of the nth TFT in the scanning direction of the scanning line 101 is smaller than the parasitic capacitance region of the (n + 1) th TFT was formed. . The pattern of this structure was applied to the 13.3 type * GA liquid crystal panel, and the opposing voltage optimum value (optimum value of flicker characteristic) of the voltage supply terminal, center part, and terminal of the scanning line 101 was measured.

3 shows measurement results of opposing voltage optimum values of the present invention and the conventional example. The curve 31 of FIG. 3 shows the measured value of the liquid crystal panel of a conventional structure. In a conventional panel, a difference of about 0.3 V occurs near the voltage supply source and the terminal end, and flicker can be confirmed even if the entire surface of the liquid crystal panel is adjusted to the opposing voltage optimum value. And the curve 32 shows the measured value of the liquid crystal panel by the structure of Example 1, the difference between a voltage supply terminal and a former terminal is suppressed to 0.1V or less, and when it adjusts to an opposing voltage optimum value, flicker is not confirmed and a display screen Uniformity of characteristics is greatly improved.

FIG. 6 is a sectional view of a portion shown in plan view of the TFT 103 of FIG. The gate electrode 201 is formed on an insulating substrate, for example, not shown. The gate electrode 201 shares a part of the scan line. In addition, the source electrode 202 shares a part of the signal line. The drain electrode 203 shares a part of the pixel output wiring portion. The overlapping portion 204 of the gate electrode 201 and the drain electrode 203 is shown by a dotted line and an arrow.

(Example 2)

The equivalent circuit of the active matrix liquid crystal display element of Example 2 is shown in FIG. 1 which is the same drawing as the equivalent circuit shown in Example 1. FIG. In this embodiment, in the step of forming the thin film pattern constituting the drain electrode 203 of the TFT 103, n is connected to the scanning line 101 at the time of exposure, as shown in Fig. 4A. The width Wn of the drain electrode 204 of the first TFT is smaller than the width W (n + 1) of the drain electrode 204 of the (n + 1) th TFT, as shown in Fig. 4B. The width of each drain electrode was controlled by using a photomask so as to form an active matrix liquid crystal display device in which the parasitic capacitance between the gate and the drain of the TFT 103 was adjusted. The pattern of this structure was applied to the 13.3 type * GA liquid crystal panel, and the opposing voltage optimum value (optimum value of flicker characteristic) of the voltage supply terminal, center part, and terminal of a scanning line was measured.

Curve 33 in FIG. 3 shows measured values of the liquid crystal panel of Example 2. FIG. The difference between the voltage supply end and the front end of the opposing voltage optimum value of the liquid crystal panel of Example 2 was 0.1 V or less, and flicker was not confirmed, and the uniformity of the display screen characteristics was greatly improved.

As described above, according to the liquid crystal panel having the active matrix liquid crystal display element of the configuration of the present invention, the influence of the wiring delay and the parasitic capacitance of the TFT, which are very big problems in panel design due to the enlargement and high definition of the liquid crystal panel By having an in-plane distribution in the parasitic capacitance with respect to image quality problems such as flicker caused by the above, it is possible to improve the uniformity of the display screen and to realize a high-quality liquid crystal panel.

Claims (8)

A plurality of switching elements including a plurality of scan lines, a plurality of signal lines, a plurality of pixel electrodes, a scan line input unit, a signal line input unit, and a pixel output wiring unit are disposed on a substrate, and the signal line input unit and the pixel output wiring unit face each other, or Or substantially parallel to each other, and they are arranged in a matrix shape substantially perpendicular to the scan line, and the pixel electrode and the switching element are provided near the intersection of the scan line and the signal line, and the scan line input portion of the switching element is provided. In the active matrix liquid crystal display device wherein the scanning line is connected, the signal line is connected to the signal line input portion of the switching element, and the pixel electrode is connected to the pixel output wiring portion of the switching element. Flicker suppression means for suppressing flicker of the display screen caused by the feedthrough voltage of the active matrix liquid crystal display element being different at the input terminal side of the scanning line and the terminal side thereof is provided in the vicinity of the pixel output wiring section. Active matrix liquid crystal display device. The method of claim 1, And said flicker suppressing means is arranged in a portion away from said signal line input part in said pixel output wiring part. The method of claim 1, The parasitic capacitance of the flicker suppression means is adjusted by adjusting the wiring width of the pixel output wiring portion in a space prepared near the pixel output wiring portion on the scanning line. The method according to any one of claims 1 to 3, The scanning line is connected to the gate electrode of the TFT, the signal line is connected to the source electrode, and the pixel output wiring part is connected to the drain electrode, and the parasitic capacitance adjustment in the flicker suppression means is a part of the drain electrode which is far from the source electrode. It is performed by width adjustment, The active-matrix type liquid crystal display element characterized by the above-mentioned. The method of claim 1, The size of the parasitic capacitance from the input end side of the scanning line to the terminal side in the flicker suppressing means is smaller in the input end side, and the terminal side is larger in the active matrix liquid crystal display element. The method of claim 5, Capacitive adjustment in the flicker suppression means is performed in block units from the input end side of the scanning line to the terminal side thereof. In the method of manufacturing the active-matrix liquid crystal display element in any one of Claims 1-6, A method of manufacturing an active matrix liquid crystal display device characterized by changing the exposure conditions so that the flicker suppressing means is provided. In the method of manufacturing the active-matrix liquid crystal display element in any one of Claims 1-6, A flicker suppression means is provided in the specification of an exposure mask, The manufacturing method of the active-matrix type liquid crystal display element characterized by the above-mentioned.