KR20000061461A - Pre-charging circuit of bit line in semiconductor memory - Google Patents

Abstract

A bit line precharge circuit in a semiconductor memory device is disclosed. In the semiconductor memory device according to the present invention, a bit line precharging circuit includes a memory cell array including a plurality of memory cells for storing data, a selector for selecting a bit line of a memory cell in response to a selection signal, and a bit line of a selected memory cell Connected between a current detection amplifier and a current detection amplifier and a selector for detecting and amplifying data stored in the selected memory cell through current detection flowing in the circuit, the current flowing through the bit line of the selected memory cell is detected, and the detected current is above a predetermined level. In this case, the connection between the current detection amplifier and the bit line of the selected memory cell is disconnected for a predetermined time, and the bit line is precharged to the excitation voltage for a predetermined time, and when the bit line is charged to the excitation voltage, the current detection amplifier and Automatic pre-charging means to reconnect the bit line It is characterized in that, by using the excessive current flows in the bit line at the initial stage when the bit line is selected, if the excess current flows more than a predetermined level in the bit line, the current detection amplifier and the bit line is blocked for a predetermined time, This allows the bitline to charge quickly for a long time, allowing for quick retrieval of data in the off-cell state.

Description

Pre-charging circuit of bit line in semiconductor memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a precharge circuit of a bit line for rapidly charging a bit line to an excitation voltage so as to read data in an off-cell state quickly in a semiconductor memory device such as a flash memory.

In general, in order to read data stored in a memory cell in a semiconductor semiconductor memory device such as a flash memory, a signal to first read the information to the corresponding cell or switch. The method of designating the position of the desired cell is a two-dimensional matrix structure. The line connected to the gate of the transistor is called a word line and is connected to the drain of the transistor. A line is called a bit line. At this time, in order to read information from the memory cell array, a preceding operation is required to excite (enable) the word line and the bit line.

Meanwhile, in the case of a flash memory, data stored in a memory cell is detected by detecting an amount of current flowing through a bit line. Therefore, a current sensing amplifier is used to detect the current flowing through the bit line to detect data stored in the memory cell, and the time required for data detection depends on how quickly the current flowing through the bit line finds a steady state. Depends.

For example, in the case of an on cell, the current flowing through the bit line must flow above a certain reference current to detect information. In this case, the information detection time is determined according to the speed at which the word line is excited. On the other hand, in the case of an off cell, the current flowing through the bit line must flow below the reference current to detect the information. In this case, the information detection time is determined according to the speed at which the bit line is excited. However, in the case of off-cell, excessive bit line charging current is supplied to the bit line while charging to the excitation voltage to excite the bit line. In this case, the current detection amplifier detects such an excessive bit line charging current, so that the bit line is read on the cell regardless of data stored in the memory cell charged with the excitation voltage. Therefore, in the case of the off-cell, the time for which the bit line is charged to the excitation voltage is shortened to increase the data detection time.

As a result, word lines and bit lines need to be excited quickly in order to speed up data detection in on and off cells. However, it is sometimes impossible to quickly excite both word lines and bit lines due to the structure of the circuit. In this case, the off-cell information detection time takes a long time. In such a case, a separate precharge circuit is used to quickly charge the bit line to the excitation voltage at the off-cell. A bit line precharge circuit Address Change Detector (ATD) is used. However, in the case of the flash memory, there is a problem that using the ATD, the circuit is complicated and takes a considerable time to use the ATD.

An object of the present invention is to charge a bit line by sensing current flowing through the bit line without address change information in a semiconductor memory device in which it is difficult to precharge the bit line through an address change detector (ATD) such as a flash semiconductor memory device. A bit line precharge circuit of a semiconductor memory device is provided.

1 is a diagram for describing a bit line precharging circuit in a semiconductor memory device according to the present invention.

FIG. 2 is an embodiment according to the present invention of the automatic precharge unit shown in FIG. 1.

3A to 3C are diagrams showing currents or voltages of respective parts of the circuit shown in FIG.

4 is a view for comparing the charging of the bit line according to the prior art and the present invention.

FIG. 5 is a diagram illustrating a specific implementation circuit of the automatic precharge unit illustrated in FIG. 2.

6A and 6B are diagrams illustrating pulse generation in a pulse generator.

In order to achieve the above object, a bit line precharge circuit in a semiconductor memory device according to the present invention includes a memory cell array including a plurality of memory cells for storing data, a selector for selecting a bit line of a memory cell in response to a selection signal, A current detection amplifier and a selector connected between a current detection amplifier and a selector for detecting and amplifying data stored in the selected memory cell through current detection on the bit line of the selected memory cell detects a current flowing in the bit line of the selected memory cell, and the detected current is predetermined. When the level is above the level, the connection between the current detection amplifier and the bit line of the selected memory cell is interrupted for a predetermined time, precharges the bit line to the excitation voltage for a predetermined time, and detects the current when the bit line is charged to the excitation voltage. Automatic Precharger Reconnects Amplifier and Bitline It characterized in that it comprises a.

Hereinafter, a bit line precharge circuit in a semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.

1 is a diagram for describing a bit line precharging circuit in a semiconductor memory device according to the present invention. 1 to 11 are current sense amplifiers, 13 are automatic precharges, 15 are selectors (MUX), and 17 are memory cell arrays, respectively.

Referring to FIG. 1, the memory cell array 17 includes a plurality of memory cells that store data, and the selector 15 selects a bit line of the memory cell in response to the selection signal S. Referring to FIG. The current detection amplifier 11 detects and amplifies data stored in the selected memory cell through current detection flowing through the bit line of the selected memory cell. The automatic precharge unit 13 is connected between the current detection amplifier 11 and the selector 15 to detect a current flowing in the bit line of the selected memory cell. When the detected current reaches a predetermined level or more, the current detection amplifier 11 is disconnected from the bit line of the selected memory cell and the bit line of the selected memory cell is charged to the excitation voltage. When the bit line of the selected memory cell is fully charged to the excitation voltage, the current detection amplifier 11 is connected to the bit line of the selected memory cell so that the current detection amplifier 11 detects a current flowing in the bit line, Detect stored data.

In general, when an off-cell bit line is selected in a flash semiconductor memory device, an excessive charge current causes an excessive amount of current to flow over the bit line while charging the bit line to an excitation voltage to excite the bit line. . Therefore, a sense amplifier that detects the current flowing in the bit line and detects the data stored in the memory cell, turns on the off-cell due to the excessive current flowing in the bit line while charging the bit line to the excitation voltage at the beginning of the selection of the new bit line. Will be read incorrectly.

The present invention utilizes the current characteristics flowing in the bit line, and the automatic precharge unit 13 detects the current flowing in the bit line of the selected memory cell, and when the detected current is above a predetermined level, the current detection amplifier 11 and The bit line of the selected memory cell is disconnected. As such, the current detection amplifier 11 and the bit line of the selected memory cell are disconnected, thereby preventing the current detection amplifier 11 from detecting excessive charging current for charging the bit line to the excitation voltage. In addition, while the connection between the current detection amplifier 11 and the bit line of the selected memory cell is disconnected, the bit line is rapidly charged, and when the charging to the excitation voltage is completed and the current flowing through the bit line is normalized, the current detection amplifier 11 is again. ) And the bit line of the selected memory cell can be used to speed up information detection.

2 is an embodiment according to the present invention of the automatic pre-charging unit 13 shown in FIG. The automatic precharge unit 13 according to the present invention includes a switch 21, a current charger 23, a resistor 25, a current flow detector 27, and a pulse generator 29. The connection terminal A is connected to the current detection amplifier 11, and the connection terminal B is connected to the selector 15, respectively.

Referring to FIG. 2, the current charger 23 may pass a current flowing through a bit line of a memory cell selected by the selector 15 or charge a bit line of the selected memory cell in response to the pulse signal CS. Generates charging current. The switch 21 is connected between the current detection amplifier 11 and the current charging unit 23, and the current detection amplifier 11 detects the current flowing in the bit line of the selected memory cell in response to the pulse signal CS. To control. The resistor 25 is connected between the current charging 23 and the bit line of the selected memory cell. The current flow detector 27 detects the voltage between both ends of the current through the resistor 25, and generates an output voltage of the second predetermined level when the voltage between the resistor 25 becomes equal to or greater than the first predetermined level. The pulse generator 29 generates a pulse signal CS having a predetermined duty when the voltage generated by the current flow detector 27 reaches a second predetermined level.

That is, when the bit line starts to be charged, a large amount of current flows initially in the bit line, which causes the voltage across the resistor 25 to be above the first predetermined level. As such, when the voltage across the resistor 25 is greater than or equal to the first predetermined level, the pulse generator 29 generates a predetermined duty when the current flow detector 27 generates the output voltage having the second predetermined level by the pulse generator 29. A pulse signal CS is generated.

As a result, the connection of the current detection amplifier 11 and the bit line is interrupted by the switch 21 during the predetermined duty in which the pulse signal CS is generated, and the bit line is quickly charged by the current charging unit 23.

On the other hand, the resistor 25 according to the present invention may be a variable size of the resistance by the pulse signal (CS). That is, while the bit line is being charged, the resistance size of the resistor 25 is made small so that the bit line can be charged quickly, and while the bit line is not being charged, the resistance size of the resistor 25 is made large. Here, when the bit line is not charged, the bit line is charged and the charging is completed. First, before the bit line is charged, the resistance size of the resistor 25 is increased to increase the voltage across the resistor 25. In addition, when charging is completed, the resistance of the resistor 25 is increased to prevent current from flowing back to the current detection amplifier 11 when the bit line is charged excessively.

3A to 3C are diagrams showing currents or voltages of respective parts of the circuit shown in FIG. 2, and FIG. 3A shows an amount of current flowing in a bit line detected by the current detection amplifier 11, and FIG. 3B shows a pulse. The pulse signal CS generated by the generator 29 is shown, and FIG. 3C shows the charging current supplied from the current charging section 23, respectively.

3A to 3C, the current detection amplifier 11 detects that an excessive current, such as 35a, flows in the initially selected bit line when the bit line is changed, and when such an excessive current is detected, the pulse generator 29 is shown in FIG. The pulse signal CS is generated for a predetermined time as shown in 3b. While the pulse signal CS is generated, the switch 21 is turned off to disconnect the current detection amplifier 11 and the selected bit line, thereby preventing the current detection amplifier 11 from detecting a current flowing in the bit line. In addition, while the pulse signal CS is generated, the current charging unit 23 generates a charging current as shown in FIG. 3C to charge the selected bit line. At this time, the current charger 23 must supply sufficient current to the bit line so that the bit line is charged while the pulse signal CS is generated. After a predetermined time, the charging of the bit line is completed, and the current detection amplifier 11 detects the current 35b flowing in the bit line in the off-cell state.

As described above, the current flowing in the bit line in the off-cell state is lower than the reference current 31. Referring to FIG. 3A, in the case of the off-cell, the current flowing in the bit line during charging of the bit line is larger than the reference current 31 as shown in 33, and thus data detection is not performed while the bit line is being charged. However, in the present invention, the bit line is charged for a short time during which the pulse signal CS is generated, so that data detection in the off-cell state can be accelerated.

4 is a view for comparing the charging of the bit line according to the prior art and the present invention. In FIG. 4, 41 is a charging curve of a bit line according to the prior art, 43 is a curve conceptually showing a process of charging a bit line according to the present invention, and 45 is a bit line charged to an excitation voltage according to the present invention. It seems to be a curve.

Referring to FIG. 4, the charging curve according to the prior art is an excitation voltage at which the final charging voltage is excited by a bit line. On the other hand, in the charging curve of the bit line according to the present invention, when the charging voltage of the bit line reaches the excitation voltage because the final charging voltage is higher than the excitation voltage, the bit voltage is maintained in a faster time than before by maintaining the excitation voltage as shown in curve 45. The line can be excited.

FIG. 5 is a diagram illustrating a specific implementation circuit of the automatic precharge unit illustrated in FIG. 2. Referring to FIG. 5, M27 and M29 are switches 21, M17 to M25 are current charging units 23, M3 to M9 and inverters 51 and 53 are current flow sensing units 27, and M13 and M15. Is a resistor 25, C1 to C4, M1 and M2, M10 and M11 and inverters 55, 57, 61, 63 and 65 constitute pulse generators 29a and 29b, respectively.

First, M9 constituting the current flow detecting unit 27 is a kind of resistance, and the voltage is applied to both ends by excessive current flow in the initial stage of the bit line charging, and this voltage is input to the differential amplifiers composed of M4 to M8. . The signals output from the differential amplifiers of the current flow detector 27 are input to the pulse generators 29a and 29b, respectively. The pulse generators 29a and 29b discharge the charged charge using the momentarily short pulse and the large NMOS transistors M11 and M2, and then slowly charge using the small PMOS transistors M10 and M1. Pulses.

6A and 6B are diagrams for explaining pulse generation in the pulse generator 29. Figure 6a shows a curve that is discharged and charged by M11 or M2 and M10 or M2, respectively. FIG. 6B shows the pulse signal obtained from the discharge / charged curve shown in FIG. 6A.

In this way, the pulse signal generated by the pulse generators 29a and 29b operates the current charging section 23 and controls the switch 21 to cut off the current detection amplifier 11 and the current charging section 23. In addition, the resistor 25 is controlled so that the resistance size of the resistor 25 becomes small to quickly charge the bit line. The resistor 25 and the switch 21 can be simply configured by connecting two MOS transistors in parallel as shown in the figure. In addition, the current charging unit 23 is composed of PMOS and NMOS transistors, and includes an NMOS diode (M25) to charge over the excitation voltage, to prevent the charge on the excessive voltage and to escape the charge on the bit line. Configured. As such, the current charging unit 23 charges the bit line to a potential higher than the excitation voltage of the bit line as shown in curve 43 in FIG. 4, so that the bit line can be quickly charged to the excitation voltage.

As described above, the bit line pre-charging circuit in the semiconductor memory device according to the present invention utilizes that excessive current flows in the bit line at an initial stage when the bit line is selected, so that an excessive current of more than a predetermined level flows in the bit line. Since the detection amplifier and the bit line are blocked for a predetermined time and the bit line is rapidly charged during the block, the data can be quickly retrieved in the off-cell state.

Claims (3)

A memory cell array consisting of a plurality of memory cells for storing data; A selector for selecting a bit line of the memory cell in response to a selection signal; A current detection amplifier configured to sense and amplify data stored in the selected memory cell through current detection flowing through a bit line of the selected memory cell; And A current connected between the current detection amplifier and the selector to detect a current flowing in the bit line of the selected memory cell, and when the detected current is above a predetermined level, the connection of the current detection amplifier and the bit line of the selected memory cell is predetermined. An automatic precharging means for blocking the time, precharging the bit line to an excitation voltage for the predetermined time, and reconnecting the current detection amplifier and the bit line when the bit line is fully charged to the excitation voltage. And a pre-charging circuit of the bit line in the semiconductor memory device. The method of claim 1, wherein the automatic pre-charging means A current charger configured to pass a current flowing through a bit line of the selected memory cell in response to a pulse signal or generate a charging current for charging the bit line of the selected memory cell to the excitation voltage; A switch connected between the current detection amplifier and the current charging unit and controlling the current detection amplifier to detect a current flowing in a bit line of the selected memory cell in response to the pulse signal; A resistor connected between the current charger and a bit line of the selected memory cell; A current flow detector for detecting a current passing through the resistor, and generating an output voltage having a predetermined level when the detected current becomes above the predetermined level; And And a pulse generator for generating the pulse signal in response to the output voltage generated by the current flow detector. The method of claim 2, wherein the resistor And a magnitude of a resistor is variable in response to the pulse signal.