KR20000059830A - A fuse array in a semiconductor device and a fabricating method thereof - Google Patents

Abstract

PURPOSE: A fuse array of a semiconductor device and forming method thereof is to minimize the area of the fuse array and allow the fuse to be operated electrically, thereby preventing the degeneration of the semiconductor device. CONSTITUTION: A fuse array of a semiconductor device comprises: a first interconnection connected to a signal input; a second interconnection connected to a signal output; and a transistor(51) having a gate insulator made of a ferroelectric, placed between the first interconnection and the second interconnection and for electrically switching the first and second interconnections. A forming method of a fuse array comprises the steps of: forming an insulating layer on a semiconductor substrate having a MOS(Metal oxide semiconductor) transistor(51) having source, drain and gate made of ferroelectric; forming first to third contact hole to expose a selected portion of the source, drain and gate; forming first to third plug to fill the first to third contact holes; and forming first to third interconnections connected to the first to third plugs.

Description

Fuse Array of Semiconductor Device and Formation Method {A FUSE ARRAY IN A SEMICONDUCTOR DEVICE AND A FABRICATING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuse array of a semiconductor device and a method of manufacturing the same. In particular, in order to repair a defective portion that occurs during a PAB process in manufacturing a memory device of a semiconductor device, an end portion of a memory array and a redundancy line ( Instead of polysilicon, fuses connecting redundancy lines are formed of transistors that operate electrically, resulting in high integration and simplicity of circuits, and the manufacture of transistor fuse arrays for semiconductor devices that eliminate the need for expensive fuse-cutting laser equipment. It is about a method.

As semiconductor technology has rapidly developed and the degree of integration of circuits has been greatly increased, the storage capacity of semiconductor memories has also increased greatly. That is, a very large number of memory cells can be integrated in one memory chip. If any one of these memory cells fails, the chip becomes unusable and treated as defective. This lowers yield and is very inefficient.

Therefore, a method of increasing yield by preparing a spare memory cell on a chip and replacing a defective memory cell with a spare memory cell has been adopted. Because of the increase in the chip area due to the spare memory cell and the addition of a test process necessary for defect repair, it is not practically used in general logic circuits. However, in the memory field, the area occupied by the spare memory cell is larger than that of the general memory cell array. Since it is relatively small, it has been adopted in earnest from 64M to 256M DRAM.

According to the conventional method of forming a fuse of a semiconductor device, an oxide film is formed on a silicon substrate, and then a doped polysilicon is deposited thereon, and then patterned to form a fuse, and an insulating layer for insulating the fuse and the metal wiring is formed thereon. After that, a contact hole for connecting the fuse and the slug wiring is formed by removing a predetermined portion of the insulating layer, and the multi-metal layer is formed on the entire surface by sputtering. At this time, the multi-metal layer is made of MoSi / Al / MoSi and the thickness is about 600/8000/400 mm 3, the multi-metal layer may be formed of TiN / polysilicon.

Subsequently, a photolithography process for forming a metal wiring is performed to form a fuse made of polysilicon, and the fuse is cut as needed using a laser.

In this case, the pep process of the semiconductor device generally refers to a process of forming a passivation layer and then opening the pad part.

In the prior art, a process of inspecting a defective product and repairing a defective part after completing a chip on which a device of a semiconductor device is formed is as follows.

First, a probe test is performed in order to manufacture a chip having an element or the like formed on a wafer and to check for defects. If such a test determines that a defective product is found to be defective, the repairable product is entered into the next stage and the non-repairable product is disposed of.

Repairable products can be repaired by generating repair data, finding faulty parts, and precisely irradiating and cutting specific fuses that produce repair data. Thus, the repaired bad chip is converted into a good product.

1 is a circuit diagram of a fuse array of a semiconductor device according to the prior art.

Referring to FIG. 1, a plurality of true wirings 11 made of polysilicon or metal doped in a fuse array positioned between a memory cell array (not shown) and a redundant cell array (not shown) and serving as a switch are provided. It is formed on an interlayer insulating layer. In this case, the wirings are electrically connected to or cut from the required redundancy cells, and the cutting is performed by a physical method such as a laser.

At this time, reference numeral A1 denotes a wiring area cut by a laser, and this area is required to secure a minimum area, and damage to the substrate or its underlying layer due to laser cutting cannot be avoided.

Therefore, the addresses of the defective memory cells decoded from the row decoder (not shown) and the column decoder (not shown) are input to the fuse array in the form of an addressing input signal IN, and the necessary address of the redundancy cells as the addressing output signal OUT is required. It is connected to the address to heal the defect of the cell.

2 is a layout of a fuse array of a semiconductor device according to the prior art. In this case, the fuse is covered with an insulating layer such as an oxide film, but is omitted for convenience.

Referring to FIG. 2, a plurality of fuses 21 made of doped polysilicon or metal are formed on the insulating layer 20 in a wiring form. At this time, reference numeral A2 is a portion to be cut by a physical method using a laser or the like. Therefore, after testing a defect of a memory cell, this region is selectively removed to store data to be stored in the memory cell at a corresponding address of the redundancy cell.

FIG. 3 is a cross-sectional view of a fuse array of a semiconductor device according to the prior art, and is a cross-sectional view of the fuse line taken along the cutting line I-I 'of FIG. 2, and the same reference numerals are used as those of FIG. 2.

Referring to FIG. 3, a cross section of a fuse 21 to be cut by a laser among a plurality of fuses formed on an interlayer insulating layer 20 of a substrate (not shown) is illustrated.

When the fuse is cut, a part of the insulating film such as the oxide film 22 covering the fuse is also removed. It is essential to secure a minimum area A2 for such laser cutting, which in turn reduces the integration of the device.

4A through 4D are cross-sectional views illustrating a method of forming a fuse of a semiconductor device according to the related art.

Referring to FIG. 4A, a field oxide film 42 is grown on a predetermined portion of a silicon substrate 41 by LOCOS or a trench is formed and then embedded in an oxide film or the like. The field oxide film 42 is intended to block leakage current generated between the polysilicon fuse formed thereafter and the silicon of the substrate.

An impurity doped polysilicon layer 43 is deposited on the surface of the substrate 41 including the field oxide film 42 by CVD to form a thickness of about 2000 mm 3.

After the photoresist is applied on the polysilicon layer 43, the photoresist pattern 400 exposing the polysilicon layer 43 defined to be included in the field oxide film 42 formation region is defined as exposure and development.

Referring to FIG. 4B, a fuse 430 made of a polysilicon layer 43 remaining on the field oxide layer 42 by etching a polysilicon layer of a portion which is not protected from the photoresist pattern as an etching mask is etched. Form. At this time, a part of the surface of the field oxide film 42 and the surface of the substrate 41 are exposed. Next, the photoresist pattern is removed.

Referring to FIG. 4C, the insulating layer 44 for electrical insulation between the fuse and the metal wiring to be formed on the surface of the substrate 41 including the exposed fuse 430 surface and the field oxide film 42 surface may be formed of an oxide film or the like. By vapor deposition.

Next, a contact hole for connecting the metal wiring and the fuse 43, which exposes a predetermined portion of the fuse 43, is formed by removing a predetermined portion of the insulating layer 44 by a photolithography process.

MoSi is formed on the insulating layer 44 including the inside of the contact hole by the lower barrier metal layer 45 so as to have a thickness of about 600 kPa by the sputtering method, and thereafter, the aluminum layer 46 is also about 8000 kPa thick by the sputtering method. It is formed by vapor deposition, and the upper barrier metal layer 47 is formed thereon so as to have a thickness of about 400 GPa by the sputtering method to form metal wirings 45, 46 and 47.

Next, a photoresist is applied to the entire surface of the substrate including the surface of the upper barrier metal layer 47, and then the photoresist pattern 48 exposing most of the upper barrier metal layer 47 positioned on the field oxide film 42 is exposed and It is defined as a phenomenon and formed.

Referring to FIG. 4D, dry etching using the photoresist pattern as an etching mask is performed to remove the metal wires 45, 46, and 47 that are not protected therefrom, thereby exposing a part of the surface of the insulating layer 44. . At this time, a portion of the surface of the exposed insulating layer 44 is removed by performing excessive etching so that the metal wires 45, 46, 47 are cut reliably. Therefore, from this point on, the metal wires 45, 46, 47 are electrically connected only by the fuse 430.

Thereafter, the polysilicon fuse 430 is cut through a laser to supplement the cell if necessary through wafer inspection and probe test.

However, since the fuse forming method of the semiconductor device according to the related art described above uses polysilicon as a fuse, it is disadvantageous to manufacture a highly integrated device because it is necessary to secure the minimum area required for laser cutting. There is a concern that deterioration of the characteristics of the device by cutting, there is a problem that requires expensive laser equipment.

Accordingly, an object of the present invention is to form a fuse with a ferroelectric transistor instead of a fuse formed of a conventional conductor material, thereby minimizing the area required by the fuse part and forming a fuse that is electrically operated instead of a high temperature laser. Therefore, to provide a method of forming a fuse of the semiconductor device to prevent deterioration of the characteristics of the device.

A fuse array of a semiconductor device according to the present invention for achieving the above object is a semiconductor memory device having a memory cell and a redundancy cell, a plurality of first wiring connected to the signal input, and a plurality of first connected to the signal output And a plurality of transistors located between the second wiring and each of the first wiring and the corresponding second wiring to electrically switch the corresponding first wiring and the second wiring.

According to an aspect of the present invention, there is provided a power level detector of a semiconductor integrated circuit, comprising: a plurality of first wires connected to a power level signal input; a plurality of second wires connected to a power level signal output; And a plurality of transistors positioned between the first wiring and the respective second wirings to electrically switch the corresponding first wirings and the second wirings.

According to still another aspect of the present invention, there is provided a method of forming a fuse of a semiconductor device, the method including forming a morph transistor having a gate insulating film made of ferroelectric on a predetermined portion of a semiconductor substrate and having a gate, a source / drain, and a channel region; Forming an insulating layer on an entire surface of the substrate including a transistor, removing first portions of the insulating layer to form first to third contact holes exposing predetermined portions of the gate and the source / drain, respectively; Forming first to third plugs with a conductive material to fill the first to third contact holes, first wirings electrically connected to the first to third plugs, first wirings for applying a gate voltage, and second wirings for signal output And forming third signal input wirings on the insulating layer, respectively.

1 is a circuit diagram of a fuse array of a semiconductor device according to the prior art.

2 is a layout of a fuse array of a semiconductor device according to the related art.

3 is a cross-sectional view of a fuse array of a semiconductor device according to the prior art, and is taken along the line II ′ of FIG. 2.

4A through 4D are cross-sectional views illustrating a method of forming a fuse of a semiconductor device according to the related art.

5 is a circuit diagram of a transistor fuse array of a semiconductor device according to the present invention.

6A through 6B are cross-sectional views illustrating the operation of a transistor of a fuse array according to the present invention.

7A to 7B are cross-sectional views of a manufacturing process showing a method of forming a transistor of a fuse array of a semiconductor device according to the first embodiment of the present invention.

8A to 8B are cross-sectional views of a manufacturing process showing a method of forming a transistor of a fuse array of a semiconductor device according to the second embodiment of the present invention.

As a nonvolatile memory device, a metal-ferroelectric-semiconductor field effect transistor (hereinafter referred to as MFSFET) may be used. The operation of such MFSFET devices results from changes in drain current and channel surface charges due to the remanence polarization of ferroelectric materials.

The MFSFET device, which consists of a gate electrode, a ferroelectric gate insulating film, and a source / drain, enables the fabrication of high density memory devices due to the simple memory cell structure.

MFSFET devices of this structure provide non-destructive read-out characteristics. Non-destructive read-out provides short read-write operation cycles because the data read operation only needs to sense the drain current.

In order to repair defects occurring during the PAB process in the manufacture of memory devices in semiconductor devices, redundancy lines are typically provided at the ends of the memory array to cut specific fuse parts with a laser, thereby causing a specific bad bit line. Repair your back. In the present invention, the fuse is formed of a ferroelectric transistor that serves as a fuse.

That is, in the present invention, when a defect occurs in a part of a memory device such as a DRAM device to replace a cell of a defective part with a redundancy cell, a fuse necessary for using the redundancy cell is manufactured as a ferroelectric transistor in order to improve the yield of device fabrication. As a result, the area occupied by the fuse part and the damage occurring when the fuse part is cut are reduced. At this time, the ferroelectric transistor turns on / off by applying a voltage, thereby acting as a fuse.

In addition, the present invention provides a power level detector for preventing overload, a plurality of first wires connected to a power level signal input, a plurality of second wires connected to a power level signal output, and each of the first wires It is also used as a fuse array of a semiconductor integrated circuit composed of a plurality of transistors located between and corresponding to each of the second wirings to electrically switch the corresponding first and second wirings.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

5 is a circuit diagram of a transistor fuse array of a semiconductor device according to the present invention.

Referring to FIG. 5, a plurality of transistors including a transistor having a gate insulating film made of a ferroelectric in a fuse array positioned between a memory cell array (not shown) and a redundancy cell array (not shown) and serving as a switch, 51 is formed in the fuse array. At this time, each transistor constituting the fuse is in an on or off state as necessary. Therefore, the operation state of the transistor is determined according to the polarity of the gate bias voltage and the conductivity type of the MOS type device, and thus serves as a fuse while operating as a switching device. That is, the memory cell and the redundancy cell are in the electrically connected or disconnected state according to the on / off state of the transistor.

At this time, reference numeral A3 denotes the area occupied by the transistor as a fuse, which is smaller than the area required by the fuse-type fuse formed of a conductor using the laser cutting method of the prior art, and the substrate or the underlying layer thereof caused by laser cutting. To prevent damage.

Accordingly, the addresses of the defective memory cells decoded from the row decoder (not shown) and the column decoder (not shown) are input to the fuse array in the form of an addressing input signal IN, and the fuse array storing the address is an addressing output signal OUT. ) Is connected to the necessary address of the redundancy cell and the fuse 51 in the on state to heal the defect of the cell. At this time, the input signal is a comparison address input signal and the output signal is a comparison address output signal, or the input signal includes a comparison address power input and the output signal is connected to the memory cell or the redundancy cell.

By the same principle, the present invention is also used in a power level detector for protecting a circuit from overload in a semiconductor integrated circuit. That is, when it is determined that the detector is overloaded, the transistor of the fuse array is turned off according to the overload input signal to the fuse array to protect the circuit by opening the circuit.

6A to 6B are cross-sectional views illustrating the operation of the transistor of the fuse array according to the present invention, and FIG. 6A is a case where a positive voltage is applied to a gate, and FIG. 6B is a negative value to a gate. This is the case when voltage is applied. In this case, the substrate may be a separate silicon layer formed on the substrate on which the active region may be formed.

Referring to FIG. 6A, a gate insulating layer 61 made of a ferroelectric insulator and a gate electrode 62 are sequentially stacked on the active region of the silicon substrate 60, which is a semiconductor substrate 60, and is positioned around the gate 62. The source 64 and the drain 63 are formed at predetermined portions of the substrate 60 of the substrate 60.

When the channel region formed on the substrate surface between the gate insulating film 61 made of ferroelectric and the source / drain 64 and 63 is an N-type channel, when a positive voltage is applied to the gate 62, the gate 62 The electron density increases at the interface between the gate insulating film 61 in contact with the gate insulating film 61 and the electron density is also increased in the channel forming region in contact with the gate insulating film 61. Thus, a channel C is formed in the channel forming region so that the p-type transistor is turned on and the fuse is turned on. Has the same effect as is connected.

Referring to FIG. 6B, as in FIG. 6A, a gate insulating film 61 made of a ferroelectric and a gate electrode 62 are sequentially stacked on the active region of the silicon substrate 60, which is the semiconductor substrate 60, and the gate ( 62, the source 64 and the drain 63 are formed at predetermined portions of the substrate 60 around the substrate 60.

When the channel region formed on the substrate surface between the gate insulating film 61 made of ferroelectric and the source / drain 64 and 63 is an N-type channel, when a negative voltage is applied to the gate 62, the gate 62 is applied. The density of electrons decreases at the interface of the gate insulating film 61 in contact with the gate insulating layer 61, and the density of electrons decreases in the channel forming region in contact with the gate insulating film 61, thereby preventing a channel from being formed in the channel forming region. Therefore, the p-type transistor is kept in the turned off state, and has the same effect as if the fuse is blown.

The above example can be implemented by applying the same operation principle to the case where the ferroelectric transistor as the switching element is an N-type transistor having a P-type channel.

In the prior art, since a part of the wiring made of a conductive material is used as a fuse, the circuit is opened by cutting this portion with a laser if necessary, but in the present invention, a positive or negative voltage is applied to the gate of the ferroelectric transistor used as a fuse. By applying, the transistor is turned on / off as necessary to obtain a fuse role.

At this time, in the case of the ferroelectric transistor, the state is maintained even after the voltage applied to the gate is removed, so that the on / off state is continuously maintained. Therefore, it is very advantageous in terms of power consumption.

7A to 7B are sectional views of the manufacturing process showing the transistor forming method of the fuse array of the semiconductor device according to the first embodiment of the present invention.

Referring to FIG. 7A, an insulating film is formed to a predetermined thickness with a ferroelectric such as SrBi ₂ Ta ₂ O ₉ , Pb (Zr, Ti) O _3, or BaMgF ₄ on a silicon substrate 70, which is a semiconductor substrate, and then doped thereon. The conductive layer is formed by a conductor such as polysilicon by a sol-gel method, sputtering, or chemical mechanical deposition (CVD) method to a predetermined thickness. In this case, the silicon substrate 70 may be replaced by a silicon layer formed on the insulating layer, and the ferroelectric insulating film may be formed at the same time as the dielectric film forming process of the capacitor of the memory cell having a ferroelectric capacitor and transistor-gate connection (FCG) structure. .

A photoresist is applied on the conductive layer, followed by exposure and development using a mask defining a gate electrode to form a photoresist pattern (not shown) covering only the gate electrode formation portion.

The gate electrode 72 and the gate insulating film 71 are patterned by sequentially removing the conductive layer and the ferroelectric insulating film that are not protected by the photoresist pattern by dry etching.

Next, the ion implantation using the gate electrode 72 as an ion implantation mask is doped with an active region of the substrate using p-type impurity ions and then diffused into the highly doped impurity diffusion region 74 and drain 73. To form.

Therefore, the manufacturing of the p-type transistor having an n-type channel is completed, and the transistor serves as a fuse as a switching element. Since the operation description thereof has been described with reference to FIGS. 6A and 6B, a description thereof will be omitted.

Referring to FIG. 7B, electrical isolation between a fuse and a metal wiring to be subsequently formed on the surface of the substrate 70 including the exposed transistor surface and the field oxide (not shown) surface including the source / drain 74 and 73 surfaces. The interlayer insulating layer 75 is formed by depositing with an oxide film or the like.

Next, the photolithography process includes a metal wiring exposing predetermined portions of the source / drain 74 and 73 and a first and second contact holes for connecting transistors and a third contact hole for applying a gate voltage exposing the upper surface of the gate. The predetermined part of the insulating layer 75 is removed and formed.

Then, a conductive material such as polysilicon doped on the interlayer insulating layer 75 is filled by CVD to fill the first to third contact holes, and then the surface of the interlayer insulating layer 75 is used as an etch stop layer. Etch back is performed to form first to third plugs 76, 77, and 78 to fill the first to third contact holes. In this case, the first plug 76 and the second plug 77 are electrically connected to the drain 73 and the source 74, respectively, and the third plug 78 is connected to the gate electrode 72.

Next, a conductive layer such as metal is formed on the surface of the interlayer insulating layer 75 including the surfaces of the first to third plugs 76, 77, and 78, and then patterned by a photolithography process to form the first to third wiring lines ( 790,792,791 are formed at the same time. In this case, the first wiring 790 is connected to the drain 73 through the first plug 76, the second wiring 792 is connected to the source 74 through the second plug 77, and the third The wiring 791 is connected to the gate electrode 72 through the third plug 78 to supply a gate voltage. Therefore, from this point on, the first wiring and the second wiring are electrically connected or opened only by the fuse formed of the transistor.

8A to 8B are cross-sectional views of the manufacturing process showing the transistor forming method of the fuse array of the semiconductor device according to the second embodiment of the present invention.

Referring to FIG. 8A, an oxide film is deposited on the silicon substrate 80, which is a semiconductor substrate, by the CVD method to have a predetermined thickness with the first insulating layer 81.

The conductive layer is formed by depositing a conductive layer with a conductor such as polysilicon doped on the first insulating layer 81 to a predetermined thickness by a chemical mechanical deposition (CVD) method. A ferroelectric film, such as SrBi ₂ Ta ₂ O ₉ , Pb (Zr, Ti) O _3, or BaMgF ₄ , is formed on the conductive layer to form a gate insulating film. In this case, the ferroelectric film may be formed at the same time as the dielectric film forming process of the capacitor of the memory cell having a ferroelectric capacitor and transistor-gate connection (FCG) structure.

Then, a photoresist is applied on the ferroelectric film, followed by exposure and development using a mask defining a gate electrode to form a photoresist pattern (not shown) covering only the gate electrode formation portion.

The conductive layer and the ferroelectric film of the portion not protected by the photoresist pattern are sequentially removed by dry etching to pattern the gate insulating film 83 and the gate electrode 82 made of the ferroelectric. Then, the photoresist is removed.

Next, a second insulating layer 84 is formed by CVD using an oxide film on the first insulating layer 81 including the gate insulating film 83 and the gate electrode 82 by CVD. An etching back or chemical mechanical polishing (CMP) process is performed on the surface of the second insulating layer 84 to expose the surface of the gate insulating film 83, and at the same time, to form a flattened second insulating layer 84 surface.

Then, the undoped polysilicon layer 85 is formed on the exposed gate insulating film 83 surface and the second insulating layer 84 surface by CVD. At this time, the undoped polysilicon layer 85 is deposited to form an active region in which the source / drain and channel regions of the MFSFET device are formed.

Next, a photoresist is applied to the surface of the undoped polysilicon layer 85, and then exposure and development using a mask for forming a gate electrode are performed on the photoresist to form a photoresist pattern for an ion implantation mask.

Ion implantation using a photoresist pattern is performed by forming an impurity ion buried layer on a predetermined portion of the undoped polysilicon layer 85 using p-type impurity ions and then diffusing the source region 87 and the drain region 86 To form.

Accordingly, the manufacture of the p-type transistor having an inversed n-type channel is completed, and the transistor serves as a fuse as a switching element. Since the operation description thereof has been described with reference to FIGS. 6A and 6B, a description thereof will be omitted.

A third insulating layer 88 is formed as an interlayer insulating layer using an oxide film or the like on the polysilicon layer 85 including the sources / drains 87 and 86 and not being doped to serve as an insulating layer. The third insulating layer 88 is subsequently formed for electrical insulation between the active region and the wiring in the wiring forming process.

Referring to FIG. 8B, a photolithography process is performed on the predetermined portions of the third insulating layer 88 through the first and second contact holes for connecting the metal lines and the transistors to expose the predetermined portions of the source / drain 87 and 86. And a third contact hole for applying a gate voltage exposing the upper surface of the gate 82 by a photolithography process, the third insulating layer 88 / the undoped polysilicon layer 85 / gate insulating film 83 It forms by removing the predetermined part of). In this case, the third contact hole is formed to be offset so as not to overlap with the channel region so that a predetermined portion of the gate line formed by extending the gate electrode is opened and simultaneously overetched.

In addition, a conductive material such as polysilicon doped on the third insulating layer 88 is deposited by CVD to fill the first to third contact holes, and then the etch stop layer is formed on the surface of the third insulating layer 88. The first to third plugs 890, 891, and 892 filling the first to third contact holes are formed by performing an etch back. In this case, the first plug 890 and the second plug 891 are electrically connected to the drain 86 and the source 87, respectively, and the third plug 892 is connected to the gate 82.

Next, a conductive layer such as a metal is formed on the surface of the third insulating layer 88 including the surfaces of the first to third plugs 890,891,892, and then patterned by photolithography to form the first to third wirings 900,902,901. At the same time. In this case, the first wiring 900 is connected to the drain 86 through the first plug 890, and the second wiring 902 is connected to the source 87 through the second plug 891. The wiring 901 is connected to the gate 82 through a third plug 892 to supply a gate voltage. Therefore, from this point on, the first wiring and the second wiring are electrically connected or opened only by the fuse formed of the transistor.

Therefore, the fuse forming method of the semiconductor device according to the present invention greatly reduces the area occupied by the fuse array on the chip as compared with the prior art. In other words, the size of each fuse is reduced by controlling the connection between the wires using transistors rather than conductive wires.

In the present invention, since the connection or disconnection of the wiring is controlled by voltage, the damage of the device caused by laser cutting is prevented and the free space considering the damage of the device does not have to be considered.

In the present invention, the connection (short) or disconnection (open) of the wiring can be freely repeated.

In addition, since the ferroelectric transistor used in the present invention uses the residual magnetic properties, there is almost no power consumption.

Claims (10)

In a semiconductor memory device having a memory cell and a redundancy cell, A plurality of first wires connected to the signal inputs; A plurality of second wirings connected to the signal outputs; A fuse of a semiconductor device comprising several transistors, positioned between each of the first wirings and each of the corresponding second wirings, electrically switching the corresponding first and second wirings, and having a gate insulating film made of ferroelectric Array. The fuse array of claim 1, wherein the ferroelectric is formed of SrBi ₂ Ta ₂ O ₉ , Pb (Zr, Ti) O _3, or BaMgF ₄ . The fuse array of claim 1, wherein the signal input is a comparison address signal input and the signal output is a comparison address signal output. The fuse array of claim 1, wherein the signal input includes a comparison address power input and the signal output is connected to the memory cell or the redundancy cell through the second wiring. The semiconductor memory device of claim 1, wherein the semiconductor memory device comprises: a plurality of first wires connected to a power level signal input; a plurality of second wires connected to a power level signal output; and each of the first wires corresponding to the first wires. And a power level detector of a semiconductor integrated circuit comprising a plurality of transistors positioned between the second wirings and electrically switching the corresponding first wirings and the second wirings. Forming a MOS transistor having a gate insulating film made of ferroelectric on a predetermined portion of the semiconductor substrate and having a gate, a source / drain, and a channel region; Forming an insulating layer on an entire surface of the substrate including the morph transistor; Removing first portions of the insulating layer to form first to third contact holes respectively exposing predetermined portions of the gate and the source / drain; Forming first to third plugs of a conductive material filling the first to third contact holes; A first wire for applying a gate voltage electrically connected to the first to third plugs and electrically connected to the gate, and a second wire for signal output electrically connected to the source and a signal input electrically connected to the drain. Forming a third wiring on the insulating layer, respectively. The method of claim 6, wherein the ferroelectric is formed of SrBi ₂ Ta ₂ O ₉ , Pb (Zr, Ti) O _3, or BaMgF ₄ . The fuse forming method of claim 6, wherein the MOS transistor has an inverse structure in which the gate is formed under the gate insulating layer and the source and drain are positioned above the gate insulating layer. The method of claim 8, wherein when forming the inverse structure, the gate insulating layer is formed simultaneously with a process of forming a dielectric layer of a capacitor of a memory cell having a ferroelectric capacitor and transistor-gate connection (FCG) structure, and the first plug does not overlap the channel region. And a fuse forming method of the semiconductor device. The method of claim 6, wherein the semiconductor substrate is a semiconductor layer formed on an interlayer insulating layer.