KR20000054359A - noncontact type-card leader - Google Patents

Abstract

The present invention relates to a contactless card reader device that satisfies the standard of ISO / IEC 14443 and enables fast data transmission speed and high reliability access control. The present invention provides a method for receiving data transmitted from an IC card through an antenna. A preamplifier for preamplifying and outputting the amplified signal, a constant voltage circuit for providing a reference signal for converting the received signal into a pulse form, a filter outputted from the preamplifier, and providing the filtered signal and the constant voltage circuit. An amplitude limiting amplifier for converting a received signal into a pulse form by comparing the reference signal to be used; an effective signal recognition unit detecting a valid signal from a pulse signal output from the amplitude limited amplifier; Data demodulation section for demodulating data, receiving data transmitted from an IC card, In the case of transmitting the data to the controller, the clock generator for generating the necessary reference clock and the signal output from the valid signal recognition unit determine whether the received signal is normal, and if the received signal is valid, process the received data demodulated by the data demodulator. In addition, a non-contact card reader device is implemented as a control unit for outputting transmission data to be transmitted to the IC card, an amplification and modulation unit for power amplification, amplitude modulation, and transfer to the antenna side.

Description

Contactless card reader device {noncontact type-card leader}

The present invention relates to a contactless card reader device, and more particularly, to a contactless card reader device that satisfies the standard of ISO / IEC 14443 while enabling fast data transfer speed and high reliability access control.

More specifically, the present invention relates to a contactless card reader device for transmitting data corresponding to a wake-up signal from a microcomputer to an IC card through a transmitter, and reading desired data from the IC card.

In general, the card reader device is mostly contact type.

That is, when the IC card is in contact with a predetermined portion of the card reader, the card reader is configured to read data recorded on the IC card through data communication.

In this case, the IC card may be damaged due to contact, and a standard method (ISO / IEC 14443) for a contactless card reader has been proposed as a means to prevent such damage.

However, this standard method is only a standard method for a contactless card reader, and a contactless card reader device suitable for this is currently being developed.

Accordingly, an object of the present invention is to provide a contactless card reader apparatus that satisfies the ISO / IEC 14443 standard scheme, and which has a high data transmission speed and high reliability access control.

Contactless card reader device according to the present invention for achieving the above object,

A preamplifier for preamplifying and outputting data transmitted from the IC card through the antenna;

A constant voltage circuit providing a reference signal for converting the received signal into a pulse form;

An amplitude limiting amplifier configured to filter the signal output from the preamplifier, and convert the received signal into a pulse form by comparing the filtered signal with a reference signal provided from the constant voltage circuit;

An effective signal recognizing unit detecting a valid signal from the pulse signal output from the amplitude limiting amplifier;

A data demodulator for demodulating data from the pulse signal output from the amplitude limited amplifier;

A clock generator which generates a reference clock required when receiving data transmitted from the IC card or transmitting data to the IC card side;

A control unit for determining whether a received signal is normal according to the signal output from the valid signal recognition unit, processing received data demodulated by the data demodulator if the received signal is valid, and outputting transmission data to be transmitted to the IC card; Wow;

And an amplifier and a modulator for power amplifying and amplitude modulating the transmission signal output from the controller and transmitting the amplitude to the antenna.

1 is a block diagram showing the overall configuration of a contactless card reader device according to the present invention,

FIG. 2 is a circuit diagram illustrating an embodiment of the preamplifier of FIG. 1.

3 is a view showing the frequency characteristics of each part of FIG.

4 is a circuit diagram illustrating an example of the amplitude limiting amplifier and the constant voltage circuit of FIG. 1;

5 is a diagram illustrating input and output waveforms of each part of FIG. 4;

6A and 6B are circuit diagrams illustrating an embodiment of the effective signal recognition unit of FIG. 1.

7A to 7F are diagrams illustrating input / output waveforms of each part of FIG. 6,

8 is a circuit diagram illustrating an embodiment of a data demodulator of FIG. 1;

9A to 9G are diagrams illustrating input and output waveforms of each part of FIG. 8;

FIG. 10 is a circuit diagram illustrating an exemplary embodiment of the transmission amplifier and modulator of FIG. 1.

<Explanation of symbols for the main parts of the drawings>

200 ..... Preamplifier

400 ..... amplitude limiting amplifier

500 ..... valid signal recognition unit

600 ..... data demodulator

700 ..... dispensing

800 ..... Clock Generator

900 ..... Controls

1000 ..... amplification and modulator

Hereinafter, described in detail with reference to the accompanying drawings, preferred embodiments of the present invention according to the technical spirit as described above.

1 is a block diagram showing the overall configuration of a contactless card reader device according to the present invention.

Here, reference numeral 100 denotes an antenna for transmission and reception, reference numeral 200 denotes a preamplifier for pre-amplifying and outputting data transmitted from the IC card through the antenna 100, and reference numeral 300 denotes an antenna. A constant voltage circuit for supplying a circuit driving voltage is shown, and reference numeral 400 denotes an amplitude limiting amplifier for filtering a received signal output from the preamplifier 200 and converting the filtered signal into a pulse form.

Also, reference numeral 500 denotes an effective signal recognizing unit for detecting a valid signal from the pulse signal output from the amplitude limiting amplifier 400, and reference numeral 600 denotes data from the pulse signal output from the amplitude limiting amplifier 400. Denoting a data demodulator, a reference numeral 800 denotes a clock generator for generating a reference clock required when receiving data transmitted from the IC card or transmitting data to the IC card.

In addition, reference numeral 700 denotes a divider 700 for dividing the reference clock generated by the clock generator 800 to a predetermined level and providing the divided data to the data demodulator 600, and reference numeral 900 denotes the valid signal recognition unit. Determining whether or not the received signal is normal according to the signal output from the 500, and if the received signal is valid, processing the received data demodulated by the data demodulator 600, and outputs the transmission data to be transmitted to the IC card The control unit 1000 denotes a modulation and amplifying unit for power amplifying, amplitude modulating, and transmitting the transmission data output from the control unit 900 to the antenna 100.

The operation of the non-contact card reader device according to the present invention configured as described above will be described in detail with reference to FIGS. 1 to 10.

First, data transmitted from the IC card is received by the transmitting and receiving antenna 100 and then transferred to the preamplifier 200.

The preamplifier 200 preamplifies the received signal (847 kHz, BPSK modulation) into a signal suitable for detecting a weak signal.

Here, the preamplifier 200 has a circuit configuration as shown in FIG. 2.

As shown therein, low pass filters C1 and R1 for low pass filtering the signal received from the antenna 100, buffer amplifiers Q1 for buffering signals through the low pass filters C1 and R1, and the buffers. High frequency bypass filters RB1 to RB4 and CB1 to CB4 for filtering high frequency components of the received signal amplified by the amplifier Q1, and low pass filters R3 to R6 for low pass filtering the output signal of the buffer amplifier Q1. C2 to C4, Q2) and two-stage high pass amplifiers C5, R7, Q3, C6, R9, R10, and Q4 that sequentially amplify the signal through the low pass filter.

In FIG. 2, the resistors RB1 to RB4 and the capacitors CB1 to CB4 prevent the signal received by the high frequency bypass filter from affecting the power supply terminal. In addition, the diode D1 is a low loss pin diode PIN DIODE, and the capacitor C1 and the resistor R1 represent a low pass filter for removing input noise. In addition, the received signal induced in the antenna 100 is first amplified through Q1, which is a buffer amplifier, and noise is removed through a third-order low pass filter including resistors R3 to R6, capacitors C2 to C4, and transistors Q2. Next, the received signal through the buffer amplifier Q1 is amplified by a two-stage high pass amplifier composed of a capacitor C5, a resistor R7, a transistor Q3 and a capacitor C6, a resistor R9, and a resistor R10.

As a result, the preamplifier 200 is connected to the low pass filter and the high pass filter in series to implement a band pass filter, and at the same time, amplifies the signal into a signal suitable for detecting a weak reception signal.

3 shows frequency characteristics of the preamplifier.

As described above, the received signal pre-amplified by the preamplifier 200 is input to the amplitude limiting amplifier 400, and the amplitude limiting amplifier 400 filters the input signal and pulses using the reference signal. The signal is converted into a form and output.

4 is a circuit diagram illustrating an embodiment of the amplitude limiting amplifier 400 and the constant voltage circuit 300.

As shown in the drawing, the constant voltage circuit 300 compares the resistors R15 and R16 for dividing the input voltage Vcc with the divided voltage and the inverting terminal input voltage fed back and amplifies the difference voltage to obtain a reference voltage. A non-inverting amplifier 310 for outputting Vref).

In addition, the amplitude limiting amplifier 400 includes a coupling capacitor C11 for removing the direct current component of the input signal A and passing only the alternating current component, a signal through the coupling capacitor C11, and the reference voltage. A first inverting amplifier 410 for amplifying the difference voltage of (Vref), and a second inverting amplifier for inverting and amplifying the difference between the output signal of the first inverting amplifier 410 and the reference voltage Vref ( 420.

In FIG. 4, the capacitor C11 removes the DC component from the output signal A of the preamplifier 200 and blocks only the AC component for direct current (DC) blocking.

Next, the constant voltage circuit 300 determines the reference voltage Ref by the ratio of the resistors R15 and R16, and provides the amplitude limiting amplifier 400 stably through the buffer, where the capacitor C12 is the ripple of the power supply voltage ( RIPPLE) is a ripple filter that does not affect the constant voltage.

Here, the overall gain Av of the amplitude limiting amplifier 400 is as follows.

Av (total) dB = Av1 dB + Av2 dB = 20log (R12 / R11) + 20log (R14 / R13).

5 shows an output waveform of the amplitude limiting amplifier 400.

On the other hand, the effective signal recognition unit 500 recognizes whether the received signal is valid as a pulse signal output from the amplitude limiting amplifier 400. That is, since the valid signal recognition unit 500 receives the signal from the antenna 100, the effective signal recognition unit 500 generates a signal for detecting and demodulating the received signal.

6 is a circuit diagram illustrating an embodiment of the valid signal recognition unit 500.

First, FIG. 6A illustrates a peak-to-peak detection circuit, which performs low pass filtering on the input signal B with the capacitor C51 and the resistor R51, and compares the low pass filtered signal B 'with the reference signal V _B in the comparator 510. Output Thereafter, the signal detected through the Schmitt trigger 520 is output as a valid signal recognition signal C.

Next, FIG. 6B illustrates a monostable multi-vibrator 530. The input signal B is maintained by the time constant set by the resistor R _T and the capacitor C _T and output as the valid signal recognition signal C. FIG. .

7A to 7C show the operation waveforms of each part of the effective signal recognition unit using the peak value detection circuit as shown in FIG. 6A, and FIGS. 7D to 7F show the effective signal using the monostable multivibrator as shown in FIG. 6B. The operation waveforms of the parts of the recognition unit are shown.

Comparing the waveforms of both waveforms, since the t1 in the waveform of FIG. 7C is longer than the t2 in FIG. 7F, the effective signal recognizer using the monostable multivibrator is more effective in terms of circuit, that is, in terms of recognition range error and waveform ripple. It can be seen that it is advantageous.

On the other hand, the clock generator 800 generates a reference clock for reading data transmitted from the IC card and transmits it to the division unit 700, and simultaneously generates and amplifies and modulates a reference clock for transmitting data to the IC card. It passes to the unit (1000).

The division unit 700 divides the reference clock to be transmitted 16 and transmits the same to the data demodulation unit 600, and the data demodulation unit 600 is output from the amplitude limiting amplifier 400 in synchronization with the transferred clock. Demodulate the pulse signal into the original data.

8 is a circuit diagram illustrating an embodiment of the data demodulation unit 600, that is, an ISO / IEC 14443 TYPE B type data demodulation circuit.

Since the received signal of the TYPE B method is a BPSK modulated signal using 847 KHz divided into 16 at the transmission carrier frequency (13.56 MHz), the demodulated data is subjected to 180 degree phase difference during data demodulation.

In FIG. 8, CLK represents a 13.56 MHz clock pulse output from the clock generator 800, and signal D is a 16-divided pulse signal.

The demodulation exclusively ORs the pulse signal B and the 16-divided pulse signal D output from the amplitude limiting amplifier 400 to the exclusive logical sum element 610, and performs a low pass filtering on the resultant F signal with the low pass filter 620. To remove the noise component.

Thereafter, the data waveform is sharpened through the Schmitt trigger 630 to be input to the controller 900 to read the data.

9A to 9G illustrate waveforms of respective parts of the data demodulator of FIG. 8.

In FIG. 9, since the F signal has a glitch due to the delay in the circuit, the G signal is removed by using the low pass filter, and the signal H is a sharpened waveform using the Schmitt trigger.

In addition, the controller 900 reads the received data transmitted from the data demodulator 600.

Here, the transmission data (T _x -data) is transmitted to the IC card side before reading the data transmitted by the data demodulation unit 600. The transmission data transmitted here is also called a wake-up signal.

The amplification and modulation unit 1000 receives the wake-up signal, amplifies the power, modulates the BPSK, and transmits the BPSK to the IC card through the antenna 100.

10 is a circuit diagram illustrating an embodiment of the amplifier and modulator 1000.

As shown therein, the driving transistor Q91 operating based on the reference clock CLK obtained by the clock generator 800 and the capacitor C1 and the inductor resonating the driving signal output to the emitter terminal of the driving transistor Q91 A series resonator 1010 formed of (L1), a power amplifying transistor Q92 for power amplifying a carrier frequency through the series resonator 1010, and an antenna in parallel resonant with a carrier frequency of the power amplifying transistor Q92. A parallel resonator 1020 set to transmit power to the maximum, a transistor Q93 for amplitude modulating a transmission signal, and an impedance matching unit 1030 for impedance matching between the antenna 100 and the power amplifier circuit It is composed of

The amplifying and modulating unit 1000 configured as described above operates in accordance with the reference clock obtained by the clock generator 800 in the driving transistor Q91 to generate a driving signal. The series resonator 1010 resonates the driving signal to allow a maximum driving current to flow through the power amplifying transistor Q92 at the carrier frequency, and the power amplifying transistor Q92 power amplifies the generated carrier frequency. Next, the parallel resonator 1020 resonates in parallel with the carrier frequency to provide maximum power to the antenna 100, and the transistor Q93 modulates a transmission signal. Next, the impedance matching unit 1030 serves to match the impedance between the transmission signal and the antenna 100 to be transmitted.

According to the present invention as described above, it is possible to provide a contactless card reader apparatus that satisfies the standard of ISO / IEC 14443, yet has a high data transmission speed and high reliability access control.

Claims (7)

A preamplifier for preamplifying and outputting data transmitted from the IC card through the antenna; A constant voltage circuit providing a reference signal for converting the received signal into a pulse form; An amplitude limiting amplifier configured to filter the signal output from the preamplifier, and convert the received signal into a pulse form by comparing the filtered signal with a reference signal provided from the constant voltage circuit; An effective signal recognizing unit detecting a valid signal from the pulse signal output from the amplitude limiting amplifier; A data demodulator for demodulating data from the pulse signal output from the amplitude limited amplifier; A clock generator which generates a reference clock required when receiving data transmitted from the IC card or transmitting data to the IC card side; A control unit for determining whether a received signal is normal according to the signal output from the valid signal recognition unit, processing received data demodulated by the data demodulator if the received signal is valid, and outputting transmission data to be transmitted to the IC card; Wow; And amplifying and modulating unit for power amplifying, amplitude modulating, and transmitting the transmitted signal output from the control unit to the antenna side. The method of claim 1, wherein the preamplifier is Low pass filters C1 and R1 for low pass filtering the signal received by the antenna 100, a buffer amplifier Q1 for buffering signals through the low pass filters C1 and R1, and amplification in the buffer amplifier Q1. High frequency bypass filters RB1 to RB4 and CB1 to CB4 for filtering the high frequency components of the received signal, and low pass filters R3 to R6, C2 to C4 and Q2 for low-pass filtering the output signal of the buffer amplifier Q1. And a two-stage high pass amplifier (C5, R7, Q3, C6, R9, R10, Q4) which sequentially amplifies the signal through the low pass filter. The method of claim 1, wherein the amplitude limiting amplifier, A coupling capacitor C11 that removes the direct current component of the input signal A and passes only the alternating current component, and a first inversion that amplifies the difference voltage between the signal through the coupling capacitor C11 and the reference voltage Vref. And a second inverting amplifier 420 for inverting and amplifying the difference between the output signal of the first inverting amplifier 410 and the reference voltage Vref. . The method of claim 1, wherein the valid signal recognition unit, A capacitor C51 and a resistor R51 for low-pass filtering the input signal B, a comparator 510 for comparing the low-pass filtered signal B 'with a reference signal V _B and outputting a result thereof, and an output signal waveform of the comparator 510. Non-contact card reader device characterized in that consisting of Schmitt trigger (520) to make sharp and output as a valid signal recognition signal C. The method of claim 1, wherein the valid signal recognition unit, A non-contact card reader device comprising a monostable multi-vibrator 530 which maintains an input signal B by a time constant set by a resistor R _T and a capacitor C _T and outputs it as a valid signal recognition signal C. . The method of claim 1, wherein the data demodulation unit, Low-pass filtering the exclusive logic sum element 610 for exclusive OR of the pulse signal B output from the amplitude limiting amplifier and the pulse signal D divided in 16 from the divider, and the F signal that is an output signal of the exclusive logic sum element 610. And a low pass filter (620) for removing noise components, and a Schmitt trigger (630) for sharpening a signal through the low pass filter (620). The method of claim 1, wherein the amplifying and modulating unit, A driving transistor Q91 operating based on the reference clock CLK obtained by the clock generator 800, and a capacitor C1 and an inductor L1 for resonating the driving signal output to the emitter terminal of the driving transistor Q91. A power amplification transistor Q92 for power amplifying a series resonator 1010, a carrier frequency through the series resonator 1010, and a carrier frequency of the power amplifying transistor Q92 in parallel resonant power to the antenna 100. Is configured as a parallel resonator 1020 configured to transmit the maximum, a transistor Q93 for amplitude modulating a transmission signal, and an impedance matching unit 1030 for impedance matching between the antenna 100 and the power amplifier circuit. Contactless card reader device.