KR19990066130A - Nonvolatile Memory Device And Its Program Method - Google Patents

Abstract

A nonvolatile memory device according to the present invention comprises: at least one memory cell electrically erasable and programmable and having a floating gate and a control gate; The memory cell has a threshold voltage distribution of one of a plurality of uniform threshold voltage distributions representing a plurality of possible data states, and during a program operation, provides a sequentially varying program voltage to a control gate of the memory cell. Means for programming to have a threshold voltage distribution of one of the possible data states, wherein the difference between adjacent distributions of the threshold voltage distributions corresponding to each of the possible data states is uneven.

Description

NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF

TECHNICAL FIELD The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile memory device and a program method thereof for storing multi-bit data in electrically erasable and programmable cells.

1 is a diagram showing a threshold voltage distribution corresponding to possible states of 2-bit data according to the prior art. 2 is a waveform diagram illustrating a change in a program voltage and a program reference voltage according to a conventional program method.

As an example, assume that an electrically erasable and programmable ROM (hereinafter referred to as EEPROM) cell has four possible states. In this case, the possible states are "0", "1", "10" and "11". As shown in Fig. 1, state "0" represents an erased state, and states "1"-"11" represent programmed states. Here, the threshold voltage distribution of the programmed states is approximately 0.4V, and the distribution may be formed differently according to process changes and various variables.

The EEPROM cell is programmed to the required state through a series of program and program verification operations based on the program reference voltages Vref1, Vref2 and Vref3 corresponding to each of the above states. . The program reference voltages Vref1, Vref2, and Vref3 corresponding to each state are 0.4V, 1.6V, and 2.8V, respectively, as shown in FIGS. 1 and 2. The interval of the program reference voltages is uniformly distributed at 1.2V.

By sequentially supplying selection voltages (Vg1, Vg2 and Vg3 of FIG. 1) corresponding to each data state to the control gate of the EEPROM cell, through the above-described process, the data state of the programmed EEPROM cell is sense amplifier (sense). amplifier (see FIG. 3) (e.g., page buffer).

The interval between the low threshold voltage distribution and the high threshold voltage distribution on the basis of any selected voltage is set for the following reason. The data state stored in the EEPROM cell is sensed by the sense amplifier. At this time, based on whether the amount of current flowing through the EEPROM cell, which is induced by the difference between the selection voltage and the threshold voltage of the EEPROM cell, can be sufficiently sensed, the interval between the selection voltage and the lower threshold voltage compared thereto ( Or margin). This is indicated by symbol (a) in FIG.

In contrast, in a data state having a higher threshold voltage distribution than the selected voltage, the interval (or margin) between the selected voltage and the higher threshold voltage is determined in consideration of leakage current, process change, power supply change, and the like. . This is indicated by symbol (b) in FIG. As shown in Figures 1 and 2, the margins (a) and (b) between the low and high states with respect to any selected voltage and the spacing between the program verify voltages are distributed at equal intervals.

Increasingly, semiconductor memory devices are on the trend of high integration and high speed with the development of technology. In accordance with such a trend, in order to realize a semiconductor memory device having a higher degree of integration, as described above, multiple technologies capable of storing at least two bits of data in one memory cell have been researched and developed. Since multi-technology stores multi-bit data in one memory cell, reliability is inferior to a single bit. As a result, reliability problems are gradually raised as an important task for the practical use of nonvolatile memory devices for storing multi-bit data.

Accordingly, an object of the present invention is to provide a program method capable of improving the reliability of a nonvolatile memory device storing multi-bit data.

Another object of the present invention is to provide a nonvolatile memory device which stores multi-bit data with improved reliability.

1 shows a threshold voltage distribution corresponding to possible states of 2-bit data according to the prior art;

2 is a waveform diagram showing a change in a program voltage and a program reference voltage according to a conventional program method;

3 is a block diagram showing a schematic configuration of a nonvolatile memory device;

4 is a cross-sectional view structurally showing a program operation using F-N tunneling;

5 shows the change in the threshold voltage due to reverse F-N tunneling;

6 shows a threshold voltage distribution corresponding to possible states of 2-bit data according to the present invention; And

7 is a waveform diagram illustrating a change in a program voltage and a program reference voltage according to the program method of the present invention.

* Explanation of symbols on the main parts of the drawings

100: memory cell array 120: word line voltage generation circuit

140: row decoder 160: sense amplifier

(Configuration)

According to one aspect of the present invention for achieving the object as described above, it comprises at least one memory cell electrically erasable and programmable and having a floating gate and a control gate, the memory cell comprising a plurality of possible data states A program method of a nonvolatile memory device having a threshold voltage distribution of one of a plurality of uniform threshold voltage distributions, the method comprising: programming to have a threshold voltage distribution of a data state of one of the possible data states; The difference between adjacent distributions of the threshold voltage distributions corresponding to each of the possible data states is characterized by unevenness.

In this embodiment, the difference between the threshold voltage distributions corresponding to each of the possible data states is larger as the threshold voltage is larger.

In this embodiment, the voltage difference between the threshold voltages corresponding to each of the data states and the corresponding control gate voltages is equal based on the voltage applied to the control gate of the memory cell.

In this embodiment, the voltage difference between gate voltages applied to the control gate corresponding to each of the data states and higher threshold voltages than the gate voltages in the read operation is uneven, but the higher the threshold voltage is. It is characterized by a larger one.

In this embodiment, the difference between the control gate voltages is characterized by unevenness.

In this embodiment, the memory cell is programmed by F-N tunneling in the program step.

According to another aspect of the invention, a nonvolatile memory device comprising: at least one memory cell electrically erasable and programmable and having a floating gate and a control gate; The memory cell has a threshold voltage distribution of one of a plurality of uniform threshold voltage distributions representing a plurality of possible data states, and during a program operation, provides a sequentially varying program voltage to a control gate of the memory cell. Means for programming to have a threshold voltage distribution of one of the possible data states, wherein the difference between adjacent distributions of the threshold voltage distributions corresponding to each of the possible data states is uneven; .

In this embodiment, the memory cell is programmed by F-N tunneling.

In this embodiment, the difference between the threshold voltage distributions corresponding to each of the possible data states is larger as the threshold voltage is larger.

In this embodiment, the voltage difference between the threshold voltages corresponding to each of the data states and the corresponding control gate voltages is equal based on the voltage applied to the control gate of the memory cell.

In this embodiment, the voltage difference between gate voltages applied to the control gate corresponding to each of the data states and higher threshold voltages than the gate voltages in the read operation is uneven, but the higher the threshold voltage is. The voltage difference is characterized in that it is larger.

(Action)

In this manner, reliability can be improved by setting a threshold threshold voltage value in a memory device using F-N tunneling and setting the threshold voltages corresponding to possible data states under a lower voltage.

(Example)

Reference will now be made in detail with reference to FIGS. 3 to 7 according to an embodiment of the present invention.

In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those of ordinary skill in the art, the present invention may be practiced only by the above description without these details.

3 is a block diagram schematically illustrating a configuration of a nonvolatile memory device.

As shown in FIG. 3, a nonvolatile memory device according to an exemplary embodiment of the present invention may include a memory cell array 100, a wordline voltage generating circuit 120, A row decoder 140 and a sense amplifier 160. The memory cell array 100 is comprised of a plurality of electrically erasable and programmable ROM cells arranged in rows and columns, although not shown in the figure. The word line voltage generation circuit 120 generates different word line voltages related to each operation mode.

For example, in the program mode, as shown in FIG. 2, the program voltage Vpgm and the program reference voltages Vref1-Vref3 that are sequentially changed are generated. The sense amplifier 160 senses and amplifies the data state stored in the selected cell in the read / verify mode and delivers a voltage corresponding to the data state required on the column associated with the selected cell in the program mode.

Since the memory cell array 100, the word line voltage generator circuit 120, the row decoder 140 and the sense amplifier 160 are well known to those skilled in the art, detailed circuits on them are not shown. Did.

4 is a cross-sectional view structurally illustrating a program operation for an EEPROM cell using F-N tunneling. 5 is a diagram showing the results of simulation of the change in the threshold voltage according to reverse F-N tunneling.

Electrically erasable and programmable ROM (EEPROM) cells are programmed using hot electron injection and cold electron tunneling. The former uses avalanche and the latter uses tunneling, ie, Fowler-Norheim (F-N) tunneling, which is apparent to those who have gained common knowledge in this field. Common to these program methods is that they inject negative electrons into the floating gate 10 of the EEPROM cell. Then, the threshold voltage of the EEPROM cell is determined according to the amount of electrons injected. As shown in FIG. 4, the EEPROM cell has a floating gate 10 in which negative electrons are accumulated, and a control gate 12 to which a program voltage Vpgm is applied.

A method of storing single-bit or multi-bit data in an EEPROM cell using F-N tunneling is outlined below.

Program voltage Vpgm (eg, 18V) is applied to the control gate 12. The floating gate voltage of a predetermined level is induced in the floating gate 10 by the program voltage Vpgm. At this time, a current flows in the channel according to the electric field induced by the voltage difference between the induced floating gate voltage and the bulk 14 biased to 0V. This is called an F-N current, and is represented by Equation 1 below.

[Equation 1]

In Equation 1, symbol (A) represents the FN diode area, and symbol (Tox) represents the thickness of the tunnel oxide film or the gate oxide film 16. Here, the tunnel oxide film 16 is formed between the floating gate 10 and the bulk 14 in FIG. 4. The voltage V _FG is the voltage induced in the floating gate 10, and the symbols J _F and E _F are FN diode parameter constants. Charge is injected into the floating gate 10 according to the amount of current indicated in Equation 1, and the potential of the floating gate 10 is changed according to the injected charge amount. That is, the initial threshold voltage of the cell (the threshold voltage corresponding to the erased state) changes.

For example, the program voltage Vpgm applied to the control gate 12 of the cell is 18V, and the capacitance C1 between the control gate 12 and the floating gate 10 and between the floating gate 10 and the bulk 14. Assume that the capacitance of C2 is the same. Therefore, the voltage V _FG induced in the floating gate 10 becomes 1 / 2Vpgm [{C1 / (C1 + C2)} × Vpgm (18V)]. And the area (A) is 0.5 μm × 0.5 μm, the thickness T _OX is 100 μs, and the FN parameters J _F and E _F are 1.1 × 10 ⁻¹⁶ [A / V ² ] and 2.4, respectively. When x10 ⁸ [V / Cm], the FN current I _FN is 1.06x10 < -12 > [A]. Charge is injected into the floating gate 10 by the FN current I _FN during an arbitrary program time, and the dress voltage of the cell increases according to the injected charge amount.

As the amount of charge injected into the cell's floating gate 10 increases, the threshold voltage of the cell also increases while the potential of the floating gate 10 is lowered. As a result, the electric field between the channel and the floating gate 10 is increased in the direction opposite to the direction of the electric field induced during the programming process. In this case, when the electric field is expressed by a formula according to time, it may be expressed as Equation 2 below.

[Equation 2]

here, V _T (t) = V _{T - init} -▵V _T (t) , Symbol C _FG is a floating gate coupling ratio, and symbol C _OG is a control gate coupling ratio. In addition, the voltage V _{T_init} means a programmed cell threshold voltage. If the electric field E (t) generated in reverse by the threshold voltage V _{T_init} of the programmed cell is sufficiently large, the reverse FN current I _R (t) from the floating gate 10 to the channel also increases. The reverse FN current I _R (t) flowing over time may be expressed as in Equation 3.

[Equation 3]

The amount of charge that the charges stored in the floating gate 10 of the cell are released by the inverse FN current I _R (t) may be expressed as Equation 4, so that the threshold voltage is initially programmed when the threshold voltage is initially programmed. It is lower than the threshold voltage (V _{T_init} ). This may be expressed as an equation (5).

[Equation 4]

[Equation 5]

Here, the voltage V _{T (tDR)} represents the time for which the programmed data lasts as the data holding time (tDR = 10 _years) of a commercially available flash EEPROM cell. Typically, such time (tDR) is specified in the product specification.

A diagram of the results of simulating the above described process is shown in FIG. 5. As can be seen in FIG. 5, after the data retention period of the commercialized EEPROM cell has elapsed, the threshold voltage corresponding to the state "11" is lowered by approximately 0.6V. When a selection voltage (ie, control gate voltage) is applied, the EEPROM cell is sensed as an on cell from an initial off cell. As a result, the reliability of the nonvolatile memory device storing the multi-bit data can be lowered. In contrast, as can be seen in FIG. 5, the threshold voltages of the remaining states "10" and "1" hardly change during the data retention time tDR.

Therefore, when designing the product, in advance, the reliability problem described above is preempted by distributing the dress voltages corresponding to each state below the voltage at which reverse FN tunneling occurs in consideration of the change in the dress voltage due to reverse FN tunneling. To prevent it. Such voltage is hereinafter referred to as the limit threshold voltage Vmax.

6 is a diagram showing a threshold voltage distribution corresponding to possible states of 2-bit data according to the present invention. 7 is a waveform diagram illustrating a change in a program voltage and a program reference voltage according to the program method of the present invention.

Possible states of 2-bit data according to the present invention are distributed below the threshold threshold voltage (Vmax). The threshold voltage distribution corresponding to each state is 0.4V. The likelihood of the reverse F-N tunneling phenomenon described above is greater as the threshold voltages corresponding to each state are higher. On the basis of this, the cell distribution according to the present invention is different from the conventional one. For example, in FIG. 1, the margins (a) and (b) between the low and high threshold voltages based on the selection voltage are equal to 0.4V.

On the contrary, the cell distribution according to the present invention is distributed below the limit threshold voltage Vmax in consideration of the reverse FN tunneling phenomenon, and the low threshold voltage based on the respective selection voltages Vg1, Vg2, and Vg3. The difference between (a) and the high threshold voltages (b), (b ') and (b ") is uneven.

For example, the selection voltage Vg2 is based on whether the amount of current flowing through the EEPROM cell is sufficiently sensed, induced by the difference between the selection voltage Vg2 and the threshold voltage 0.6V of the EEPROM cell. In comparison, the spacing (or margin) between the low threshold voltage (0.6V) is 0.4V. In contrast, the spacing (or margin) between the selection voltage Vg2 and the high threshold voltage 1.3V (ie, the program reference voltage Vref2) is 0.3V.

In addition, the high threshold voltages (ie, the program reference voltages Vref1, Vref2 and Vref3) and the respective selection voltages Vg1 and Vg2 based on the respective selection voltages Vg1, Vg2, and Vg3. ), And the difference between (Vg3) is larger the higher the threshold voltage. In other words, the higher the threshold voltage, the higher the probability of reverse F-N tunneling. The lower the threshold voltage, the lower the probability of reverse F-N tunneling.

As a result, it is possible to prevent the degradation of reliability in advance by distributing the threshold voltages corresponding to each data state below the threshold threshold voltage Vmax. In addition, since the probability of reverse FN tunneling is higher at higher threshold voltages, the margins (b, b ', b ") are allocated more at higher threshold voltages, and smaller at lower threshold voltages. Therefore, in the program operation using FN tunneling, the electric charges stored in the floating gate 10 are lost due to the reverse FN current I _R (t) and various leakage sources. Probability can be prevented in advance.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, bit fail due to reverse FN current induced in a cell by setting a threshold threshold voltage and programming an electrically erasable and programmable ROM (EEPROM) cell using FN tunneling at a lower voltage than the voltage. Can be prevented. As a result, a nonvolatile memory device having improved reliability can be implemented.

Claims (11)

At least one memory cell electrically erasable and programmable and having a floating gate and a control gate, wherein the memory cell is one of a plurality of equivalent threshold voltage distributions representing a plurality of possible data states. In the method of programming a nonvolatile memory device having: Program to have a threshold voltage distribution of one of the possible data states, wherein the difference between adjacent distributions of the threshold voltage distributions corresponding to each of the possible data states is uneven. The method of claim 1, And the difference between the threshold voltage distributions corresponding to each of the possible data states is larger as the threshold voltage is larger. The method of claim 2, The voltage difference between the threshold voltages corresponding to each of the data states and the control gate voltages corresponding to the voltages applied to the control gates of the memory cells is equal. The method of claim 2, In a read operation, a voltage difference between gate voltages applied to the control gate corresponding to each of the data states and higher threshold voltages than the gate voltages is uneven, but the higher the threshold voltage is, the larger the difference is. Program method. The method of claim 4, wherein And the difference between the control gate voltages is uneven. The method of claim 1, And wherein said memory cell is programmed by F-N tunneling in said programming step. In a nonvolatile memory device: At least one memory cell that is electrically erasable and programmable and has a floating gate and a control gate; The memory cell has one threshold voltage distribution of one of a plurality of uniform threshold voltage distributions representing a plurality of possible data states; Means for providing a sequentially varying program voltage to a control gate of said memory cell during a program operation and having a threshold voltage distribution of one of said possible data states; And an uneven difference between adjacent distributions of the threshold voltage distributions corresponding to each of the possible data states. The method of claim 7, wherein And said memory cell is programmed by F-N tunneling. The method of claim 7, wherein And the difference between the threshold voltage distributions corresponding to each of the possible data states is larger as the threshold voltage is larger. The method of claim 7, wherein And a voltage difference between the threshold voltages corresponding to each of the data states and the control gate voltages is equal based on a voltage applied to the control gate of the memory cell. The method of claim 7, wherein In the read operation, a voltage difference between gate voltages applied to the control gate corresponding to each of the data states and high threshold voltages is higher than the gate voltages, but the higher the threshold voltage is, the larger the voltage difference is. Nonvolatile memory device characterized in that.