KR19990026244A - Dualization of Contact Hole Formation - Google Patents

Abstract

The present invention relates to a semiconductor manufacturing method for forming contact holes. More specifically, when the thicknesses of the interlayer insulating layer and the nitride layer in the source / drain contact hole region and the gate contact hole region are different, the source / drain contact having a relatively thin thickness of the nitride layer, even if the etching selectivity is optimized. In order to solve the problems of the prior art that the source / drain under the hole area has to be etched, the etching for the source / drain contact hole area and the etching for the gate contact hole area are performed separately by dualization. Thus, it is possible to prevent etching to the source / drain under the source / drain contact hole region. In addition, the source / drain may be damaged to prevent the leakage current caused by the PN junction.

Description

Dualization of Forming Contact Hall

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact hole in a method of manufacturing a semiconductor device.

1A to 1B are cross-sectional views of a semiconductor device by a contact hole forming method according to the prior art.

Referring to FIG. 1A, a cell array region 10 for memory cell elements and a peripheral circuit region 20 for other circuit elements are defined on a P-type semiconductor substrate, whereby a plurality of gate electrodes 15, 15 '). Next, a silicon nitride layer 30 is formed on the semiconductor substrate, the silicon nitride layer 30 on the sidewalls of each gate electrode 15 and 15 'is etched to form a gate spacer, and then all remaining silicon nitride layers are formed. Etch it.

In addition, an n-type source / drain 16 is formed between the gate electrodes 15 of the cell array region 10, and N is formed under the semiconductor substrate on the side of the gate electrode 15 ′ of the peripheral circuit region 20. Conductive impurity, which is one of and P type, is implanted to form the peripheral circuit source / drain 25.

Next, the silicon nitride layer 30 is thinly formed once more on the semiconductor substrate including the gate spacers. In this case, the thickness of the silicon nitride layer 30 on the gate spacer is larger than the thickness of the silicon nitride layer 30 formed in the semiconductor substrate active region.

Next, a first interlayer insulating layer 40 is formed on the silicon nitride layer 30. Subsequently, the first interlayer insulating layer inside the cell array source / drain contact hole region is formed using a photoresist pattern defining a cell array source / drain contact hole region between adjacent gate spacers in the cell array region 10 as a mask. 40 and the nitride layer 30 are removed.

The poly layer 50 is formed by filling conductive poly in the cell array source / drain contact region.

Next, a second interlayer insulating layer 60 is formed on the first interlayer insulating layer 40 and the poly layer 50.

Next, the cell array contact hole 70 region connected to the poly layer 50 and the source / drain contact hole 80 region connected to the peripheral circuit source / drain 25 and the peripheral circuit gate electrode 15 ′. First and second in the cell array contact hole 70 and the source / drain contact hole 80 and the gate contact hole 90 regions, using the photoresist pattern defining the region of the gate contact hole 90 to be connected as a mask. The interlayer insulating layers 40 and 60 and the silicon nitride layer 30 are etched away. In this case, an etching selectivity with respect to the first and second interlayer insulating layers 40 and 60 and the nitride layer 30 is high, and an etching selectivity with respect to the poly layer 50 uses a low etching material.

However, according to the above-described prior art, the thickness of the peripheral circuit source / drain contact hole 80 region and the gate contact hole 90 region are different, and in addition, the thickness of the silicon nitride layer 30 in the gate contact hole 90 region. Is much thicker than the thickness of the silicon nitride layer 30 in the source / drain contact hole 80 region. Accordingly, the thick silicon nitride in the region of the gate contact hole 90 under the condition that the etch selectivity in which the first and second interlayer insulating layers 40 and 60 should be etched relatively better than the silicon nitride layer 30 is required. In order to etch all of the layer 30, a portion of the source / drain 85 in the lower portion of the source / drain contact hole 80 including the thin silicon nitride layer 30 must be etched. Occurs. At this time, if the damage of the source / drain 25 becomes fatal, the leakage current caused by the PN junction increases, which causes the semiconductor device manufacturing process to fail.

Therefore, when the source / drain contact hole and the gate contact hole of the peripheral circuit region are formed, the thicknesses of the two contact hole regions and the thicknesses of the interlayer insulating layer and the silicon nitride layer therein are different from each other. The purpose is to prevent the source / drain under the thin source / drain contact hole region from being damaged, thereby preventing the leakage current caused by the PN junction.

1A to 1B are cross-sectional views of a contact hole forming method according to the prior art.

2A to 2B are cross-sectional views of a contact hole forming method according to a first embodiment of the present invention.

3 is a cross-sectional view of a contact hole forming method according to a second exemplary embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

115, 115 ': gate electrode 125: source / drain

130 silicon nitride layer 140 first interlayer insulating layer

150: poly layer 160: second interlayer insulating layer

170: cell array contact hole 180: source / drain contact hole

190: gate contact hole

(First embodiment)

Hereinafter, a first preferred embodiment of the present invention for achieving the above object will be described with reference to FIGS. 2A to 2B.

Referring to FIG. 2A, a region of a cell array 110 for memory cell elements and a region of a peripheral circuit 120 for other circuit elements is defined on a P-type semiconductor substrate, whereby a plurality of gate electrodes 115, 115 '). Next, a silicon nitride layer 130 is formed on the semiconductor substrate. The silicon nitride layer 130 on the sidewalls of the gate electrodes 115 and 115 'is etched to form gate spacers, and the remaining silicon nitride layers are etched away.

In addition, an n-type source / drain 116 is formed between the gate electrodes 115 in the cell array 120 region, and is formed under the semiconductor substrate on the side of each gate electrode 115 ′ in the peripheral circuit 120 region. A conductive impurity, one of N and P types, is implanted to form the peripheral circuit source / drain 125.

Next, the silicon nitride layer 130 is thinly formed once more on the semiconductor substrate including the gate spacers. At this time, the thickness of the silicon nitride layer 130 on the gate spacer is larger than the thickness of the silicon nitride layer 130 formed in the semiconductor substrate active region.

Next, a first interlayer insulating layer 140 is formed on the silicon nitride layer 130. Subsequently, the first interlayer insulating layer inside the cell array source / drain contact hole region is formed using a photoresist pattern defining a cell array source / drain contact hole region between adjacent gate spacers in the cell array region 110 as a mask. 140 and the silicon nitride layer 130 are removed. The poly layer 150 is formed by filling conductive poly in the cell array source / drain contact region.

Next, a second interlayer insulating layer 160 is formed on the first interlayer insulating layer 140 and the poly layer 150.

Next, referring again to FIG. 2A, the cell array contact hole 170 and the peripheral circuit are formed using a photoresist pattern defining a cell array contact hole 170 region and a source / drain contact hole 180 region of the peripheral circuit as a mask. The first and second interlayer insulating layers 140 and 160 and the silicon nitride layer 130 in the source / drain contact hole 180 regions of the silicon nitride layer 130 are etched. In this case, an etching selectivity with respect to the first and second interlayer insulating layers 140 and 160 and the silicon nitride layer 130 is high, and an etching selectivity with respect to the poly layer 150 is low.

Next, referring to FIG. 2B, the photoresist pattern defining the gate contact hole 190 region of the peripheral circuit 120 is used as a mask and the first and second interlayer insulating layers 140 in the gate contact hole 190 region are formed as a mask. 160 and silicon nitride layer 130 are etched. In this case, the etching selectivity of the first and second interlayer insulating layers 140 and 160 and the silicon nitride layer 130 is high, and the etching selectivity of the gate electrode 115 'is low. ') The thick silicon nitride layer 130 on the upper side is etched to remove all.

As a result, the cell array contact hole 170 is formed adjacent to the poly layer 150, and the source / drain contact hole 180 and the gate contact hole 190 of the peripheral circuit are respectively the source / drain of the peripheral circuit 120. The source / drain 125 under the source / drain contact hole 180 is not damaged while being connected to the drain 125 and the gate electrode 115 '.

(Second embodiment)

The poly layer 150 is formed by filling the conductive poly in the cell array source / drain contact hole region through the same semiconductor manufacturing steps as the first embodiment described above. Next, a second interlayer insulating layer 160 is formed on the first interlayer insulating layer 140 and the poly layer 150, and as shown in FIG. 3, the cell array contact hole 170 and the peripheral circuit 120 are formed. Using the photoresist pattern defining the gate contact hole 190 region as a mask, the first and second interlayer insulating layers 140 and 160 in the cell array contact hole 170 region and the gate contact hole 190 region of the peripheral circuit are used as masks. ) And the silicon nitride layer 130 are etched. In this case, an etching selectivity with respect to the first and second interlayer insulating layers 140 and 160 and the silicon nitride layer 130 is high, and an etching selectivity with respect to the poly layer 150 uses a low etching material.

Next, referring again to FIG. 2B, the first and second interlayer insulating layers in the source / drain contact hole 180 region (the photoresist pattern defining the source / drain contact hole 180 region of the peripheral circuit as a mask) may be used as a mask. 140 and 160 and silicon nitride layer 130 are etched. In this case, the thick silicon nitride layer 130 on the gate electrode 115 'may be formed by using an etching material having a high etching selectivity with respect to the first and second interlayer insulating layers 140 and 160 and the silicon nitride layer 130. Remove everything.

As a result, the cell array contact hole 170 is formed adjacent to the poly layer 150, and the gate contact hole 190 and the source / drain contact hole 180 of the peripheral circuit are respectively formed as gates of the peripheral circuit 120 ( 115 ') and the source / drain 125 formed under the source / drain contact hole 180 are not damaged.

According to the present invention, the source / drain contact holes and the gate contact holes of the peripheral circuit region are formed separately, so that the thicknesses of the contact hole regions different from each other and the thickness of the interlayer insulating layer and the silicon nitride layer inside each contact hole are different. In the etching process using the etching selectivity, the source / drain under the relatively thin source / drain contact hole region of the silicon nitride layer may be prevented from being damaged to prevent the occurrence of leakage current due to the PN junction.

Claims (17)

In the semiconductor manufacturing method, On a semiconductor substrate comprising an active region and an inactive region, the gate electrode and the silicon nitride layer gate spacer formed in the cell array region and the peripheral circuit region, Implanting a first conductivity type impurity between adjacent gate electrodes in the cell array region to form a cell array source / drain; Implanting a second conductivity type impurity into the gate electrode side in the peripheral circuit region to form a peripheral circuit source / drain; Forming a thin silicon nitride layer over the semiconductor substrate including the gate spacers; Forming a first interlayer dielectric layer over said silicon nitride layer; A first interlayer insulating layer and a silicon nitride layer in the cell array source / drain contact hole region as a mask, using a first photoresist pattern defining a cell array source / drain contact hole region between adjacent gate spacers in the cell array region. Removing the; Filling the cell array source / drain contact hole region with a conductive poly to form a poly layer; Forming a second interlayer insulating layer over the first interlayer insulating layer and the poly layer; A cell array contact hole region and a source / drain contact hole are formed using a cell array contact hole region connected to the poly layer and a second photoresist pattern defining a source / drain contact hole region on a gate spacer side of a peripheral circuit region as a mask. Removing the first and second interlayer dielectric layers and silicon nitride layers in the region; Removing a first and a second interlayer insulating layer and a silicon nitride layer in the gate contact hole region by using as a mask a third photoresist pattern defining a gate contact hole region on top of the gate electrode in the peripheral circuit region. The manufacturing method of the semiconductor device characterized by the above-mentioned. The method of claim 1, The silicon nitride layer formed on the gate electrode is several times thicker than the silicon nitride layer formed on the active region. The method of claim 1, The silicon nitride layer is SiN. The method of claim 1, A cell array contact hole region and a source / drain contact hole are formed using a cell array contact hole region connected to the poly layer and a second photoresist pattern defining a source / drain contact hole region on a gate spacer side of a peripheral circuit region as a mask. Removing the first and second interlayer dielectric layers and silicon nitride layers in the region; Removing the first and second interlayer dielectric layers and silicon nitride layers in the gate contact hole region by using a third photoresist pattern defining a gate contact hole region as a mask on top of the gate electrode in the peripheral circuit region may be an etch selection. A semiconductor manufacturing method which is etched using a ratio. The method of claim 1, And filling the cell contact hole region with a conductive poly to form a poly layer, followed by polishing and planarizing the semiconductor device. The method of claim 1, A cell array contact hole region and a source / drain contact hole are formed using a cell array contact hole region connected to the poly layer and a second photoresist pattern defining a source / drain contact hole region on a gate spacer side of a peripheral circuit region as a mask. Removing the first and second interlayer dielectric layers and silicon nitride layers in the region; Using the third photoresist pattern defining the gate contact hole region as a mask on the gate electrode in the peripheral circuit region, removing the first and second interlayer insulating layers and the silicon nitride layer in the gate contact hole region may be performed. A semiconductor manufacturing method that can be preceded by either. In the semiconductor manufacturing method, On a semiconductor substrate comprising an active region and an inactive region, the gate electrode and the silicon nitride layer gate spacer formed in the cell array region and the peripheral circuit region, Implanting a first conductivity type impurity between adjacent gate electrodes in the cell array region to form a cell array source / drain; Implanting a second conductivity type impurity into the gate electrode side in the peripheral circuit region to form a peripheral circuit source / drain; Forming a thin silicon nitride layer over the semiconductor substrate including the gate spacers; Forming a first interlayer dielectric layer over said silicon nitride layer; A first interlayer insulating layer and a silicon nitride layer in the cell array source / drain contact hole region as a mask, using a first photoresist pattern defining a cell array source / drain contact hole region between adjacent gate spacers in the cell array region. Removing the; Filling the cell array source / drain contact hole region with a conductive poly to form a poly layer; Forming a second interlayer insulating layer over the first interlayer insulating layer and the poly layer; A first layer in the cell array contact hole region and the gate contact hole region, using a cell array contact hole region connected to the poly layer and a second photoresist pattern defining a gate contact hole region on the gate electrode of the peripheral circuit region as a mask. Removing the second interlayer dielectric layer and silicon nitride layer; The first and second interlayer insulating layers and silicon nitride layers in the source / drain contact hole regions are removed by using a third photoresist pattern defining a source / drain contact hole region as a mask on the side of the gate spacer in the peripheral circuit region. A method of manufacturing a semiconductor device, comprising the step. The method of claim 7, wherein The silicon nitride layer formed on the gate electrode is several times thicker than the silicon nitride layer formed on the active region. The method of claim 7, wherein The silicon nitride layer is SiN. The method of claim 7, wherein A first layer in the cell array contact hole region and the gate contact hole region, using a cell array contact hole region connected to the poly layer and a second photoresist pattern defining a gate contact hole region on the gate electrode of the peripheral circuit region as a mask. Removing the second interlayer dielectric layer and silicon nitride layer; The first and second interlayer insulating layers and silicon nitride layers in the source / drain contact hole regions are removed by using a third photoresist pattern defining a source / drain contact hole region as a mask on the side of the gate spacer in the peripheral circuit region. The step of etching the semiconductor using an etching selectivity. The method of claim 7, wherein And filling the cell contact hole region with a conductive poly to form a poly layer, followed by polishing and planarizing the semiconductor device. The method of claim 7, wherein A first layer in the cell array contact hole region and the gate contact hole region, using a cell array contact hole region connected to the poly layer and a second photoresist pattern defining a gate contact hole region on the gate electrode of the peripheral circuit region as a mask. Removing the second interlayer dielectric layer and silicon nitride layer; The first and second interlayer insulating layers and silicon nitride layers in the source / drain contact hole regions are removed by using a third photoresist pattern defining a source / drain contact hole region as a mask on the side of the gate spacer in the peripheral circuit region. And the step may be preceded by either. In the manufacturing method of a semiconductor device, Forming first and second conductive layers, respectively, on the semiconductor substrate; A silicon nitride layer is formed on the first conductive layer and the second conductive layer, and the silicon nitride layer on the first conductive layer is formed by a separate etching / deposition process for the silicon nitride layer on the first conductive layer and the second conductive layer. Varying the thickness of the layer and the thickness of the silicon nitride layer on the second conductive layer; Forming an interlayer insulating layer on the semiconductor substrate including the silicon nitride layer; Removing an interlayer insulating layer and a silicon nitride layer in the first contact hole region using a first photoresist pattern defining a first contact hole region connected with the first conductive layer as a mask; Removing the interlayer insulating layer and the silicon nitride layer in the second contact hole region using a second photoresist pattern defining a second contact hole region connected with the second conductive layer as a mask. The method of claim 13, The silicon nitride layer on the first conductive layer is SiN. The method of claim 13, The silicon nitride layer on the second conductive layer is SiN. The method of claim 13, Removing an interlayer insulating layer and a silicon nitride layer in the first contact hole region using a first photoresist pattern defining a first contact hole region connected with the first conductive layer as a mask; Removing the interlayer insulating layer and the silicon nitride layer in the second contact hole region by using a second photoresist pattern defining a second contact hole region connected to the second conductive layer as a mask may be performed by using an etching selectivity. Semiconductor manufacturing method. The method of claim 13, Removing the interlayer insulating layer and the silicon nitride layer in the second contact hole region using a second photoresist pattern defining a second contact hole region connected with the second conductive layer as a mask; Removing the interlayer insulating layer and silicon nitride layer in the first contact hole region by using a first photoresist pattern defining a first contact hole region connected with the first conductive layer as a mask may be preceded by either. Semiconductor manufacturing method.