KR19990017337A - Video frame memory device and video data processing method - Google Patents

Abstract

A video frame memory device and video data processing method are disclosed. The video frame memory device of the present invention is a video frame memory for storing digital video signals inputted from an image detector into radix / excellent field video data, storing the multiple video signals, and outputting the multiplexed output signals of the image detector output signals. A radix / excellent field memory for storing and outputting video data, a first buffer and a second buffer for outputting the image detector output signal or maintaining high impedance, and an output multiplexer for multiplexing and outputting the input video data. And a microprocessor data input / output port for inputting the video data output from the output multiplexer to the microprocessor and inputting the video data output from the microprocessor to the odd / excellent video field memory, and a microphone upon input. A third buffer and a fourth buffer for outputting video data from a low processor, a radix / excellent field address multiplexer for selecting and outputting one address, and a FIFO type buffer for outputting a digital video signal for continuous horizontal scanning. And a frame memory control logic for controlling the input / output and processing of the video data, and can correspond to various types of detector scanning methods and interpolated scanning and sequential scanning image output methods, and parallel image processing without additional frame memory. Can provide functionality.

Description

Video frame memory device and video data processing method

The present invention relates to a video frame memory device and a method of processing the video data, and more particularly, to a video frame memory device and a video data processing method for easy parallel image processing by a microprocessor.

In general, image detection is performed by scanning a linear or planar image detector. Examples of the image detector include a CCD (imaging device), a low light CCD and an infrared detector. When the image detectors are provided with a large number of detection elements on a plane, the image detectors may not have to acquire an image by scanning the image detector. However, in the case of a camera that acquires a high resolution image screen, a large number of detection elements are provided on the plane. Is difficult in the manufacturing process and difficult to ensure characteristic homogeneity in the detection elements. In order to overcome these disadvantages, the cameras requiring high resolution precision are arranged with a small number of uniform elements on a linear or two-dimensional plane of one-dimensional plane, and the detector is scanned to obtain an image of a desired resolution. And a method of scanning the image detector by a mechanical method, or a method in which the reflector has a scanning effect while receiving visible or infrared light input from an optical system through a reflector.

In order to explain a method of scanning a general linear and planar image detector, a conceptual diagram of a horizontal scanning method is illustrated in FIG. 1, and a conceptual diagram of a vertical scanning method is illustrated in FIG. 2. Referring to FIG. 1, a horizontal scan method in which a linear image detector including a plurality of image detection cells is vertically arranged and scanned in a horizontal direction with respect to a plane on which an image is to be detected, and FIG. 2, a plane to detect an image There is a vertical scanning method in which a linear image detector composed of a plurality of image detection cells is horizontally arranged and scanned in a vertical direction. In the horizontal scan mode, the scanning time can be regarded as a period of one video field or video frame in which one screen is completely composed. For example, 1024 linearly arranged image detectors can be 1280 × l024 while performing horizontal scanning. It is reported that a video signal of pixel resolution can be output, and a video signal of 1024 × 768 pixel resolution can be output if vertical scanning is performed. However, in the case of the horizontal scan, the actual video output is based on the horizontal scan, and also in the vertical scan, the output timing of the detector and the video output timing of the actual camera do not coincide. In addition, in order to perform image tracking, target recognition, or other various image processing operations by outputting the detector, a digital video signal must be stored in a frame memory, which requires a conversion function in the middle.

3 is a block diagram of a frame memory device having a scan conversion function for processing an image output of a conventional interlaced scan. Referring to FIG. 3, the conventional frame memory apparatus in the interlaced scanning method includes a frame memory control logic 300 for outputting an odd field or even field selection control signal, and an image detector scan address signal from an image detector (not shown). And the odd field address multiplexer 302 and the even field address multiplexer 304 which receive the digital video address signal and output an address signal by multiplexing in response to the odd field or even field selection control signal of the frame memory control logic 300. A radix field memory 306 and an even field memory 308 for storing and outputting an image detector output signal in response to the address signal, and a three-phase buffer for outputting an image detector output signal or maintaining high impedance in response to a control signal; The first buffer 310 and the second buffer 312, the odd field memory in response to the control signal or It is provided with a output multiplexer 314 which multiplexes the output data from the field memory output.

In the conventional frame memory device having a scan conversion function for processing the image output of the interlaced scan, the output field of the image detector is controlled by the control signal (not shown) of the frame memory control logic 300. Or the even field memory 308. In addition, the frame memory control logic 300 generates and stores an address in which the detector output according to the scanning method is to be stored, and stores the result in the radix field memory 306, and the first buffer is enabled and the radix field is stored. The address 2: 1 multiplexer 302 selects an image detector scan address and acts as an address input to the radix field memory 306. Thus, the even field is selected for the digital video output for display or other processing, the second buffer 312 is disabled, and the even field address 2: 1 multiplexer 304 selects the digital video address. The address of the memory is input, and the output multiplexer 314 outputs data of the even field memory 308. The opposite case also works in the same way. In this method, processing is performed with a delay of one field between the input signal and the output image signal of the current detector. If the non-interlaced video signal is output in a non-interlaced manner, the entire frame unit is processed. Two frame memory spaces are required to have low latency.

In the conventional frame memory device having a scan conversion function for processing the image output of the interlaced scan, it is difficult to add a self-diagnosis function for the verification of the rear end processing unit that processes the digital video output by the actual scan conversion. When parallel processing for image processing is required in addition to the configuration of the image processing unit in a single order, there is a disadvantage in that an additional frame memory is added. In addition to processing digital video and outputting images by analog-to-digital conversion, a microprocessor is generally used for histogram calculation, image tracking, and recognition of image data. A separate frame memory that can be used by the microprocessor is used. There is a drawback to the additional configuration.

The technical problem to be achieved by the present invention is that the microprocessor can be shared with its own image frame memory without having a separate image frame memory together with the regular digital video output for the image output, such as output in the field unit, the image output In order to add a separate function to the simple function of the camera to obtain a bay to provide a video frame memory device capable of parallel image processing.

Another technical problem to be solved by the present invention is a microprocessor that can be shared with its own image frame memory without having a separate image frame memory together with regular digital video output for image output and the like. The present invention provides a video data processing method of a video frame memory implemented in an image frame memory device capable of parallel image processing in order to add a separate function to a simple function.

1 is a conceptual diagram of a horizontal scanning method.

2 is a conceptual diagram of a vertical scanning method.

3 is a configuration diagram of a video frame memory device having a scan conversion function for processing an image output of a conventional interlaced scan.

4 is a configuration diagram of a video frame memory device according to an embodiment of the present invention.

FIG. 5 is a timing diagram illustrating pixel output and microprocessor input / output steps according to a horizontal blank signal.

6 is a block diagram illustrating an external input / output terminal of the image frame memory device of the present invention.

Explanation of symbols for the main parts of the drawings

400 ... frame memory control logic, 402,404,418 ... multiplexer,

406,408 ... Video field memory 410,412,414,416 ... 3-phase buffer,

420 ... FIFO type buffer.

In order to achieve the above object, the image frame memory device of the present invention is a video frame memory for storing the digital video signal input from the image detector divided into radix field video data and even field video data, and multiplexed according to the control signal and outputted. Storing the radix field video data and the even field video data of the image detector output signal at a place designated by the address input signal at the time of input, and storing the radix field video data and the even field stored from the place specified by the address input signal at the output. Odd field memory and even field memory for outputting field video data; When the output terminal is connected to the data input terminal of the odd / excellent field memory and the video data is input to the odd / excellent field memory, the image detector output signal is output to the data terminal, and the video from the odd / excellent field memory is output. A first buffer and a second buffer, which are three-phase buffers for maintaining high impedance when data is output; An output multiplexer for multiplexing and outputting video output data from the odd / excellent field memory or video data from the microprocessor; A microprocessor data input / output port for inputting the video data output from the output multiplexer to the microprocessor and inputting the video data output from the microprocessor to the odd / excellent video field memory; An input terminal is connected to the microprocessor data input / output port, and an output terminal is connected to the input terminals of the radix / excellent field memory and the output multiplexer to output video data from the microprocessor to the radix / excellent field memory upon input, and to output high impedance. A third buffer and a fourth buffer which are three phase buffers for holding the buffer; An image detector scan address signal, a microprocessor address bus signal, and a horizontal scan pixel address signal are connected to an input terminal, and an address input terminal of the odd / excellent field memory is connected to an output terminal to select one address by multiplexing the three address signals. Radix field address multiplexer and even field address multiplexer for outputting; An FIFO type buffer having an input connected to an output of the output multiplexer and outputting a digital video signal for continuous horizontal scanning; And a frame memory control logic provided in the video frame memory to control input / output and processing of the video data.

The frame memory control logic may include an odd field or even field selection control signal, an address signal supplied to the odd / excellent field memory, a device control signal of the multiplexers and the buffers, a memory read / write signal, a sequential address signal, Preferably, the frame memory control logic has logic implemented to perform the function of outputting the horizontal scanning pixel address signal and the busy signal.

According to another aspect of the present invention, a video data processing method includes storing digital video signals input from an image detector into radix field video data and even field video data or radix line video data and even line video data. In the video data processing method of a video frame memory which is output by multiplexing according to a control signal, the frame memory control logic outputs a pixel input control signal in response to a horizontal blank signal representing a horizontal retrace time of the output video signal and a scan conversion signal. Making; During the blank period, in response to the pixel input control signal, the FIFO type buffer, which is an output buffer, stores one line of video pixel output; Outputting a synchronized video pixel in response to the pixel clock which is the basic pixel clock of the output when the horizontal output is completed and the horizontal output is activated; Performing microprocessor input / output during the scan activation period; And repeating the above-described first-in-first-out (FIFO) type storage operation to support parallel image processing of video sequential output and microprocessor image processing.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a block diagram of a video frame memory device according to an embodiment of the present invention. Referring to FIG. 4, the frame memory of the present invention includes a frame memory control logic 400 for controlling video input / output and processing of a video frame memory, an image detector scan address signal from a image detector (not shown), and a microprocessor. Radix field address multiplexer 402, which is a 3: 1 multiplexer which receives an address bus signal and a horizontal scan pixel address signal, and outputs an address signal by multiplexing the radix field video address signal and the even field video address signal of the image detector output signal, respectively. Even field field multiplexer 404 and odd field memory 406 and even field memory for storing / outputting odd field video data and even field video data of the image detector output signal to / from a place designated by the address signal, respectively. 408 and an output terminal to the data terminals of the field memories 406 and 408. First and second buffers 410 and 412, which are three-phase buffers for outputting image detector output signals or maintaining high impedance, and input terminals are connected to data terminals of the field memories 406 and 408 so that the odd field memory 406 or an output multiplexer 418 for multiplexing and outputting output data from the even field memory 408, and an output terminal of which is connected to an output terminal of the microprocessor data bus and the output multiplexer 418 to output a microprocessor video data signal or output. A third buffer 414 and a fourth buffer 416, which are three-phase buffers for outputting the video data signal of the multiplexer 418 or maintaining high impedance, and an input terminal are connected to the output terminal of the output multiplexer 418 for continuous horizontal And a FIFO type buffer 420 for outputting a digital video signal for scanning, and the video data output from the output multiplexer 418. And a microprocessor data input / output port for inputting a chromoprocessor and outputting video data from a microprocessor to the radix / excellent video field memories 406 and 408. The frame memory control logic 400 has a radix field or even Field selection control signals, address signals supplied to each field memory, device control signals of the multiplexers 402, 404, 418 and buffers 410, 412, 414, 416, 418, memory read / write signals, sequential address signals, and busy signals It is provided by implementing logic to perform the function of outputting.

The operation of the video frame memory of the present invention provided as described above will be described below. The radix field address multiplexer 402 and even field address multiplexer 404, which are 3: 1 multiplexers, include an image detector scan address signal and a microprocessor address bus signal that is an address of the field memories 406 and 408 which direct access from the microprocessor. The frame memory control logic 400 receives a horizontal scan pixel address signal, which is a sequential address necessary for horizontal scanning, and multiplexes one address signal according to the device control signal of the frame memory control logic 400 to radiate one address signal to the radix field memory 406. And output to the address input terminal of the even field memory 408. The first buffer 410 and the second buffer 412 transmit the image detector output signals to the data input terminals of the field memories 406 and 408 and the input multiple output terminals 418 in response to the device control signals of the frame memory control logic 400. And outputs data from the field memories 406 and 408 to maintain high impedance in response to the device control signal. The output multiplexer 418 multiplexes and outputs video output data from the image detector output signal, the field memories 406 and 408, or the microprocessor data bus in response to the control signal to the microprocessor data bus and the FIFO type buffer 420. Enter it. The third buffer 414 and the fourth buffer 416 are connected to the output terminal of the output multiplexer 418 to field the microprocessor video data signal or the video data signal output from the output multiplexer 418 in response to the device control signal. Outputs to the data input terminal of the memory (406, 408) or maintains high impedance to block. The FIFO type buffer 420 outputs a video signal in units of pixels in response to the pixel clock, or outputs a digital video signal for continuous horizontal scanning according to a control signal from the frame memory control logic 400. The frame memory control logic 400 includes an odd or even field selection control signal, an address signal supplied to each field memory 406 and 408, device control signals of the multiplexers 402, 404, 418 and buffers 410, 412, 414, 416, and memory read / write. (write) signal, sequential address signal for horizontal scanning to be input to FIFO type buffer 420, and microprocessor accesses frame memory while inputting pixel output for horizontal scanning to FIFO type buffer 420 during horizontal regression In this case, it functions as a dual port random access memory (hereinafter referred to as RAM) by outputting a busy signal.

In the case of the horizontal scanning method, the output of the image detector is separated by the odd field and the even field, and stored in the location defined by the address signal of each field memory 406 and 408, and the pixel video signal output of the field memory 406 and 408 is It can be output to a digital video output port, which is an output terminal of a microprocessor (not shown) and a FIFO-type buffer 420. The distinction is that there is a blank section in which the actual video signal is horizontally revolved during one horizontal scan. 5 is a timing diagram illustrating a pixel output and a microprocessor input / output stage according to a horizontal blank signal. Referring to FIG. 5, the frame memory control logic 400 outputs a pixel input control signal to store a digital video signal for the next horizontal scan line in the FIFO type buffer 420 during a blank period, and outputs a microprocessor during the horizontal scan activation period. The field memories 406 and 408 can be accessed by (not shown), and a digital video signal of one horizontal scan line stored in the FIFO-type buffer 420 is output in synchronization with an external video clock during the horizontal scan activation period. This is possible because when configuring the bank of each field memory, several pixels can be read at once. The digital video address is selected from the frame memory control logic 400 by selecting the horizontal scan pixel address signal generated for each pixel of the horizontal scan line to be stored in the FIFO buffer 420 during the blank period and the address of the microprocessor. (406, 408). In order to solve the real wiring difficulties, it is preferable that the address for reading the pixel video signal to be stored in the FIF0 type buffer 420 is generated in the video frame memory control logic 400 without being supplied from the outside.

Referring to the operation according to the scanning process of the frame memory of the present invention configured as described above, first, the memory bank for storing the input of the image detector that is a continuous input and the memory selected to make a microprocessor or a continuous pixel output The banks are separated in consideration of the structure of each image detector. In the scanning method, when a memory storing a line of pixels for output is selected, whether the image detector is horizontally scanned or vertically scanned, the frame memory control logic 400 is horizontal to indicate the horizontal retrace time of the output image signal. In response to a blank signal / HBLANK, a scan conversion signal and a pixel input control signal are output to read several pixels at a time and store the pixels in the FlFO-type buffer 420 during the horizontal retrace period. When the horizontal output is completed and the horizontal output is activated, the FIFO type buffer 420 outputs the synchronized pixels in response to the pixel clock PCLK, which is the basic pixel clock of the output, and stores the FIFO type as described above. Repeat this. The memory selection method according to the scanning method of the image detector is as follows. When using this memory device in a camera that performs horizontal scanning and requires interlaced output, one horizontal scan is completed in one-fifth of a sixty-second period, a field of data input from the image detector. Will continue to operate as opposed to the current pixel output or the output field of the microprocessor. This has a delay of one field between the image information input at the current detector and the image information output. On the other hand, when vertical scanning and sequential scanning rather than interlaced scanning are required, vertical scanning separates the output for the detector output and image output in units of lines rather than fields. This means that the analog-digital converted pixels of the stored detector are outputted to the digital image processing / output unit or the microprocessor by one line delay than the line storing the detector output. This method is effective for real-time image processing because it has a delay of one line between the image information input from the detector and the image information output from the detector compared to a horizontal scan camera. When the sequential scanning method is required for horizontal scanning of the detector, it is possible to configure it by two frame memory banks instead of the field memory.For the cameras in which the detector is vertically scanned and the interaced image output is required, the detector vertical scanning is mentioned. In the structure of the sequential scanning system, the control logic only divides the radix line and the even line to store and output. This can be extended to this concept even for a small planar image detection device.

For better understanding, the video frame memory device of the present invention is regarded as a unified device, and the terminals corresponding to the external input signal and the external output signal will be described separately. 6 illustrates an external input / output terminal of the image frame memory device of the present invention. Referring to FIG. 6, an output once detected by an image detector is converted into a digital signal through an analog-digital converter and input to an image frame memory input terminal nVIN [m: 0], and simultaneously stored in a memory for each scanning step. The synchronization signal (DetSync) is supplied to the frame memory control logic to store it. Here, nVIN, which is a reference code of the video frame memory input terminal nVIN [m: 0], means that the input is divided into n channels according to the characteristics of the image detector used, and [m: 0] is an analog-to-digital conversion. It means a gray level (gray leve1) of the detected detection pixel. The control logic in the frame memory is operated by the detector clock (DetCLK), which is the basic operation clock of the detector, and continuously outputs a single pixel in a section where the video output is substantially activated, not the vertical retrace section and the horizontal retrace section, for image output. The signal S [m: 0] is output. This is accomplished by the internal control logic being operated by the synchronization signal of the actual video output (VidSync: VidSync typically includes HSYNC, HBLANK, VSYNC and VBLANK) and the pixel clock PCLK, which is the basic pixel clock. Meanwhile, the microprocessor performs an image processing algorithm by reading data of an image frame in order to execute its own image processing algorithm. For this purpose, the address processor A [s: 0] and the bus control signal CPUCtrl: RD, WR are performed. Input / output is performed by D [w: 0], which is a data bus connected to the frame memory. In this case, the bit width of the commonly used pixels is 8 to 12 bits, whereas the microprocessors used in these days are capable of 32 bit or 64 bit input / output, so the width of the data bus is not limited to the bit width of the pixel, but the width of the pixel is measured in units of width. Done. The video frame memory device of the present invention described above may be configured as one chip by a semiconductor manufacturing process at the level of those skilled in the art having ordinary technical knowledge in the art.

As described above, the frame memory device of the present invention can cope with various types of detector scanning methods and interlaced and progressive scanning image output methods, and outputs video data to a microprocessor while outputting video data on a regular basis. There is an advantage that the parallel image processing function can be provided without additional frame memory to the camera function of sequentially outputting video signals of data.

Claims (3)

A video frame memory that stores digital video signals input from an image detector into radix field video data and even field video data, and multiplexes and outputs them according to a control signal, and outputs the image detector to a place designated by an address input signal at the time of input. A radix field memory and even field memory for storing the radix field video data and the even field video data of a signal, respectively, and outputting radix field video data and even field video data stored from a place designated by the address input signal at the time of output; When the output terminal is connected to the data input terminal of the odd / excellent field memory and the video data is input to the odd / excellent field memory, the image detector output signal is output to the data terminal, and the video from the odd / excellent field memory is output. A first buffer and a second buffer, which are three-phase buffers for maintaining high impedance when data is output; An output multiplexer for multiplexing and outputting video output data from the odd / excellent field memory or video data from the microprocessor; A microprocessor data input / output port for inputting the video data output from the output multiplexer to the microprocessor and inputting the video data output from the microprocessor to the odd / excellent video field memory; An input terminal is connected to the microprocessor data input / output port, and an output terminal is connected to the input terminals of the radix / excellent field memory and the output multiplexer to output video data from the microprocessor to the radix / excellent field memory upon input, and to output high impedance. A third buffer and a fourth buffer which are three phase buffers for holding the buffer; An image detector scan address signal, a microprocessor address bus signal, and a horizontal scan pixel address signal are connected to an input terminal, and an address input terminal of the odd / excellent field memory is connected to an output terminal to select one address by multiplexing the three address signals. Radix field address multiplexer and even field address multiplexer for outputting; An FIFO type buffer having an input connected to an output of the output multiplexer and outputting a digital video signal for continuous horizontal scanning; And a frame memory control logic provided in the video frame memory to control input / output and processing of the video data. The frame memory control logic of claim 1, wherein the frame memory control logic comprises an odd field or even field selection control signal, an address signal supplied to the odd / excellent field memory, a device control signal of the multiplexers and the buffers, a memory read / write signal, And a frame memory control logic in which logic is implemented to output a sequential address signal, the horizontal scan pixel address signal, and a busy signal. The digital video signal input from the image detector is divided into odd field video data and even field video data or odd line video data and even line video data, and is then multiplexed and output according to a control signal. The frame memory control logic may include: outputting a pixel input control signal in response to a horizontal blank signal representing a horizontal retrace time of the output video signal and a scan conversion signal; During the blank period, in response to the pixel input control signal, the FIFO type buffer, which is an output buffer, stores one line of video pixel output; Outputting a synchronized video pixel in response to the pixel clock which is the basic pixel clock of the output when the horizontal output is completed and the horizontal output is activated; Performing microprocessor input / output during the scan activation period; And repeating the above-described first-in-first-out (FIFO) type storage operation. The video data processing method of a video frame memory supporting parallel image processing of video sequential output and microprocessor image processing.