KR19990006151A - Metal wiring method of semiconductor device - Google Patents
Metal wiring method of semiconductor device Download PDFInfo
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- KR19990006151A KR19990006151A KR1019970030373A KR19970030373A KR19990006151A KR 19990006151 A KR19990006151 A KR 19990006151A KR 1019970030373 A KR1019970030373 A KR 1019970030373A KR 19970030373 A KR19970030373 A KR 19970030373A KR 19990006151 A KR19990006151 A KR 19990006151A
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- Prior art keywords
- metal wiring
- metal
- seed
- layer
- semiconductor device
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 49
- 239000002184 metal Substances 0.000 title claims abstract description 49
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 30
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 8
- 239000007769 metal material Substances 0.000 claims abstract description 7
- 238000000206 photolithography Methods 0.000 claims abstract description 4
- 239000002356 single layer Substances 0.000 claims abstract description 4
- 239000010949 copper Substances 0.000 claims description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 16
- 229910052802 copper Inorganic materials 0.000 claims description 16
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- NXDMHKQJWIMEEE-UHFFFAOYSA-N 4-(4-aminophenoxy)aniline;furo[3,4-f][2]benzofuran-1,3,5,7-tetrone Chemical group C1=CC(N)=CC=C1OC1=CC=C(N)C=C1.C1=C2C(=O)OC(=O)C2=CC2=C1C(=O)OC2=O NXDMHKQJWIMEEE-UHFFFAOYSA-N 0.000 claims 1
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 claims 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910021591 Copper(I) chloride Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- OXBLHERUFWYNTN-UHFFFAOYSA-M copper(I) chloride Chemical compound [Cu]Cl OXBLHERUFWYNTN-UHFFFAOYSA-M 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 플러그와 금속 배선을 화학 기상 증착법에 의해 동시에 형성하는 반도체 소자의 금속 배선 방법에 관한 것이다. 상기 목적을 달성하기 위하여, 반도체 기판 상에 단층 또는 다층 금속 배선 형성을 위한 반도체 소자의 금속 배선 방법으로서, 하부 전도층 상에 금속 배선을 위한 콘택홀 또는 비아가 기형성된 반도체 기판을 제공하는 단계; 상기 전체 구조 상에 시드층을 증착하는 단계; 사진 식각 공정을 통하여 상기 시드층으로 형성된 시드 패턴을 형성하며, 상기 콘택홀 또는 비아의 내부 측벽에 제1시드 패턴 및 금속 배선이 형성되는 상기 콘택홀 또는 비아와 인접한 상기 층간 절연막 상에 소정 크기의 제2시드 패턴을 형성하는 단계; 및 상기 시드 패턴에 선택적으로 증착되는 금속 물질을 화학 기상 증착 방식에 의해 증착하여 상기 제1패턴 상에 금속막을 증착하여 플러그를 형성하고 동시에 상기 제2시드 패턴 상에 금속막을 형성하는 단계로, 증착된 상기 플러그와 금속막이 서로 병합되어 하나의 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal wiring method of a semiconductor device in which a plug and a metal wiring of the semiconductor device are simultaneously formed by chemical vapor deposition. In order to achieve the above object, a metal wiring method of a semiconductor device for forming a single layer or a multi-layer metal wiring on a semiconductor substrate, comprising: providing a semiconductor substrate with a contact hole or via preformed for metal wiring on a lower conductive layer; Depositing a seed layer over the entire structure; A seed pattern formed of the seed layer is formed through a photolithography process, and a predetermined size is formed on the interlayer insulating layer adjacent to the contact hole or via where the first seed pattern and the metal wiring are formed on the inner sidewall of the contact hole or the via. Forming a second seed pattern; And depositing a metal material selectively deposited on the seed pattern by chemical vapor deposition to form a plug by depositing a metal film on the first pattern, and simultaneously forming a metal film on the second seed pattern. And the plug and the metal film are merged with each other to form a single metal wire.
Description
본 발명은 반도체 소자의 금속 배선 방법에 관한 것으로, 특히 반도체 소자의 플러그와 금속 배선을 화학 기상 증착법에 의해 동시에 형성하는 반도체 소자의 금속 배선 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal wiring method of a semiconductor device, and more particularly to a metal wiring method of a semiconductor device in which a plug and a metal wiring of the semiconductor device are simultaneously formed by chemical vapor deposition.
반도체 소자가 고집적화됨에 따라 디자인 룰이 감소되고, 이에 따라 미세 패턴들을 형성하기 위하여 새로운 재료 및 공정 기술들이 요구되고 있다. 일례로, 반도체 소자의 금속 배선을 위한 콘택홀 또는 비아의 경우 그 크기가 미세해지고 단차비(Aspect ratio)가 커지면서, 전기장에 의해 가속된 자유 전자들이 아르곤 가스 분자와 충돌하여 아르곤 분자를 이온화하고 이렇게 이온화된 아르곤 분자들이 타겟 물질을 스퍼터링시켜 반도체 기판 상에 증착하는 현재의 스퍼터링(Sputtering) 방식으로는 양호한 층덮힘(Step Coverage) 특성을 갖는 미세 콘택을 형성하기 힘들다.As semiconductor devices are highly integrated, design rules are reduced, and new materials and process technologies are required to form fine patterns. For example, in the case of a contact hole or a via for a metal wiring of a semiconductor device, as its size becomes smaller and the aspect ratio becomes larger, free electrons accelerated by an electric field collide with argon gas molecules to ionize argon molecules and thus With the current sputtering method in which ionized argon molecules sputter a target material and deposit it on a semiconductor substrate, it is difficult to form fine contacts having good step coverage characteristics.
이에 따라, 종래에는 도 1에서와 같이 반도체 기판 또는 금속 배선과 같은 하부 전도층(100) 상의 층간 절연막(110) 내에 형성된 콘택홀이나 비아를 먼저 화학기상 증착(이하, CVD) 방식으로 텅스텐(120)을 매립한 다음 화학적 기계적 연마(CMP)로 텅스텐 플러그를 형성한다. 그 다음, 그 상부에 알루미늄 합금(130)의 금속막을 증착하여 식각함으로써 금속 배선을 형성한다.Accordingly, conventionally, as shown in FIG. 1, a contact hole or a via formed in the interlayer insulating layer 110 on the lower conductive layer 100, such as a semiconductor substrate or a metal wire, is first deposited by chemical vapor deposition (hereinafter, referred to as CVD). ) And then tungsten plug is formed by chemical mechanical polishing (CMP). Next, a metal film of the aluminum alloy 130 is deposited and etched thereon to form metal wirings.
그러나, 이 경우 텅스텐 플러그와 알루미늄 배선 사이에 반응물의 발생을 방지하고 젖음성(Wettability)을 증가시키기 위해 티타늄/티타늄 질화막(Ti/TiN) 등을 증착한다.In this case, however, a titanium / titanium nitride film (Ti / TiN) or the like is deposited to prevent the generation of reactants and increase wettability between the tungsten plug and the aluminum wiring.
그러나, 종래의 금속 배선 공정은 여러 공정이 추가되기 때문에 공정 순서가 복잡한 문제점이 있다. 또한, 현재의 금속 배선 재료로 사용되는 알루미늄 합금은 단가가 저렴하여 경제성이 있으나, 구리(Cu)에 비해 전기 비저항이 높고 일렉트로마이크레이션(Electromigration)에 대해 낮은 저항성을 갖는 문제점이 있다.However, the conventional metal wiring process has a problem in that the process sequence is complicated because several processes are added. In addition, although the aluminum alloy used as the current metal wiring material is economical due to low cost, there is a problem in that the electrical resistivity is higher than that of copper (Cu) and low resistance to electromigration.
따라서, 본 발명은 금속 배선이 형성되어야 하는 소정 영역 상에 시드 패턴(Seed pattern)을 형성하고, 이 시드층을 따라 선택적 증착이 가능한 금속 물질을 CVD 방식으로 증착하여 플러그(Plug)와 금속 배선을 동시에 형성함으로써, 반도체 소자의 신뢰성을 향상시키고 제조 공정을 단순화할 수 있는 반도체 소자의 금속 배선 방법을 제공하는데 그 목적이 있다. 또한, 낮은 전기 비저항값을 갖는 금속 물질을 증착하여 반도체 소자의 동작 속도를 증가시킬 수 있는 반도체 소자의 금속 배선 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention forms a seed pattern on a predetermined region where a metal wiring is to be formed, and deposits a metal material which can be selectively deposited along the seed layer by CVD to form a plug and a metal wiring. By forming at the same time, an object of the present invention is to provide a metal wiring method of a semiconductor device that can improve the reliability of the semiconductor device and simplify the manufacturing process. Another object of the present invention is to provide a metal wiring method of a semiconductor device capable of increasing the operation speed of a semiconductor device by depositing a metal material having a low electrical resistivity.
도 1은 종래 반도체 소자의 금속 배선을 나타내는 단면도.1 is a cross-sectional view showing a metal wiring of a conventional semiconductor element.
도 2A 및 도 2C는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 공정을 나타내는 공정 단면도.2A and 2C are cross-sectional views illustrating a metal wiring process of a semiconductor device in accordance with an embodiment of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
100,200: 하부 전도층110,210: 층간 절연막100,200: lower conductive layer 110, 210: interlayer insulating film
120: 텅스텐130: 알루미늄 합금120: tungsten 130: aluminum alloy
220a,220b: 시드 패턴230: 구리막220a and 220b: seed pattern 230: copper film
상기 목적을 달성하기 위하여, 본 발명에 따른 반도체 기판 상에 단층 또는 다층 금속 배선 형성을 위한 반도체 소자의 금속 배선 방법으로서, 하부 전도층 상에 금속 배선을 위한 콘택홀 또는 비아가 기형성된 반도체 기판을 제공하는 단계; 상기 전체 구조 상에 시드층을 증착하는 단계; 사진 식각 공정을 통하여 상기 시드층으로 형성된 시드 패턴을 형성하며, 상기 콘택홀 또는 비아의 내부 측벽에 제1시드 패턴 및 금속 배선이 형성되는 상기 콘택홀 또는 비아와 인접한 상기 층간 절연막 상에 소정 크기의 제2시드 패턴을 형성하는 단계; 및 상기 시드 패턴에 선택적으로 증착되는 금속 물질을 화학 기상 증착 방식에 의해 증착하여 상기 제1패턴 상에 금속막을 증착하여 플러그를 형성하고 동시에 상기 제2시드 패턴 상에 금속막을 형성하는 단계로, 증착된 상기 플러그와 금속막이 서로 병합되어 하나의 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a metal wiring method of a semiconductor device for forming a single layer or a multi-layer metal wiring on the semiconductor substrate according to the present invention, a semiconductor substrate in which a contact hole or via for metal wiring is pre-formed on the lower conductive layer Providing; Depositing a seed layer over the entire structure; A seed pattern formed of the seed layer is formed through a photolithography process, and a predetermined size is formed on the interlayer insulating layer adjacent to the contact hole or via where the first seed pattern and the metal wiring are formed on the inner sidewall of the contact hole or the via. Forming a second seed pattern; And depositing a metal material selectively deposited on the seed pattern by chemical vapor deposition to form a plug by depositing a metal film on the first pattern, and simultaneously forming a metal film on the second seed pattern. And the plug and the metal film are merged with each other to form a single metal wire.
[실시예]EXAMPLE
반응 챔버에 주입된 화학 반응 기체들의 확산, 흡착 및 화학 반응에 의해 증착되는 CVD는 종래의 스퍼터링과 같은 물리 기상 증착(PVD)에 비해 단차 부위에서 증착층의 층덮힘 특성이 매우 양호하다. 그리고, 구리는 전기 비저항이 낮고 일렉트로마이크레이션에 대해 높은 저항성을 갖기 때문에 서브마이크론 이하로 반도체 소자를 제조하는 경우, 전도성 물질로 유망하다.CVD deposited by diffusion, adsorption, and chemical reaction of chemical reaction gases injected into the reaction chamber has a very good layer covering characteristic of the deposition layer at the stepped area, compared to physical vapor deposition (PVD) such as conventional sputtering. And since copper has low electrical resistivity and high resistance to electromigration, it is promising as a conductive material when manufacturing a semiconductor device below submicron.
그러나, 구리막은 건식 식각시 CuCl과 같은 식각 부산물을 형성하기 때문에 종래에 그 이용 범위가 제한적이다. 본 발명에서는 예정된 영역 상에 시드층을 형성하고 그 영역 상에 선택적으로 구리를 증착함으로써 식각으로 인한 문제점을 해결할 수 있다.However, since the copper film forms etching by-products such as CuCl during dry etching, its use range is conventionally limited. In the present invention, a problem due to etching may be solved by forming a seed layer on a predetermined region and selectively depositing copper on the region.
이하, 첨부된 도면을 참조로하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 2A 및 도 2C는 본 발명의 실시예에 따른 반도체 소자의 단층 또는 다층금속 배선 형성 과정을 나타내는 공정 단면도이다.2A and 2C are cross-sectional views illustrating a process of forming a single layer or multilayer metal wiring of a semiconductor device according to an embodiment of the present invention.
종래 기술과 동일한 방법으로, 도 2A와 같이 반도체 기판 또는 금속 배선과 같은 하부 전도층(200) 상에 층간 절연막(210)을 증착한다. 이어서, 사진 식각 공정을 통하여 상기 하부 전도층에 금속 배선을 형성하기 위한 콘택홀 또는 비아(H)를 형성한다. 그런 다음, 전체 구조 상에 구리막이 선택적으로 성장할 수 있는 시드층(Seed layer)을 증착한다. 따라서, 화학 기상 증착에 의해 구리를 증착할 경우, 시드층이 있는 부분에서는 구리막이 형성되지만 층간 절연막 상에는 형성되지 않는다. 구리를 선택적으로 증착하기 위한 시드층으로는 PMDA-ODA(Pyromellitic Dianhydride-Oxydianiline), 티타늄, 티타늄 질화막, 텅스텐, 구리 등이 사용된다.In the same manner as in the prior art, an interlayer insulating film 210 is deposited on the lower conductive layer 200, such as a semiconductor substrate or a metal wire, as shown in FIG. 2A. Subsequently, contact holes or vias H are formed in the lower conductive layer through the photolithography process. Then, a seed layer on which the copper film can be selectively grown is deposited over the entire structure. Therefore, in the case of depositing copper by chemical vapor deposition, a copper film is formed in the portion where the seed layer exists, but not on the interlayer insulating film. As the seed layer for selectively depositing copper, Pyromellitic Dianhydride-Oxydianiline (PMDA-ODA), titanium, titanium nitride, tungsten, copper, and the like are used.
이어서, 도 2B와 같이 사진 식각 공정을 통하여 상기 콘택홀 또는 비아(H)의 내부 측벽과, 금속 배선이 형성되어야 하는 층간 절연막 상의 소정 영역에 상기 시드 패턴(220a,220b)을 형성한다.Subsequently, as shown in FIG. 2B, the seed patterns 220a and 220b are formed in the inner sidewall of the contact hole or the via H and a predetermined region on the interlayer insulating layer where the metal wiring is to be formed.
그리고, 도 2C와 같이 화학 기상 증착 방식으로 상기 시드 패턴(220a,220b)상에 구리막(230)을 증착한다. 이 때, 상기 콘택홀이나 비아의 제1시드 패턴(220a)상에 증착되는 구리막과 층간 절연막 상의 제2시드 패턴(220b)에 증착되는 구리막이 성장하여 서로 병합(Merge)되어 금속 배선을 완성함으로써, 상기 콘택홀 또는 비아의 플러그를 형성하면서 동시에 금속 배선을 형성할 수 있다.As shown in FIG. 2C, the copper layer 230 is deposited on the seed patterns 220a and 220b by chemical vapor deposition. At this time, the copper film deposited on the first seed pattern 220a of the contact hole or via and the copper film deposited on the second seed pattern 220b on the interlayer insulating film are grown and merged to complete the metal wiring. As a result, the metal wiring can be formed while the plug of the contact hole or the via is formed.
이상에서 설명한 바와 같이, 본 발명은 하부에 형성된 시드 패턴을 따라 선택적 증착이 가능한 금속 물질을 CVD 방식으로 증착하여 동시에 콘택홀이나 비아의 플러그(Plug)와 층간 절연막 상에 금속막을 증착하여 금속 배선을 형성함으로써 반도체 소자의 신뢰성을 향상시키고 제조 공정을 단순화할 수 있다. 또한, 낮은 전기 비저항값을 갖는 구리를 금속 배선으로 사용하여 반도체 소자의 동작 속도를 증가시킬 수 있다.As described above, in the present invention, a metal material capable of selectively depositing along a seed pattern formed at the bottom thereof is deposited by CVD to simultaneously deposit a metal film on a plug and an interlayer insulating layer of a contact hole or via. By forming, the reliability of the semiconductor device can be improved and the manufacturing process can be simplified. In addition, it is possible to increase the operating speed of the semiconductor device by using copper having a low electrical resistivity value as the metal wiring.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100451767B1 (en) * | 2001-12-22 | 2004-10-08 | 주식회사 하이닉스반도체 | Method for forming interconnect structures of semiconductor device |
| KR100927762B1 (en) * | 2007-11-01 | 2009-11-20 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100451767B1 (en) * | 2001-12-22 | 2004-10-08 | 주식회사 하이닉스반도체 | Method for forming interconnect structures of semiconductor device |
| KR100927762B1 (en) * | 2007-11-01 | 2009-11-20 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device and manufacturing method thereof |
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