KR19980077667A - Symbol Timing Recovery Device - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs:

The present invention relates to a digital television receiver.

I. The technical problem the invention is trying to solve:

Conventionally, since many analog parts are used, only a received signal modulated at a specific symbol rate or whose characteristics are shifted due to temperature, use environment, etc., can be demodulated.

All. The gist of the solution of the invention:

The present invention inputs a detected timing error to a loop filter and corrects its output by a value obtained by dividing a sampling frequency by a symbol rate. The symbol timing recovery apparatus is implemented.

la. Important uses of the invention:

Symbol Timing Recovery Device.

Description

Symbol Timing Recovery Device

The present invention relates to a digital television receiver, and more particularly, to a timing recovery apparatus capable of recovering a modulated signal at an arbitrary symbol rate.

A typical communication system must first perform symbol timing before determining what is received at the receiving end. That is, the receiver must ensure that the local clock and symbol timing match.

Once the symbol timing has been adjusted and the receiving decoder has made a decision on the received symbol, it is necessary to match the relationship between the character or word and other timings, including the synchronization of the block or message. In other words, if these symbols cannot be concatenated with the correct message, it becomes difficult to decode long symbols.

The symbol rate means the number of symbols per second transmitted in digital communication, that is, the modulation rate.

The conventional timing recovery apparatus for matching symbol timing is demodulated and recovered in response to a signal modulated at a specific symbol rate used in one transmitting apparatus performing digital communication.

A configuration according to an example of the conventional timing recovery apparatus is as shown in FIG. The operation of the timing recovery device having the configuration as shown in FIG. 1 will be described below.

The symbol timing error included in the received signal is detected by the timing error detector 14. The detected symbol timing error is applied to a loop filter 16 to remove various noises and then to a voltage controlled oscillator (VCO) 18. The VCO 18 generates a clock having a frequency proportional to the voltage level of the signal output from the loop filter 16. The generated clock is applied to an analog-to-digital converter (A / D converter) 10, and the symbol timing recovery is performed by removing the symbol timing error by changing the phase of sampling.

The configuration according to another example of the conventional timing recovery apparatus is as shown in FIG.

The operation of the timing recovery device having the configuration as shown in FIG. 2 will be described below.

Oscillator 34 generates a frequency with a value slightly greater than twice the symbol rate. The generated frequency is applied to the A / D converter 20 and used as a period for sampling the received signal. The signal sampled and output from the oscillator 34 is output through the matched filter 22. The symbol timing error included in the signal output through the matched filter 22 is detected by the timing error detector 14. The detected symbol timing error is applied to a loop filter 16 to remove various noises and then mixed with a signal having a predetermined frequency f in the adder 28. The predetermined frequency f is determined by the value output from the oscillator 34. The mixed signal is applied as a control signal of a numerically controlled oscillator (NCO) 30, and the NCO 30 variably outputs the coefficient of the matching filter 22 to the control signal. The output coefficient is temporarily stored in the ROM 32 and provided to the matching filter 22 to be used as a coefficient for filtering the signal output from the A / D converter 20.

As described above, in the case of using the conventional first method, since the analog parts are used a lot, there are disadvantages in that the characteristic is moved by temperature, use environment, and the like. In addition, when the second method is used, there is a problem that the present invention can be applied only to a reception signal having a fixed symbol rate and thus cannot be applied to a variable symbol rate.

Accordingly, an object of the present invention to solve the above problems is to provide a symbol timing recovery apparatus capable of symbol timing recovery even if the symbol rate of the received signal changes.

1 is a block diagram of a timing recovery apparatus using a conventional VCO.

2 is a block diagram of a conventional timing recovery apparatus.

3 is a block diagram of a timing recovery apparatus according to an embodiment of the present invention.

4 is a detailed configuration diagram of the NCO shown in FIG. 3.

FIG. 5 is a waveform diagram of the NCO shown in FIG. 4. FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used for the same components, even if displayed on different drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

The configuration of the symbol timing recovery apparatus according to an embodiment of the present invention is as shown in FIG. 3.

The symbol timing recovery apparatus shown in FIG. 1 has a configuration in which the timing error is corrected in the interpolation circuit 36 according to the value u of the signal generated by the NCO 30.

Detailed configuration of the NCO 30 shown in FIG. 3 is as shown in FIG.

The NCO 30 illustrated in FIG. 4 includes an adder 40, a D flip flop 42, a zero detector 44, and a multiplier 46.

The adder 40 adds and outputs a signal applied from the adder 28 shown in FIG. 3 and a signal fed back from the D flip flop 42. The D flip flop 42 delays the signal applied from the adder 40 by a predetermined clock. The zero detector 44 detects a zero crossing of the signal applied from the D flip flop 42 and outputs a symbol clock. The multiplier 46 outputs a signal u multiplied by a signal applied from the D flip flop 42 and a signal having a predetermined frequency f _sam / f _sym .

FIG. 5 is a diagram showing an output waveform diagram of the NCO 30 having the configuration of FIG. 4 described above.

Hereinafter, a preferred embodiment according to the present invention will be described in detail with reference to the configuration of the symbol timing recovery apparatus described above.

The signal output through the matched filter 22 is applied to the timing error detector 24 to detect the timing error signal. The detected timing error signal is applied to the loop filter 24, and the applied timing error signal is filtered and output by the bandwidth of the loop filter 26. The filtered timing error signal is applied to the adder 28, and the timing error signal applied to the adder 28 is corrected by f value and applied to the NCO 30. The f value represents -f _sym / f _sam , where f _sym represents a symbol rate and f _sam represents a sampling frequency. The NCO 30 generates a symbol clock whenever the signal corrected from the adder 28 is zero-crossed. In addition, the NCO 30 outputs a u value for determining the phase of the interpolation circuit 36 based on a signal corrected and applied from the adder 28. The u value determines the phase of the interpolation circuit 36 and corrects the timing error of the signal applied through the A / D converter 20. The structure and operation of the timing error detector 24, the interpolation circuit 36, and the loop filter 26 used in the present invention are not limited to implementation by using a conventional circuit.

However, the operation of the NCO 30 used in the present invention will be described in more detail as follows.

The signal applied from the adder 28 shown in FIG. 3 is output in combination with the signal fed back from the D flip flop 42 in the adder 40 shown in FIG. The signal output from the adder 40 is delayed and output from the D flip flop 42. The signal output from the D flip flop 42 is applied to the zero detector 44 and the multiplier 46, respectively. By the applied signal, the zero detector 44 outputs a symbol clock by noting that the signal is zero-crossed. The multiplier 46 multiplies the signal by f _sam / f _sym and outputs the multiplied signal. The signal output from the multiplier 46 is applied to the interpolation circuit 36 to become a u value for determining the phase.

Therefore, the present invention can recover a modulated signal at an arbitrary symbol rate without changing hardware if only the value of f _sam / f _{sym is} known. The range of possible symbol rate changes is from 0 to f _sam / 2.

As described above, the present invention can recover a signal modulated at any symbol rate by knowing only the value (f _sam / f _sym ) obtained by dividing the sampling frequency by the symbol rate. Therefore, there is an effect that can recover a modulated signal with a wider symbol rate without the provision of special hardware.

Claims (2)

1. In a symbol timing recovery circuit, an oscillator for generating a sampling frequency, an analog / digital converter for sampling received analog signals according to the sampling frequency and converting them into digital data; A loop filter for filtering, a first adder for adding and outputting a digital signal having a predetermined frequency and an output of the loop filter, a numerically controlled oscillator for oscillating by outputting data from the first adder and outputting adjustment data; And an interpolation circuit for interpolating digital data output from the analog / digital converter according to the adjustment data. 2. The apparatus of claim 1, wherein the numerically controlled oscillator comprises: a D flip flop for delaying an applied signal by a predetermined time; A two-adder, a zero detector for detecting a zero state of the signal applied from the D flip flop, and generating a symbol clock, and multiplying the value obtained by dividing the sampling frequency by a symbol rate by the signal applied from the D flip flop; Symbol timing recovery apparatus, characterized in that consisting of a multiplier for outputting.