KR19980073448A - Pads for Wire Bonding in Semiconductor Memory Devices - Google Patents
Pads for Wire Bonding in Semiconductor Memory Devices Download PDFInfo
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- KR19980073448A KR19980073448A KR1019970008719A KR19970008719A KR19980073448A KR 19980073448 A KR19980073448 A KR 19980073448A KR 1019970008719 A KR1019970008719 A KR 1019970008719A KR 19970008719 A KR19970008719 A KR 19970008719A KR 19980073448 A KR19980073448 A KR 19980073448A
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- Prior art keywords
- pads
- semiconductor memory
- memory device
- wire bonding
- pad
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title abstract description 21
- 238000003491 array Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Static Random-Access Memory (AREA)
Abstract
본 발명은 반도체 메모리 장치의 와이어 본딩(bonding)용 패드에 관한 것으로서, 중앙변에 복수열로 배치되는 패드들, 및 상기 중앙변과 직각인 가장자리변들에 배치되는 패드들을 구비함으로써 전류 소모도 감소되고 반도체 메모리 장치의 데이터 처리 속도도 향상된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pad for wire bonding of a semiconductor memory device, and includes a pad disposed in a plurality of rows at a center side and pads disposed at edges perpendicular to the center side to reduce current consumption. As a result, the data processing speed of the semiconductor memory device is improved.
Description
본 발명은 반도체 메모리 장치에 관한 것으로서, 특히 와이어 본딩용 패드의 배치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to arrangement of pads for wire bonding.
현재의 반도체 메모리 장치는 고집적도를 가지며 멀티핀을 갖는다. 그리고 제조비의 절감을 위해 칩 크기는 점점 더 작아지고 있다. 그러나 칩 크기가 작아지더라도 와이어 본딩용 패드는 기존의 크기대로 유지되어야한다. 따라서 디자인 룰(design rule)의 감소에 의하여 반도체 메모리 장치의 크기는 작아지지만 패드가 반도체 메모리 장치내에서 차지하는 비중은 점점 더 커진다. 특히 멀티 핀을 갖는 반도체 메모리 장치에서는 그 크기가 작아지면서 패드가 반도체 메모리 장치내에서 차지하는 비중이 점점 중요시된다. 그래서 패드의 크기는 작이지지않으면서도 효율적으로 사용될 수 있도록 하는 패드 배치 방법이 중요시되고 있다. 패드를 어떻게 배치하느냐에 따라 데이터의 처리 속도와 전류 소모량이 달라진다.Current semiconductor memory devices have a high degree of integration and have multi-pins. And chip sizes are getting smaller and smaller to reduce manufacturing costs. However, even if the chip size is smaller, the wire bonding pad should be kept in the existing size. Therefore, the size of the semiconductor memory device is reduced due to the reduction of design rules, but the weight of pads in the semiconductor memory device becomes larger. In particular, in the semiconductor memory device having multiple pins, as the size thereof becomes smaller, the weight of the pad in the semiconductor memory device becomes increasingly important. Therefore, the pad placement method that can be used efficiently without the size of the pad is important. The placement of the pads will affect the processing speed and current consumption of the data.
패드를 중앙변에 1열 또는 2열로 배치하는 방법을 이용할 경우, 멀티핀이 필요한 반도체 메모리 장치는 본딩되어야할 패드가 많기 때문에 반도체 메모리 장치의 크기가 작아짐에 따라서 2가지 문제가 발생한다. 하나는 패드 피치(pitch) 한계에 의하여 모든 패드를 중앙변에 배치하기 힘들다는 것이고, 다른 하나는 패드를 중앙변에 모두 배치하더라도 리드 프레임의 리드들간의 피치 한계로 인하여리드 프레임을 제작하지못하는 문제가 있다.When using the method of arranging the pads in a single row or two rows on the center side, two problems arise as the semiconductor memory device is smaller in size, because the semiconductor memory device that requires the multi-pin has many pads to be bonded. One is that it is difficult to place all pads on the center side due to the pad pitch limit. The other is that even if the pads are placed on the center side, the lead frame cannot be manufactured due to the pitch limit between the leads of the lead frame. There is.
패드들을 반도체 메모리 장치의 가장자리변에 배치할 경우, 모든 회로가 패드를 따라 배치되어야 한다. 그럴 경우, 내부 신호용 라인들이 패드들을 따라 배치되기 때문에 라인의 부하가 증가한다. 라인의 부하가 증가함에 따라 신호 라인들을 구동하는 구동기의 크기가 커지게 되어 전류 소모도 증가한다. 그리고 칩의 성능을 나타내는 속도도 저하된다.When the pads are arranged at the edges of the semiconductor memory device, all circuits must be arranged along the pads. In that case, the load on the line increases because the lines for internal signals are arranged along the pads. As the load on the line increases, the size of the driver that drives the signal lines increases, resulting in increased current consumption. And the speed which shows the performance of a chip also falls.
따라서 본 발명이 이루고자하는 기술적 과제는 패드의 크기는 그대로 유지하면서 리드 프레임의 제작이 간편하고 전류 소모가 적으며 데이터 처리 속도가 향상될 수 있는 반도체 메모리 장치의 와이어 본딩용 패드를 제공하는데 있다.Accordingly, an aspect of the present invention is to provide a pad for wire bonding of a semiconductor memory device in which a lead frame can be easily manufactured, current consumption is low, and data processing speed can be improved while maintaining a pad size.
도 1은 본 발명에 따른 반도체 메모리 장치의 와이어 본딩용 패드의 배치도.1 is a layout view of a wire bonding pad of a semiconductor memory device according to the present invention.
상기 기술적 과제를 이루기 위하여 본 발명은,The present invention to achieve the above technical problem,
중앙변에 복수열로 배치되는 패드들, 및 상기 중앙변과 직각인 가장자리변들에 배치되는 패드들을 구비하는 것을 특징으로하는 반도체 메모리 장치를 제공한다.A pad is disposed in a plurality of rows on a central side, and pads disposed on edges perpendicular to the center side.
상기 본 발명에 의하여 리드 프레임의 제작이 간편해지고 전류 소모가 적으며 칩의 데이터 처리 속도가 향상된다.According to the present invention, the production of the lead frame is simplified, the current consumption is low, and the data processing speed of the chip is improved.
이하, 실시예를 통하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail through examples.
도 1은 본 발명에 따른 반도체 메모리 장치의 와이어 본딩용 패드의 배치도이다.1 is a layout view of a wire bonding pad of a semiconductor memory device according to the present invention.
도 1을 참조하면, 반도체 메모리 장치(11) 내에 메모리 어레이들(21)이 배치되어있고, 상기 메모리 어레이들(21) 사이의 중앙 가로변에 패드들(31)이 2열로 배치되어있으며, 상기 패드들(31)과 직각인 가장자리 세로변들에 패드들(33)이 각각 1열로 배치되어있다. 이와같은 패드 배치 구조를 H형 패드 구조라 한다.Referring to FIG. 1, memory arrays 21 are disposed in a semiconductor memory device 11, and pads 31 are arranged in two rows on a central horizontal side between the memory arrays 21. The pads 33 are arranged in one row on the edge vertical sides perpendicular to the fields 31. Such a pad arrangement structure is called an H type pad structure.
상기 H형 패드 구조에서는 패드들이 가장자리변에만 배치되는 구조에서 긴변의 가장자리 패드들, 예컨대 가장자리 가로변들에 배치되는 패드들이 중앙 가로변에 배치되고(31 참조), 짧은 변의 가장자리 패드들, 예컨대 세로변들에 배치되는 패드들이 가로 중앙변과 직각으로 반도체 메모리 장치(11)의 양쪽 가장자리변에 배치된다(33 참조). 그리고, 내부 회로(도시안됨)는 주로 중앙에 배치되고 일부가 가장자리변에 배치된 패드들(33) 부위에 배치된다. 따라서 내부 신호들이 패드들을 따라 존재한다면, 내부 신호가 패드들이 중앙변에만 배치되는 구조에서보다는 길지만 패드들이 가장자리변에만 배치되는 구조보다는 상당히 작아진다. 따라서 패드들이 가장자리변에만 배치되는 구조에 비해 전류 소모도 적고 반도체 메모리 장치(11)의 데이터 처리 속도도 향상된다. 즉, 패드들이 중앙변에만 배치되는 것이 불가능한 멀티핀 반도체 메모리 장치의 경우 본 발명에 따른 H형 패드 구조를 이용함으로써 전류 소모가 감소되고 칩의 데이터 처리 속도도 향상된다.In the H-type pad structure, long side edge pads, for example, pads disposed at edge transverse sides, are arranged at the center horizontal side (see 31) in the structure in which the pads are disposed only at the edge side, and short side edge pads such as vertical sides. Pads disposed in the semiconductor memory device 11 are disposed at both edges of the semiconductor memory device 11 at right angles to the horizontal center side (see 33). In addition, the internal circuit (not shown) is mainly disposed at the center of the pads 33, part of which is disposed at the edge. Thus, if the internal signals are along the pads, the internal signal is longer than in the structure where the pads are arranged only at the center side but considerably smaller than the structure where the pads are arranged only at the edge side. Therefore, the current consumption is lower and the data processing speed of the semiconductor memory device 11 is improved compared to the structure in which the pads are disposed only at the edges. That is, in the case of a multi-pin semiconductor memory device in which pads cannot be disposed only at the center side, current consumption is reduced and the data processing speed of the chip is improved by using the H-type pad structure according to the present invention.
상기 H형 패드 구조는 일반 반도체 장치에도 동일하게 적용될 수 있다.The H-type pad structure can be equally applied to general semiconductor devices.
본 발명은 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.
상술한 바와 같이 본 발명에 따르면, 전류 소모도 감소되면서 칩의 데이터 처리 속도도 향상된다.As described above, according to the present invention, current consumption is reduced, and the data processing speed of the chip is also improved.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970008719A KR100275720B1 (en) | 1997-03-14 | 1997-03-14 | Semiconductor memory divice having effective pad structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970008719A KR100275720B1 (en) | 1997-03-14 | 1997-03-14 | Semiconductor memory divice having effective pad structure |
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| Publication Number | Publication Date |
|---|---|
| KR19980073448A true KR19980073448A (en) | 1998-11-05 |
| KR100275720B1 KR100275720B1 (en) | 2001-01-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019970008719A KR100275720B1 (en) | 1997-03-14 | 1997-03-14 | Semiconductor memory divice having effective pad structure |
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| KR (1) | KR100275720B1 (en) |
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- 1997-03-14 KR KR1019970008719A patent/KR100275720B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR100275720B1 (en) | 2001-01-15 |
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