KR102732567B1 - Display device and method of driving thereof - Google Patents

Abstract

A display device and a driving method thereof are provided. The display device comprises: a display panel having a display area in which a plurality of sub-pixels are arranged along rows and columns; a plurality of data lines arranged one for each column of a pair of sub-pixels arranged in the display area and supplying data voltages to sub-pixels arranged in both sub-pixel columns; a plurality of gate lines arranged one for each row of sub-pixels arranged in the display area and supplying scan signals to sub-pixels arranged in the rows of each sub-pixel; a plurality of gate drivers arranged one for each gate line arranged in the display area and generating scan signals supplied by each gate line to the sub-pixels; and a plurality of signal lines arranged alternately with the plurality of data lines in each sub-pixel column unit and supplying signals for the operation of the gate drivers, wherein the gate drivers are composed of a plurality of gate drivers, and each gate driver is arranged in the display area to correspond to a continuous predetermined number of sub-pixel columns and supplies scan signals to corresponding gate lines. The present invention is characterized in that:

Description

DISPLAY DEVICE AND METHOD OF DRIVING THEREOF

The present invention relates to a display device, and more specifically, to a display device capable of implementing a narrow bezel while reducing a non-display area of a display panel, and a method for driving the same.

As the information society develops, the demand for display devices with various forms and functions that visually display electrical information signals is increasing. In response to this demand, display devices such as liquid crystal display devices (LCDs) and organic light emitting diode displays (OLED displays) are being utilized.

In addition, various studies are being conducted on display devices to improve their performance, such as making them larger, thinner, lighter, higher resolution, and lower power consumption.

In particular, a display panel constituting a display device is composed of a display area in which sub-pixels defined by a plurality of gate lines and data lines are arranged in a matrix structure, and a non-display area in which signal lines for supplying signals to the gate lines and data lines of the display area are arranged.

Recently, a GIP (Gantt On Panel) structure display device has been developed in which the gate drive circuit that supplies the scan signal (gate signal) is directly mounted on the display panel to reduce manufacturing costs and simplify the process.

However, a GIP structure display device like this has a problem in that it is difficult to implement a narrow bezel in the display device because the non-display area of the display panel increases.

Therefore, there is a need to develop a narrow bezel display device that has the advantages of conventional GIP structure display devices while meeting consumer needs.

The problem to be solved by the present invention is to provide a display device and a driving method thereof capable of securing a maximum display area for displaying an image by arranging a driving circuit of a display panel in the display area.

Another problem to be solved by the present invention is to provide a display device and a driving method thereof capable of implementing a narrow bezel by minimizing the non-display area of the display panel.

Another problem that the present invention seeks to solve is to provide a display device and a driving method thereof that improves the output reliability of a scan signal by preventing the Q node of a gate driving unit from floating throughout the entire section in which a scan signal is output.

Another problem that the present invention seeks to solve is to provide a display device and a driving method thereof that enable image display and touch operation by preventing the Q node of the gate driving unit from being in a floating state.

The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the description below.

In order to solve the above-described problem, a display device according to an embodiment of the present invention includes a display panel having a display area in which a plurality of sub-pixels are arranged along rows and columns; a plurality of data lines arranged one by one in each column of a pair of sub-pixels arranged in the display area and supplying data voltages to sub-pixels arranged in each of the sub-pixel columns; a plurality of gate lines arranged one by one in each row of the sub-pixels arranged in the display area and supplying scan signals to the sub-pixels arranged in the row of each sub-pixel; a plurality of gate drivers arranged one by one in each gate line arranged in the display area and generating scan signals supplied by each gate line to the sub-pixels; and a plurality of signal lines arranged alternately with the plurality of data lines in each sub-pixel column unit and supplying signals for the operation of the gate drivers, wherein the gate drivers are composed of a plurality of gate drivers, and each gate driver is characterized in that it is arranged in the display area to correspond to a continuous predetermined number of sub-pixel columns and supplies scan signals to corresponding gate lines.

According to another embodiment of the present invention, a display device driving method includes a display panel having a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels arranged along rows and columns, the display device comprising the steps of: supplying a scan signal from a previous (n-1th) gate line among the plurality of gate lines to a gate driver arranged in a display area of the display panel; increasing a voltage level of a Q node of the gate driver by the supplied scan signal; outputting a first clock signal as a scan signal to a current (nth) gate line in response to the increased Q node voltage; decreasing the Q node of the gate driver to a gate low voltage in response to a second clock signal; and supplying and maintaining a gate low voltage to the current (nth) gate line in response to the Q node voltage whose voltage level has been decreased.

Specific details of other embodiments are included in the detailed description and drawings.

The present invention has the effect of securing the maximum display area for displaying an image by arranging the driving circuit of the display panel in the display area.

The present invention has the effect of minimizing the non-display area of the display panel to implement a narrow bezel.

The present invention has the effect of improving the output reliability of a scan signal by preventing the Q node of a gate drive unit from floating throughout the entire section in which a scan signal is output.

The present invention has the effect of enabling image display and touch operation by preventing the Q node of the gate driving unit from being in a floating state.

The effects according to the present invention are not limited to those exemplified above, and further diverse effects are included in the present specification.

FIG. 1 is a block diagram showing a display device according to embodiments of the present invention.
FIGS. 2 and 3 are drawings showing the structure of sub-pixels of a display panel according to embodiments of the present invention.
FIG. 4 is a block diagram showing a schematic configuration of a display panel according to embodiments of the present invention.
FIG. 5 is a drawing illustrating a structure in which a gate driver is arranged in a display area of a display panel according to the first embodiment of the present invention.
FIG. 6 is a waveform diagram for explaining the process of generating a scan signal from a gate driver according to the embodiment of FIG. 5.
FIG. 7 is a block diagram showing a schematic configuration of a display panel according to other embodiments of the present invention.
FIG. 8 is a drawing illustrating a structure in which a gate driver is arranged in a display area of a display panel according to a second embodiment of the present invention.
FIG. 9 is a waveform diagram for explaining the process of generating a scan signal from a gate driver according to the embodiment of FIG. 8.
FIG. 10 is a drawing illustrating a structure in which a gate driver is arranged in a display area of a display panel according to a third embodiment of the present invention.
FIG. 11 is a waveform diagram for explaining the process of generating a scan signal from a gate driver according to the embodiment of FIG. 10.
FIGS. 12A to 15B are drawings for explaining a process in which a scan signal is generated in a gate driver and then supplied to a gate line according to a third embodiment of the present invention.
Figure 16 is a flowchart for explaining a method of driving a display device according to embodiments of the present invention.

The advantages and features of the present invention, and the method for achieving them, will become clear with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and these embodiments are provided only to make the disclosure of the present invention complete and to fully inform a person having ordinary skill in the art to which the present invention belongs of the scope of the invention, and the present invention is defined only by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the matters illustrated. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When the terms “includes,” “has,” “consists of,” etc. are used in this specification, other parts may be added unless “only” is used. When a component is expressed in singular, it includes a case where the plural is included unless there is a specifically explicit description.

When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, when the positional relationship between two parts is described as '~on top', '~upper part', '~lower part', '~side part', etc., one or more other parts may be located between the two parts unless 'right' or 'directly' is used. In addition, for example, when the positional relationship between two parts is described as '~on top', '~lower part', '~side part', etc., it can be described as a location such as '~upper part', '~lower part', '~side part'.

When an element or layer is referred to as being on another element or layer, this includes both cases where the other element is directly on top of the other element or layer, or where there is another layer or other element intervening therebetween.

Also, although the terms first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, a first component mentioned below may also be a second component within the technical concept of the present invention.

Throughout the specification, identical reference numerals refer to identical components.

The size and thickness of each component shown in the drawings are illustrated for convenience of explanation, and the present invention is not necessarily limited to the size and thickness of the illustrated components.

The individual features of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and may be technically linked and driven in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a display device according to embodiments of the present invention. FIGS. 2 and 3 are drawings showing the structure of sub-pixels of a display panel according to embodiments of the present invention.

Referring to FIGS. 1 to 3, a display device (100) of the present invention comprises a display panel (110) having a pixel array formed thereon, and a display panel driving circuit for writing input image data into the display panel (110). The display panel driving circuit writes input image data into pixels composed of sub-pixels. The display panel driving circuit includes a data driving circuit (120), a gate driving circuit (130), and a controller (150).

Here, the data driving circuit (120) is also called a data driver or a source driver, and the gate driving circuit (130) is also called a gate driver or a scan driver. In addition, the controller (150) may be a timing controller used in a typical display technology, or may be a control device that further performs other control functions, including a timing controller.

The display panel (110) may be a liquid crystal display panel including an upper substrate and a lower substrate facing each other with a liquid crystal layer therebetween. Additionally, it may be an organic electroluminescent display panel in which an organic light-emitting diode (OLED) is arranged in each subpixel.

A pixel array on which an input image is displayed is formed in the active area of the display panel (110). The pixel array includes sub-pixels arranged in a matrix form by a cross structure of a plurality of data lines (DL) and a plurality of gate lines (GL).

Here, the direction parallel to the gate line (GL) of the display panel (110) is defined as the X direction (or first direction), and the direction parallel to the data line (DL) is defined as the Y direction (or second direction). In some cases, the X direction may be referred to as a horizontal direction and the Y direction may be referred to as a vertical direction.

When the display panel is a display panel used in a liquid crystal display device, each pixel may be composed of sub-pixels having red (R), green (G), and blue (B) color filter layers arranged for color implementation, or sub-pixels having red (R), green (G), blue (B), and white (W) color filter layers arranged. Here, the white (W) color filter layer may be a layer implemented only with a transparent insulating layer without forming a separate color filter layer.

Referring to FIG. 2, the lower substrate of the display panel (110) may include a plurality of data lines (DL), a plurality of gate lines (GL), a thin film transistor (TR) arranged in an area corresponding to each sub-pixel, a pixel electrode connected to the thin film transistor (TR), a storage capacitor (Cst) connected to the pixel electrode, a common electrode (Vcom) that forms an electric field to control the transmittance of the liquid crystal together with the pixel electrode, etc.

When the display panel (110) is a liquid crystal display device, the thin film transistor (TR) is turned on in response to a scan signal (gate signal) and supplies the data voltage supplied from the data line (DL) to the pixel electrode. The pixel electrode generates an electric field between itself and the common electrode (Vcom) to rotate the liquid crystal molecules of the liquid crystal layer, thereby controlling the transmittance of a light source (a light source of a backlight unit, not shown) supplied from outside the display panel (110).

In addition, when the display panel is a display panel used in an organic electroluminescent display device, a red (R), green (G), or blue (B) organic light-emitting diode (OLED) may be arranged in each sub-pixel, or a blue (B) or white (W) organic light-emitting layer may be arranged in each sub-pixel, and a red (R), green (G), or blue (B) color filter layer may be arranged in a corresponding area.

Referring to FIG. 3, each sub-pixel (SP) of an organic light-emitting display device includes an organic light-emitting diode (OLED) and a pixel circuit unit that is connected to a data line (DL) and a gate line (GL) to control the organic light-emitting diode (OLED). The pixel circuit unit may include a switching transistor (TR1), a driving transistor (TR2), and a storage capacitor (Cst).

An anode electrode of an organic light-emitting diode (OLED) is connected to a driving transistor (TR2), and a cathode electrode is connected to a second power supply (ELVSS). Here, the second power supply (ELVSS) may be a low-voltage power supply. A switching transistor (TR1) is turned on when a scan signal is supplied through a gate line (GL) and transmits a data signal supplied from a data line (DL) to a storage capacitor (Cst).

One terminal of the storage capacitor (Cst) is connected to the gate electrode of the driving transistor (TR2) and the drain electrode of the switching transistor (TR1), and the other terminal is connected to the source electrode of the driving transistor (TR2). In addition, the source electrode of the driving transistor (TR2) is connected to a first power supply (ELVDD) having a relatively higher voltage level than a second power supply (ELVSS).

Therefore, the amount of light generated from the organic light-emitting diode (OLED) is controlled by controlling the current supply flowing from the driving transistor (TR2) to the organic light-emitting diode (OLED) according to the data voltage stored in the storage capacitor (Cst).

In Fig. 3, a relatively simple structure constituting the pixel circuit of a sub-pixel is shown as an example, but in reality, the configuration of the pixel circuit can be changed in various ways depending on the driving method required by the display device.

The gate driving circuit of the present invention can be applied to both the display panel (110) used in a liquid crystal display device and the panel used in an organic electroluminescent display device. Here, the description will focus on the case where the display panel (110) is a display panel used in a liquid crystal display device.

The TFTs arranged in each sub-pixel (SP) area of the display panel (110) can be implemented as amorphous silicon (a-Si) TFTs, crystalline silicon TFTs, LTPS (Low Temperature Poly Silicon) TFTs, oxide TFTs, etc.

A color filter array including a black matrix (BM) and a color filter can be formed on the upper substrate of the display panel (110). However, since this is not fixed, the color filter array can be formed on the lower substrate where the TFTs are formed.

In the present invention, the description is centered on the IPS mode (In-Plane Switching Mode) or FFS mode (Fringe Field Mode), which are horizontal field driving methods in which pixel electrodes and common electrodes are arranged together in a sub-pixel (SP), but the common electrode may be formed on the upper substrate in the case of a vertical field driving method such as the TN (Twisted Nematic) mode and the VA (Vertical Alignment) mode.

Additionally, a polarizing plate may be attached to each of the upper and lower substrates of the display panel (110) and an alignment film may be formed to set the pre-tilt angle of the liquid crystal.

Additionally, touch sensors may be placed on the display panel (110) as an on-cell type or an add on type. To drive such touch sensors, a touch sensor driving circuit (not shown) may be added to the driving circuit of the display device (100).

The touch sensor driving circuit can receive an output signal of the touch sensor, generate coordinates for each touch input, and transmit them to a host system (not shown). In particular, when the touch sensor is an on-cell type built into the display panel (110), a common electrode arranged on the display panel (110) can be used as a touch electrode.

The display device of the present invention can be implemented in any form, such as a transmissive liquid crystal display, a semi-transmissive liquid crystal display, or a reflective liquid crystal display. A backlight unit is required in transmissive liquid crystal display devices and semi-transmissive liquid crystal display devices.

The backlight unit is placed below the display panel (110) and uniformly irradiates light to the display panel (110). The backlight unit can be implemented as a direct type backlight unit or an edge type backlight unit.

In addition, the driving circuit of the display panel (110) may further include a gamma compensation voltage generator (not shown) that supplies a gamma reference voltage (GMA) to the data driving circuit (120). The gamma reference voltage (GMA) may be divided into a positive gamma compensation voltage and a negative gamma compensation voltage within the data driving circuit (120) and supplied to the display panel (110). More specifically, the voltage divided into the positive gamma compensation voltage and the negative gamma compensation voltage may be supplied to a plurality of data lines (DL) by a multiplexer (MUX) (not shown) disposed within the data driving circuit (120) or between the data driving circuit (120) and the display panel (110).

Typically, a positive data voltage is supplied to multiple data lines (DL) through a multiplexer. The positive data voltage supplied to multiple data lines (DL) is a voltage higher than the common voltage (Vcom) applied to the common electrode, and the negative data voltage is a voltage lower than the common voltage (Vcom).

The data drive circuit (120) may include one or more source drive ICs (SICs). Each source drive IC may include multiple channels, and the number of source driver ICs arranged in the data drive circuit (120) may be determined depending on the resolution of the display panel (110).

For example, in the case of an 8k 120Hz model among high-resolution TV models (the number of sub-pixels is 7680*3*4320), the number of channels of the source drive IC is 1920 channels, and 24 source drive ICs can be arranged in the data drive circuit (120).

The gate driving circuit (130) supplies scan signals (gate signals) to a plurality of gate lines (GL) under the control of the controller (150).

The controller (150) transmits input image data received from a host system (not shown) located inside or outside the display device (100) to the data driving circuit (120). The controller (150) receives timing signals synchronized with the input image data from the host system.

Timing signals include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), a main clock (DCLK), etc. The controller (150) controls the operation timing of the data driving circuit (120) and the gate driving circuit (130) based on the timing signals (Vsync, Hsync, DE, DCLK).

The gate control signal is generated by the controller (150) to control the operation timing of the gate driving circuit (130). The gate control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), etc. The gate start pulse (GSP) controls the start operation timing of the gate driving circuit (130). The gate shift clock (GSC) is a clock signal for shifting the gate start pulse (GSP). The gate output enable signal (GOE) controls the output timing of the gate driving circuit (130).

The source control signal is generated by the controller (150) to control the operation timing of the data driving circuit (120). The source control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), a source output enable signal (SOE), etc.

The source start pulse (SSP) controls the data sampling start timing of the data driving circuit (120). The source sampling clock (SSC) is a clock signal that controls the data sampling timing of the data driving circuit (120). The polarity control signal (POL) controls the polarity of the data voltage output from the data driving circuit (120). The source output enable signal (SOE) controls the charge sharing timing and the data output timing. The controller (150) can transmit the gate control signal and the source control signal through separate wiring or can code information about the on/off (or high/low) level of each of the signals into a control data packet and serially transmit it to the source drive ICs together with the input image data.

The controller (150) can control the driving frequency of the display panel (110) to the N-multiplied frame rate by increasing the frame rate to a frequency of the frame rate (or frame frequency) of the input image × N (N is a positive integer greater than or equal to 2) Hz. The frame rate is 60 Hz in the NTSC (National Television Standards Committee) method and 50 Hz in the PAL (Phase-Alternating Line) method. Recently, there is a trend to adopt a method of increasing the frame rate to 120 Hz or more in order to implement high-resolution images such as UHD.

In addition, if the data of the input image hardly changes or is a still image, the controller (150) drives the display panel driving circuit at a low speed to reduce power consumption and lowers the update frequency of data written to the pixels. For example, the timing controller (150) can lower the frame rate to 30 Hz or less in the low-speed driving mode. The frame rate in the low-speed driving mode can be referred to as LRR (Low Refresh Rate).

The controller (150) receives digital video data (RGB) of an image and timing signals (Vsync, Hsync, DE, CLK) from a host system (not shown) that controls a television system, a home theater system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a phone system, a mobile device, a wearable device, etc. The host system can execute an application program in conjunction with coordinate information of a touch input input from a touch sensor driving circuit disposed in a display device (100).

It is defined as the area where the data line (DL) and the gate line (GL) intersect, and includes a thin film transistor (TR), a liquid crystal capacitor (Clc), and a storage capacitor (Cst) that act as switching elements within the sub-pixel (SP).

In the present invention, a gate driving circuit (130) that supplies a scan signal to a gate line (GL) is arranged between sub-pixels of a display panel (110) to reduce or eliminate a non-display area, thereby implementing a narrow bezel. In particular, in the present invention, a plurality of gate driving units constituting the gate driving circuit (130) are arranged between sub-pixel rows of a display area, thereby improving the problem of an increase in the non-display area due to a conventional GIP (Gate In Panel) structure.

In this way, the present invention has the effect of securing the maximum display area for displaying an image by arranging the driving circuit of the display panel in the display area.

The present invention has the effect of minimizing the non-display area of the display panel to implement a narrow bezel.

The present invention has the effect of improving the output reliability of a scan signal by preventing the Q node of a gate drive unit from floating throughout the entire section in which a scan signal is output.

The present invention has the effect of enabling image display and touch operation by preventing the Q node of the gate driving unit from being in a floating state.

Fig. 4 is a block diagram showing a schematic configuration of a display panel according to embodiments of the present invention. Fig. 5 is a drawing showing a structure in which a gate driver is arranged in a display area of a display panel according to the first embodiment of the present invention. Fig. 6 is a waveform diagram for explaining a process in which a scan signal is generated from a gate driver according to the embodiment of Fig. 5.

Referring to FIG. 4 together with FIG. 1, the display device (100) of the present invention includes a display panel (110), a gate driving circuit (130), and a data driving circuit (120). In addition, unlike the conventional display panel (110) in which the gate driving circuit (130) is disposed in the non-display area, the display device (100) of the present invention has the gate driving circuit (130) disposed in the display area, so that a separate non-display area is not distinguished. That is, the gate driving circuit (GIP structure) disposed in the non-display area of the conventional display panel (110) is disposed by dividing it into each gate line (G(1), G(2), ..., G(n)) area (n is a positive integer).

The gate driving circuit (130) of the present invention includes a plurality of gate driving units (GDPs) that supply scan signals to each gate line (GL), and these driving units (GDPs) are arranged to correspond to each of the gate lines (G(1), G(2), ..., G(n)). Therefore, when the number of gate lines (G(1), G(2), ..., G(n)) is n, the number of gate driving units (GDPs) can also be n.

Each gate driving unit (GDP) is again composed of a plurality of gate drivers (131), and the plurality of gate drivers (131) arranged in each gate driving unit (GDP) generate the same scan signal. That is, the gate drivers (131) constituting the gate driving unit (GDP) generate the same scan signal that is supplied to the gate line (GL) corresponding to the gate driving unit (GDP).

As illustrated in FIG. 4, a gate driving unit (GDP) is arranged on each of the gate lines (G(1), G(2), ..., G(n)), and a plurality of gate drivers (131) constituting each gate driving unit (GDP) are each connected to a gate line (GL) corresponding to the gate driving unit (GDP).

Accordingly, one gate driving unit (GDP) corresponds to one gate line (GL), and a plurality of gate drivers (131) arranged in the gate driving unit (GDP) supply the same scan signal to one gate line (GL) corresponding to the gate driving unit (GDP). For example, the nth gate driving unit (GDP) is arranged in the nth gate line (G(n)) of the present invention, and the gate drivers (131) arranged in the nth gate driving unit (GDP) supply the nth scan signal to the nth gate line (G(n).

In addition, it is preferable that at least one gate driver (131) be disposed in the gate driving unit (GDP) of the present invention. This is because as the display panel (110) becomes larger, the length of the gate line (GL) also increases, causing a delay in the supplied scan signal. For example, if the gate driver (131) disposed in the gate driving unit (GDP) is disposed only at one edge of the gate line (GL), a signal delay occurs when the scan signal is supplied to the other edge area of the gate line (GL). In addition, if the gate driver (131) is disposed only at the center area of the gate line (GL), a signal delay may occur when the scan signal is supplied to the edge areas of both sides of the gate line (GL).

Therefore, it is preferable that the gate drivers (131) arranged in the gate driving unit (GDP) of the present invention are arranged in multiple numbers at a predetermined interval along the gate line (GL). However, if the number of gate drivers (131) is too large, a problem occurs in which the area of the non-display area within the display area increases. Considering this point, in the present invention, it is preferable that the number of gate drivers (131) is arranged in a range in which a delay of the scan signal does not occur, and it is preferable that the number of gate drivers (131) arranged per arbitrary unit area of the display panel (110) is the same so that a uniform load can appear over the entire area of the display panel (110).

As illustrated in the drawing, a separate non-display area is not defined in the display panel (110) of the present invention. Although the area where a plurality of gate lines (G(1), G(2), ..., G(n)) are arranged is not illustrated in the drawing, the area where the data lines (DL) intersect and the gate lines (GL) and the data lines (DL) intersect corresponds to the display area where a plurality of sub-pixels are arranged. Therefore, the display device (100) of the present invention can eliminate or minimize the non-display area where the gate driver is arranged in the conventional GIP structure, thereby increasing the area of the display area. In this way, when the non-display area is eliminated or reduced in the display panel (110), the bezel area can be reduced, thereby implementing a narrow bezel.

Referring to FIG. 5 and FIG. 6 together with FIG. 1, the structure of sub-pixels (SP) arranged on the display panel (110) of the present invention is as follows.

The display panel (110) of the present invention has a plurality of sub-pixels (SP) arranged along rows and columns. A plurality of gate lines (G(n-1), G(n), G(n+1), G(n+2)) are arranged in a first direction, and a plurality of data lines (D1, D2, ..., D12) and a plurality of signal lines are arranged in a second direction to define a sub-pixel (SP). In the present invention, one data line (D1, D2, ..., D12) is arranged in each column of a pair of sub-pixels arranged in the display panel (110), and a plurality of data lines (D1, D2, ..., D12) are arranged on both sides of the pair of sub-pixels to supply a data voltage to the pair of sub-pixels.

In addition, a plurality of gate lines (G(n-1), G(n), G(n+1), G(n+2)) are arranged one by one for each row of sub-pixels arranged on the display panel (110) and supply scan signals to the sub-pixels arranged in each row of sub-pixels.

The display panel (110) of the present invention has a gate driving circuit (130) that supplies scan signals to a plurality of gate lines (G(n-1), G(n), G(n+1), G(n+2)) arranged in a display area where sub-pixels (SP) are arranged. A plurality of gate driving units (GDPs) constituting the gate driving circuit (130) are arranged one for each gate line.

In addition, in the present invention, a plurality of signals are supplied so that the gate driver (GDP) can generate a scan signal, and these plurality of signals are supplied through a plurality of signal lines arranged in parallel with the data lines (D1, D2, ..., D12) (arranged in the second direction). The plurality of signal lines include carry signal lines (Carry1, Carry2, ...) that supply carry signals related to the initial operation of the gate drivers (131) arranged in the gate driver (GDP), clock signal lines (CLKA, CLKB, ...) that supply clock signals (CLKA, CLKB) of different phases, gate low voltage lines (VGL1, VGL2, ...) that are supplied to maintain a low voltage in the gate line (GL) or to maintain the Q node of the gate driver (131) at a low voltage, and common voltage lines (VCOM1, VCOM2, ...) that supply a common voltage to each sub-pixel (SP).

The signal lines of the present invention can be arranged between data lines (DL) arranged on both sides of a pair of sub-pixels, respectively, along the row direction. In addition, the signal lines can be arranged between a pair of consecutive sub-pixels. As illustrated in the drawing, the data lines (D1, D2, ..., D12) are arranged in units of a pair of sub-pixels (SP) along the row direction, and each of the plurality of signal lines is arranged alternately with the data lines (D1, D2, ..., D12) and arranged between a pair of sub-pixels defined by two data lines. The plurality of signal lines can be composed of carry signal lines (Carry1, Carry2, ...), clock signal lines (CLKA, CLKB, ...), gate low voltage lines (VGL1, VGL2, ...), and common voltage lines (VCOM1, VCOM2, ...), and it is preferable that these are arranged alternately with the data lines (D1, D2, ..., D12) in units of each sub-pixel column along the row direction.

Each gate driver (131) constituting the gate driving unit (GDP) of the present invention corresponds to a predetermined number of sub-pixel column units arranged in the sub-pixel row of the corresponding gate line (GL). More specifically, referring to FIG. 5, the gate driver (131) of the gate driving unit (GDP) includes first to fourth switching elements (T1, T2, T3, T4). For example, the nth gate driving unit (GDP) is arranged in the nth gate line (GL(n)), and the gate driver (131) of the nth gate driving unit (GDP) is composed of first to fourth switching elements (T1, T2, T3, T4).

That is, one gate driver (131) arranged in the gate driving unit (GDP) of the present invention is implemented with four transistors. As illustrated in the drawing, the gate driver (131) arranged first in the nth gate driving unit (GDP) has a width of an area corresponding to the first to twelfth data lines (D1, D2, ..., D12). In other words, one gate driver (131) configures a circuit in which the first to fourth switching elements (T1, T2, T3, T4) are connected to each other within an area corresponding to 22 sub-pixels (SP) consecutively arranged in the first direction to generate a scan signal.

The gate driver (131) uses the gate terminal of the second switching element (T2) as a Q node, and the Q node is commonly connected to the drain terminal of the first switching element (T1) and the drain terminal of the third switching element (T3). More specifically, the gate terminal and the source terminal of the first switching element (T1) are commonly connected to the previous ((n-1)th) gate line, and the drain terminal is connected to the gate terminal (Q node) of the second switching element (T2).

The gate terminal of the second switching element (T2) is commonly connected to the Q node, the drain terminal of the first switching element (T1) and the drain terminal of the third switching element (T3), the source terminal is connected to the first clock signal line (CLKA), and the drain terminal is connected to the current ((n)th) gate line (GL(n)).

The gate terminal of the third switching element (T3) is commonly connected to the gate terminal of the fourth switching element (T4) and the (n+2)th gate line (GL(n+2)), the source terminal is connected to the first gate low voltage line (VGL1), and the drain terminal is connected to the Q node.

The gate terminal of the fourth switching element (T4) is commonly connected to the gate terminal of the third switching element (T3) and the (n+2)th gate line (GL(n+2)), the source terminal is connected to the second gate low voltage line (VGL2), and the drain terminal is connected to the current ((n)th) gate line (GL(n)).

The driving method of the gate driver (131) of the present invention is described as follows with reference to FIG. 6.

The gate driver (131) arranged in the nth gate driving unit (GDP) is first turned on by supplying a carry signal from the previous ((n-1)th) gate line (G(n-1)) to the first switching element (T1). At this time, the carry signal is a scan signal of the previous ((n-1)th) gate line (G(n-1)). If it is the gate driver (131) of the first gate driving unit (GDP), the previous gate line (GL) does not exist, so the gate driver can be turned on by supplying a carry signal from the carry signal line.

In this way, when the first switching element (T1) is turned on, the voltage level of the Q node rises to a high level by the scan signal of the previous ((n-1)th) gate line (G(n-1)). As the Q node voltage level rises to a high level, the first switching element (T1) is turned on.

When the voltage level of the Q node rises due to the scan signal, the voltage level of the scan signal supplied to the first switching element (T1) from the previous ((n-1)th) gate line (G(n-1)) becomes a low level, and the first switching element (T1) is turned off. At this time, the first clock signal (CLKA) is supplied from the clock signal line connected to the source terminal of the second switching element (T2). When the source terminal of the second switching element (T2) rises from a low voltage level to a high voltage level corresponding to the clock signal (CLKA), the voltage level of the Q node additionally rises due to the bootstrap effect, and the first clock signal (CLKA) is supplied to the current ((n)th) gate line (G(n)) in the form of a scan signal.

Therefore, when the Q node is at a high level, the gate driver (131) pulls up the first clock signal (CLKA) to the current ((n)th) gate line (G(n)) to supply a scan signal.

Then, in a section where both the first and second clock signals (CLKA, CLKB) are at low levels, the voltage of the Q node maintains a high level with a slightly lowered voltage level, and since the first clock signal (CLKA) is at a low level, the first clock signal (CLKA) at a low level is supplied to the current ((n)th) gate line (G(n)). At this time, the gate terminals of the third and fourth switching elements (T3, T4) receive a scan signal from the commonly connected (n+2)th gate line (G(n+2)) and are turned on. That is, in response to the scan signal of the (n+2)th gate line (G(n+2)), the third and fourth switching elements (T3, T4) are turned on, and a gate low voltage is supplied to the Q node from the first gate low voltage line (VGL1).

In addition, the current ((n)th) gate line (G(n)) is supplied with a gate low voltage from the second gate low voltage line (VGL2). Therefore, as shown in the drawing, when the Q node falls to a low level and the first and second clock signals (CLKA, CLKB) are in a low state, the gate low voltage is supplied to the current ((n)th) gate line (G(n)).

In the subsequent section, since the (n-1)th gate line (G(n-1)) is at a low level, the first switching element (T1) is maintained in a turn-off state, and since the (n+2)th gate line (G(n+2)) is also at a low level, the third and fourth switching elements (T3, T4) are turned off.

That is, the Q node is in a floating state, not electrically connected to other switching elements and signal lines, and the current ((n)th) gate line (G(n)) is also in a floating state because the 4th switching element (T4) is turned off, so that the previously supplied signal is maintained.

In this way, the conventional gate driver (called a shift register or stage) required a control circuit composed of many switching elements to control the voltages of the Q node and the QB node, and an output section to pull up or pull down clock signals and supply them to the gate line (GL), but in the present invention, the gate driver is implemented with four switching elements, and the occupied area of the gate driver can be reduced.

In this way, the present invention has the effect of securing the maximum display area for displaying an image by arranging the driving circuit of the display panel in the display area.

The present invention has the effect of minimizing the non-display area of the display panel to implement a narrow bezel.

FIG. 7 is a block diagram showing a schematic configuration of a display panel according to other embodiments of the present invention.

Fig. 7 is about another embodiment of the arrangement structure of the gate driving circuit of Fig. 4, and will be described below with a focus on parts that are different from Fig. 4.

Referring to FIG. 7 together with FIG. 1, the gate driving circuit (130) of the present invention includes a plurality of gate driving units (GDPs) that supply scan signals to each gate line (GL) and a blank region (132). Therefore, one gate driving unit (GDP) includes a plurality of gate drivers (131) and a plurality of blank regions (132). The gate driving units (GDPs) are arranged to correspond to each of the gate lines (G(1), G(2), ... , G(n)). Therefore, when the number of gate lines (G(1), G(2), ... , G(n)) is n, the number of gate driving units (GDPs) can also be n.

In particular, in Fig. 7, unlike Fig. 4, the gate drivers (131) constituting the gate driving unit (GDP) are not arranged sequentially in units of a certain number of consecutive sub-pixels, but the gate drivers (131) and blank areas (132) are arranged alternately. Therefore, the number of gate drivers (131) arranged to correspond to each gate line (G(n)) is reduced compared to Fig. 4.

For example, the gate drivers of the Nth gate driving unit (GDP) corresponding to the Nth gate line are arranged with a spacing of a certain number of consecutive sub-pixel rows corresponding to the gate drivers (131). A blank area (BA: 132) is arranged between the gate drivers (131), and the occupied area of the blank area (BA: 132) may be the same as that of the gate driver (131). In addition, the gate drivers (131) of the gate driving unit corresponding to the (N+1)th gate line (G(n+1)) are arranged so as not to overlap with the gate drivers arranged to correspond to the Nth gate line (G(n)) in the vertical direction (second direction or data line direction).

More specifically, referring to FIG. 7, the gate driver (131) and the blank area (132) are alternately arranged in the gate driving unit (GDP) of the first gate line (G(1)), and the gate driver (131) of the gate driving unit (GDP) of the second gate line (G(2)) does not overlap with the gate driver of the first gate line (G(1)). Similarly, the gate drivers (131) corresponding to the third gate line (GL(3)) do not overlap with the gate drivers (131) corresponding to the second gate line (GL(2)). Although it was previously stated that the gate drivers arranged in the adjacent gate driving units (GDPs) centered on the gate driver (131) do not overlap with each other, the blank areas (132) also do not overlap with each other in the same manner.

In this way, in the present invention, a blank area (132) can be arranged to reduce the number of gate drivers (131) arranged in each gate driving unit (GDP). Accordingly, in the embodiment of FIG. 4, if 10 gate drivers (131) are arranged in one gate driving unit (GDP), in the embodiment of FIG. 7, 5 gate drivers (131) are arranged in one gate driving unit (GDP).

Fig. 7 illustrates another embodiment, and in some cases, the number of blank areas between the gate drivers may be arranged to be at least one or more. The number of gate drivers arranged in the gate driving unit (GDP) may be adjusted in various ways, taking into account the overall load uniformity of the display panel (110).

A separate non-display area is not defined in the display panel (110) of the present invention. Although the area where a plurality of gate lines (G(1), G(2), ..., G(n)) are arranged is not shown in the drawing, the area where the data lines (DL) intersect and the gate lines (GL) and the data lines (DL) intersect corresponds to the display area where a plurality of sub-pixels are arranged.

Accordingly, the display device (100) of the present invention can eliminate or minimize the non-display area where the gate driver is arranged in the conventional GIP structure, thereby increasing the area of the display area. In this way, when the non-display area is eliminated or reduced within the display panel (110), the bezel area can be reduced, thereby implementing a narrow bezel.

FIG. 8 is a drawing illustrating a structure in which a gate driver is arranged in a display area of a display panel according to a second embodiment of the present invention. FIG. 9 is a waveform diagram for explaining a process in which a scan signal is generated from a gate driver according to the embodiment of FIG. 8.

FIGS. 8 and 9 relate to other embodiments of FIGS. 5 and 6, and the following description focuses on parts that are different from FIGS. 5 and 6.

Referring to FIGS. 8 and 9 along with FIG. 1, the structure of sub-pixels (SP) arranged on the display panel (110) of the present invention is as follows.

The gate driving unit (GDP) disposed on the display panel (110) of the present invention includes a plurality of gate drivers (231). The gate drivers (231) include first to fourth switching elements (T1, T2, T3, T4).

The gate driver (231) uses the gate terminal of the second switching element (T2) as a Q node, and the Q node is commonly connected to the drain terminal of the first switching element (T1) and the drain terminal of the third switching element (T3). More specifically, the gate terminal and the source terminal of the first switching element (T1) are commonly connected to the previous ((n-1)th) gate line, and the drain terminal is connected to the gate terminal (Q node) of the second switching element (T2).

The gate terminal of the second switching element (T2) is commonly connected to the Q node, the drain terminal of the first switching element (T1) and the drain terminal of the third switching element (T3), the source terminal is connected to the first clock signal line (CLKA), and the drain terminal is connected to the current ((n)th) gate line (GL(n)).

The gate terminal of the third switching element (T3) is commonly connected to the gate terminal of the fourth switching element (T4) and the (n+2)th gate line (GL(n+2)), the source terminal is connected to the first gate low voltage line (VGL1), and the drain terminal is connected to the Q node.

The gate terminal of the fourth switching element (T4) is connected to the second clock signal line (CLKB), the source terminal is connected to the second gate low voltage line (VGL2), and the drain terminal is connected to the current ((n)th) gate line (GL(n)).

The driving method of the gate driver (131) of the present invention is described as follows with reference to FIG. 9.

The gate driver (131) arranged in the nth gate driving unit (GDP) is first turned on by supplying a carry signal from the previous ((n-1)th) gate line (G(n)) to the first switching element (T1). At this time, the carry signal is a scan signal of the previous ((n-1)th) gate line (G(n-1)). If it is the gate driver (131) of the first gate driving unit (GDP), the previous gate line (GL) does not exist, so the gate driver can be turned on by supplying a carry signal from the carry signal line.

In this way, when the first switching element (T1) is turned on, the voltage level of the Q node rises to a high level by the scan signal of the previous ((n-1)th) gate line (G(n-1)). As the Q node voltage level rises to a high level, the first switching element (T1) is turned on.

When the voltage level of the Q node rises due to the scan signal, the voltage level of the scan signal supplied to the first switching element (T1) from the previous ((n-1)th) gate line (G(n-1)) becomes a low level, and the first switching element (T1) is turned off. At this time, the first clock signal (CLKA) is supplied from the clock signal line connected to the source terminal of the second switching element (T2). When the source terminal of the second switching element (T2) rises from a low voltage level to a high voltage level corresponding to the clock signal (CLKA), the voltage level of the Q node additionally rises due to the bootstrap effect, and the first clock signal (CLKA) is supplied to the current ((n)th) gate line (G(n)) in the form of a scan signal.

Therefore, when the Q node is at a high level, the gate driver (131) pulls up the first clock signal (CLKA) to the current ((n)th) gate line (G(n)) to supply a scan signal.

Then, in a section where both the first and second clock signals (CLKA, CLKB) are at low levels, the voltage of the Q node maintains a high level with a slightly lowered voltage level, and since the first clock signal (CLKA) is at a low level, the first clock signal (CLKA) at a low level is supplied to the current ((n)th) gate line (G(n)). At this time, since the gate terminal of the third switching element (T3) is connected to the (n+2)th gate line (G(n+2)) and the gate terminal of the fourth switching element (T4) is connected to the second clock signal line (CLKB), both the third and fourth switching elements (T3, T4) are turned on. That is, the third switching element (T3) responds to the scan signal of the (n+2)th gate line (G(n+2)), and the fourth switching element (T4) is turned on in response to the second clock signal (CLKB).

Therefore, in a section where the scan signal of the (n+2)th gate line (G(n+2)) is supplied to the third switching element (T3), the Q node is brought to a low level state by the gate low voltage supplied from the first gate low voltage line (VGL1). In addition, in a section where the second clock signal (CLKB) is supplied to the fourth switching element (T4), the gate low voltage supplied from the second gate low voltage line (VGL2) is supplied to the current ((n)th) gate line (G(n)).

In the subsequent section, since the (n-1)th gate line (G(n-1)) of the previous section is at a low level, the first switching element (T1) is maintained in a turned-off state, and since the (n+2)th gate line (G(n+2)) is also at a low level, the third switching element (T3) is turned off. In addition, since the second clock signal (CLKB) is at a low level, the fourth switching element (T4) is also turned off.

That is, the Q node is in a floating state, not electrically connected to other switching elements and signal lines, and the current ((n)th) gate line (G(n)) is also in a floating state because the 4th switching element (T4) is turned off, so that the previously supplied signal is maintained.

As illustrated in FIG. 9, in section A of the subsequent section in which a scan signal is output from the current ((n)th) gate line (G(n)), the Q node and the current ((n)th) gate line (G(n)) are in a floating state, and in section B in which the second clock signal (CLKB) is at a high level, the current ((n)th) gate line (G(n)) is supplied with a gate low voltage.

That is, the source terminal and the gate terminal of the first switching element (T1) are connected to the (n-1)th gate line (G(n-1)), and the (n-1)th gate line (G(n-1)) is in a low level state but is connected together with the gate terminal, so it is turned off. In addition, since the gate terminal of the third switching element (T3) is connected to the (n+2)th gate line (G(n+2)), the third switching element (T3) is turned off in section A.

In this way, the conventional gate driver (called a shift register or stage) required a control circuit composed of many switching elements to control the voltages of the Q node and the QB node, and an output section to pull up or pull down clock signals and supply them to the gate line (GL), but in the present invention, the gate driver is implemented with four switching elements, and the occupied area of the gate driver can be reduced.

In this way, the present invention has the effect of securing the maximum display area for displaying an image by arranging the driving circuit of the display panel in the display area.

The present invention has the effect of minimizing the non-display area of the display panel to implement a narrow bezel.

FIG. 10 is a diagram illustrating a structure in which a gate driver is arranged in a display area of a display panel according to a third embodiment of the present invention. FIG. 11 is a waveform diagram for explaining a process in which a scan signal is generated from a gate driver according to the embodiment of FIG. 10. FIGS. 12a to 15b are diagrams for explaining a process in which a scan signal is generated from a gate driver and then supplied to a gate line according to the third embodiment of the present invention. In addition, FIGS. 12a to 15b illustrate circuit operations corresponding to hatched areas of signal waveforms.

FIGS. 10 to 15b are modified embodiments of the first and second embodiments of the present invention, and will be described below with a focus on distinguishable parts.

Referring to FIGS. 10 to 15b together with FIG. 1, the gate driver (GDP) of the present invention is connected to a plurality of signal lines to which a plurality of signals are supplied so as to generate a scan signal. The plurality of signals are arranged in parallel with the data lines (D1, D2, ..., D12) (arranged in the second direction, and include carry signal lines (Carry1, Carry2, ...) that supply carry signals for the initial operation of the gate drivers (331), clock signal lines (CLKA, CLKB, ...) that supply clock signals (CLKA, CLKB) of different phases, gate low voltage lines (VGL1, VGL2, ...) that are supplied to maintain a low voltage on the gate line (GL) or to maintain the Q node of the gate driver (131) at a low voltage, and common voltage lines (VCOM1, VCOM2, ...) that supply a common voltage to each sub-pixel (SP).

The gate driver (331) of the gate driving unit (GDP) of the present invention includes first to fourth switching elements (NT1, NT2, NT3, PT). In particular, in the third embodiment of the present invention, unlike the first and second embodiments, the first to third switching elements (NT1, NT2, NT3) may be configured as N-MOS transistors, and the fourth switching element (PT) may be configured as a P-MOS transistor. Accordingly, the gate driver (331) of the third embodiment of the present invention may be implemented as a CMOS transistor.

The gate driver (331) uses the gate terminal of the second switching element (NT2) as a Q node, and the Q node is commonly connected to the drain terminal of the first switching element (NT1), the drain terminal of the third switching element (NT3), and the gate terminal of the fourth switching element (PT). More specifically, the gate terminal and the source terminal of the first switching element (NT1) are commonly connected to the previous ((n-1)th) gate line, and the drain terminal is commonly connected to the gate terminals (Q nodes) of the second and fourth switching elements (NT2, PT) and the drain terminal of the third switching element (NT3).

The gate terminal of the second switching element (NT2) is commonly connected to the Q node, the drain terminal of the first switching element (NT1), the drain terminal of the third switching element (NT3), and the gate terminal of the fourth switching element (PT), the source terminal is connected to the first clock signal line (CLKA), and the drain terminal is connected to the current ((n)th) gate line (GL(n)).

The gate terminal of the fourth switching element (PT) is connected to the Q node, the source terminal is connected to the first gate low voltage line (VGL1), and the drain terminal is connected to the current ((n)th) gate line (GL(n)).

The gate terminal of the third switching element (NT3) is connected to the second clock signal line (CLKB), the source terminal is connected to the second gate low voltage line (VGL2), and the drain terminal is connected to the Q node.

The driving method of the gate driver (331) of the present invention is described as follows with reference to FIGS. 9 to 15b.

The gate driver (331) arranged in the nth gate driving unit (GDP) is first turned on by supplying a carry signal from the previous ((n-1)th) gate line (G(n-1)) to the first switching element (NT1). At this time, the carry signal is a scan signal of the previous ((n-1)th) gate line (G(n-1)). If it is the gate driver (331) of the first gate driving unit (GDP), the previous gate line (GL) does not exist, so the gate driver can be turned on by supplying a carry signal from the carry signal line.

In this way, when the first switching element (NT1) is turned on, the voltage level of the Q node rises to a high level by the scan signal of the previous ((n-1)th) gate line (G(n-1)). As the Q node voltage level rises to a high level, the second switching element (NT2) is turned on and the fourth switching element (PT), which is a P-MOS transistor, is turned off. That is, as illustrated in FIG. 12a, when the Q node voltage becomes a high level, the voltages of the drain terminal of the first switching element (NT1), the gate terminal of the second switching element (NT2), the drain terminal of the third switching element (NT3), and the gate terminal of the fourth switching element (PT) become high levels.

Accordingly, the first switching element (NT1) is turned on, the second switching element (NT2) is turned on, and the third and fourth switching elements (NT3, PT) are turned off.

Referring to FIGS. 13a and 13b, when the voltage level of the Q node rises due to the scan signal, the voltage level of the scan signal supplied to the first switching element (NT1) from the previous ((n-1)th) gate line (G(n-1)) becomes a low level, and the first switching element (NT1) is turned off. However, the second switching element (NT2) maintains a turn-on state because the Q node maintains a high voltage. Since the Q node maintains a high voltage, the fourth switching element (PT), which is a P-MOS transistor, maintains a turn-off state, and since the second clock signal (CLKB) is in a low state, the third switching element (NT3) is maintained in a turn-off state.

At this time, a first clock signal (CLKA) is supplied from a clock signal line connected to the source terminal of the second switching element (NT2). When the source terminal of the second switching element (NT2) rises from a low voltage level to a high voltage level corresponding to the first clock signal (CLKA), the voltage level of the Q node additionally rises due to the bootstrap effect, and the first clock signal (CLKA) is output in the form of a scan signal to the current ((n)th) gate line (G(n)).

In a section where both the first and second clock signals (CLKA, CLKB) are at low levels, the voltage of the Q node maintains a high level with a slightly lowered voltage level, and since the first clock signal (CLKA) is at a low level, the first clock signal (CLKA) at a low level is supplied to the current ((n)th) gate line (G(n)). At this time, since the Q node is at a high level, the fourth switching element (PT) maintains a turn-off state, and since the second clock signal (CLKB) is at a low level, the third switching element (NT3) also turns off. That is, since the Q node maintains a high level state, the second switching element (NT2) maintains a turn-on state and supplies the low level voltage of the first clock signal to the current ((n)th) gate line (G(n)).

Thereafter, referring to FIGS. 14a to 15b, the scan signal of the previous ((n-1)th) gate line (G(n-1)) is in a low state and the third switching element (NT3) is turned on in response to the high state of the second clock signal (CLKB). At this time, since the Q node is discharged to the second gate low voltage and becomes a low level voltage, the first and second switching elements (NT1, NT2) are turned off and the fourth switching element (PT) is turned on. When the gate low voltage is supplied to the Q node, the fourth switching element (PT), which is a P-MOS transistor, responds to the turn-on and supplies the gate low voltage to the current ((n)th) gate line (G(n)) through the first gate low voltage line (VGL1).

In the subsequent section, since the scan signal of the previous ((n-1)th) gate line (G(n-1)) is at a low level, the first switching element (NT1) is maintained in a turn-off state, but the Q node is discharged after the second clock signal (CLKB) is supplied, so that the voltage at a low level is maintained. In the state where the Q node is discharged, the second switching element (NT2) is turned off, but the fourth switching element (PT) is turned on so that the gate low voltage can be continuously supplied to the current ((n)th) gate line (G(n)) through the first gate low voltage line (VGL1).

That is, in the third embodiment of the present invention, the gate low voltage supplied to the current ((n)th) gate line (G(n)) can be maintained by the operation of the fourth switching element (PT), which is a P-MOS transistor, even when the Q node is in a discharge state.

Accordingly, while the first and second embodiments of the present invention maintain the previously supplied gate low voltage to the current ((n)th) gate line (G(n)) while the Q node is in a floating state, the third embodiment of the present invention has an advantage in that the reliability of the scan signal can be increased because the Q node and the current ((n)th) gate line (G(n)) are maintained by being supplied with the gate low voltage.

In particular, an in-cell touch display device in which a touch sensor is arranged within a display panel is divided into an area for displaying an image and a touch sensing area (AIT driving area) for performing touch sensing. When performing touch sensing, a LFD (Load Free Drive) signal, such as a square wave, is applied to a plurality of gate lines (GL), a plurality of data lines (DL), and a common electrode (Vcom).

Therefore, when the gate lines are maintained at the gate low voltage as in the third embodiment of the present invention, operation in the touch sensing section is possible, and the touch sensitivity can be prevented from being reduced due to signal distortion by the signals.

In this way, the present invention has the effect of securing the maximum display area for displaying an image by arranging the driving circuit of the display panel in the display area.

The present invention has the effect of minimizing the non-display area of the display panel to implement a narrow bezel.

The present invention has the effect of improving the output reliability of a scan signal by preventing the Q node of a gate drive unit from floating throughout the entire section in which a scan signal is output.

The present invention has the effect of enabling image display and touch operation by preventing the Q node of the gate driving unit from being in a floating state.

Figure 16 is a flowchart for explaining a method of driving a display device according to embodiments of the present invention.

Referring to FIG. 16, the display device driving method of the present invention includes a step (S1601) of supplying a scan signal from a previous ((n-1)th) gate line (G(n-1)) among gate lines (GL) to a gate driver arranged in a display area of a display panel; a step (S1602) of increasing a voltage level of a Q node according to an operation of a first switching element of the gate driver; a step (S1603) of supplying a first clock signal to the current ((n)th) gate line (G(n)) by driving a second switching element in response to the increased Q node voltage to output a scan signal; a step (S1604) of lowering the Q node voltage level by driving a third switching element in response to the second clock signal; and a step (S1605) of supplying and maintaining a gate low voltage to the current ((n)th) gate line (G(n)) by driving a fourth switching element by the lowered Q node voltage.

More specifically, referring to FIGS. 10 to 15B, a method for driving a display device of the present invention includes, in a display device including a display panel having a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels arranged along rows and columns, the step of supplying a scan signal from a previous (n-1th) gate line among the plurality of gate lines to a gate driver arranged in a display area of the display panel; a step of increasing a voltage level of a Q node of the gate driver by the supplied scan signal; a step of outputting a first clock signal as a scan signal to a current (nth) gate line in response to the increased Q node voltage; a step of lowering the Q node of the gate driver to a gate low voltage in response to a second clock signal; and a step of supplying and maintaining a gate low voltage to the current (nth) gate line in response to the Q node voltage whose voltage level has been lowered.

Here, the switching elements arranged in the gate driver are composed of three N-MOS transistors and one P-mode transistor. Therefore, the gate driver can be implemented with a CMOS transistor. Specifically, the gate driver (331) includes first to third switching elements (NT1, NT2, NT3) composed of N-mode transistors and a fourth switching element (PT) composed of a P-MOS transistor.

In this way, the gate driver (331) is arranged in a conventional shift register or gate driving circuit that supplies a clock signal to a gate line, including a Q node, and functions as a stage for generating a gate signal (scan signal). Therefore, the present invention has an advantage in that it can reduce the load on the display panel due to the gate driver (331) because it is implemented with fewer transistors than the transistors that constitute a conventional shift register or stage.

The gate driver (331) includes a first switching element (NT1) whose gate terminal and source terminal are connected to the previous (n-1th) gate line, and whose drain terminal is connected to the Q node, a second switching element (NT2) whose gate terminal is connected to the Q node, whose source terminal is connected to a clock signal line, and whose drain terminal is connected to the current (nth) gate line, a third switching element (NT3) whose gate terminal is connected to a clock signal line different from the clock signal line connected to the second switching element (NT2), whose source terminal is connected to a gate low voltage line, and whose drain terminal is connected to the Q node, and a fourth switching element (PT) whose gate terminal is connected to the Q node, whose source terminal is connected to a gate low voltage line, and whose drain terminal is connected to the current (nth) gate line.

Additionally, the first switching element (NT1) is turned on in response to a scan signal supplied from the previous (n-1th) gate line to raise the Q node to the voltage level of the supplied scan signal, and the second switching element (NT2) is turned on in response to the raised Q node to output the first clock signal as a scan signal to the current (nth) gate line.

The third switching element (NT3) is turned on in response to the second clock signal to supply a gate low voltage to the Q node, and as the Q node voltage drops to the gate low voltage, the fourth switching element (PT) is turned on, and the fourth switching element (PT) supplies a gate low voltage to the current (nth) gate line in response to the turn-on.

In this way, the present invention has the effect of securing the maximum display area for displaying an image by arranging the driving circuit of the display panel in the display area.

The present invention has the effect of minimizing the non-display area of the display panel to implement a narrow bezel.

The present invention has the effect of improving the output reliability of a scan signal by preventing the Q node of a gate drive unit from floating throughout the entire section in which a scan signal is output.

The present invention has the effect of enabling image display and touch operation by preventing the Q node of the gate driving unit from being in a floating state.

An exemplary embodiment of the present invention can be described as follows.

A display device according to one embodiment of the present invention may include a display panel having a display area in which a plurality of sub-pixels are arranged along rows and columns, a plurality of data lines, one for each column of a pair of sub-pixels arranged in the display area and supplying data voltages to sub-pixels arranged in both sub-pixel columns, a plurality of gate lines, one for each row of the sub-pixels arranged in the display area and supplying scan signals to the sub-pixels arranged in the row of each sub-pixel, a plurality of gate drivers, one for each gate line arranged in the display area and generating scan signals supplied by each gate line to the sub-pixels, and a plurality of signal lines, alternately arranged with the plurality of data lines for each sub-pixel column and supplying signals for operation of the gate drivers.

According to another embodiment of the present invention, a display device includes a gate driving unit composed of a plurality of gate drivers, and each gate driver is arranged in a display area to correspond to a predetermined number of consecutive sub-pixel columns and can supply a scan signal to a corresponding gate line.

According to another embodiment of the present invention, a display device comprises gate drivers constituting a gate driving unit capable of supplying the same scan signal to a gate line corresponding to the gate driving unit.

A display device according to another embodiment of the present invention may include a plurality of signal lines including at least one carry signal line related to an initial operation of a gate driver, at least one clock signal line supplying clock signals of different phases, and at least one gate low voltage line.

According to another embodiment of the present invention, a display device may include a gate driver including first to third switching elements composed of N-MOS transistors and a fourth switching element composed of a P-MOS transistor.

According to another embodiment of the present invention, a display device includes a gate driver including a Q node, a first switching element having a gate terminal and a source terminal connected to a previous (n-1th) gate line, and a drain terminal connected to the Q node, a second switching element having a gate terminal connected to the Q node, a source terminal connected to a clock signal line, and a drain terminal connected to a current (nth) gate line, a third switching element having a gate terminal connected to a clock signal line different from the clock signal line connected to the second switching element, a source terminal connected to a gate low voltage line, and a drain terminal connected to the Q node, and a fourth switching element having a gate terminal connected to the Q node, a source terminal connected to a gate low voltage line, and a drain terminal connected to the current (nth) gate line.

According to another embodiment of the present invention, a display device is provided in which each gate driver of a gate driving unit arranged to correspond to each gate line can be arranged sequentially to correspond to a predetermined number of consecutive sub-pixel columns.

According to another embodiment of the present invention, a display device includes a gate driver including a plurality of gate drivers and a plurality of blank regions, wherein the gate drivers and blank regions of the gate driver corresponding to an n-th gate line among the plurality of gate lines are arranged alternately, and the gate drivers and blank regions of the gate driver corresponding to the (n+1)-th gate line can be arranged so as not to overlap vertically with the gate drivers and blank regions of the gate driver corresponding to the n-th gate line.

According to another embodiment of the present invention, a display device driving method may include a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels arranged along rows and columns, the display device comprising the steps of: supplying a scan signal from a previous (n-1) gate line among the plurality of gate lines to a gate driver arranged in a display area of the display panel; increasing a voltage level of a Q node of the gate driver by the supplied scan signal; outputting a first clock signal as a scan signal to a current (n-th) gate line in response to the increased Q node voltage; decreasing the Q node of the gate driver to a gate low voltage in response to a second clock signal; and supplying and maintaining the gate low voltage to the current (n-th) gate line in response to the Q node voltage whose voltage level has been decreased.

According to another embodiment of the present invention, a method for driving a display device includes a gate driver including first to third switching elements composed of N-MOS transistors and a fourth switching element composed of P-MOS transistors.

According to another embodiment of the present invention, a display device driving method comprises: a gate driver including a Q node; a first switching element has a gate terminal and a source terminal connected to a previous (n-1th) gate line, and a drain terminal connected to the Q node; a second switching element has a gate terminal connected to the Q node, a source terminal connected to a clock signal line, and a drain terminal connected to a current (nth) gate line; a third switching element has a gate terminal connected to a clock signal line different from the clock signal line connected to the second switching element, a source terminal connected to a gate low voltage line, and a drain terminal connected to the Q node; and a fourth switching element has a gate terminal connected to the Q node, a source terminal connected to a gate low voltage line, and a drain terminal connected to the current (nth) gate line.

According to another embodiment of the present invention, a method for driving a display device is provided in which a first switching element is turned on in response to a scan signal supplied from a previous (n-1th) gate line to raise the Q node to a voltage level of the supplied scan signal.

According to another embodiment of the present invention, a display device driving method can be provided in which the second switching element is turned on in response to a raised Q node to output a scan signal to the current (nth) gate line through a first clock signal.

According to another embodiment of the present invention, a display device driving method is provided in which a third switching element is turned on in response to a second clock signal to supply a gate low voltage to a Q node, and a fourth switching element is turned on as the Q node voltage drops to the gate low voltage.

According to another embodiment of the present invention, a method for driving a display device can supply a gate low voltage to a current (nth) gate line in response to the fourth switching element being turned on.

Although the embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical idea of the present invention. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are exemplary in all aspects and not restrictive. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

100: Display device
110: Display panel
120: Gate drive circuit
130: Data drive circuit
150: Controller
131, 231, 331: Gate Driver
132: Blank area
GDP: Gate Driver
SP: Subpixel

Claims (14)

A display panel having a display area in which a plurality of sub-pixels are arranged along rows and columns;
A plurality of data lines, one for each column of a pair of sub-pixels arranged in the above display area and supplying data voltages to the sub-pixels arranged in each of the sub-pixel columns on both sides;
A plurality of gate lines arranged one for each row of sub-pixels arranged in the above display area and supplying scan signals to the sub-pixels arranged in each row of sub-pixels;
A plurality of gate drivers arranged one for each gate line arranged in the above display area and generating scan signals that each gate line supplies to sub-pixels; and
It includes a plurality of signal lines arranged alternately with the plurality of data lines in each sub-pixel column unit and supplying signals for the operation of the gate driver,
The above gate driving unit is composed of a plurality of gate drivers, and each gate driver is arranged in the display area to correspond to a certain number of consecutive sub-pixel rows and supplies a scan signal to the corresponding gate line.
The above display panel further includes a plurality of blank areas,
The gate drivers and blank areas corresponding to the nth gate line among the above plurality of gate lines are arranged alternately,
A display device in which the gate drivers and blank areas corresponding to the n+1th gate line among the plurality of gate lines are arranged so as not to overlap with the gate drivers and blank areas corresponding to the nth gate line.
In the first paragraph,
A display device in which the gate drivers constituting the above gate driving unit supply the same scan signal to the gate line corresponding to the gate driving unit.
In the first paragraph,
A display device wherein the plurality of signal lines include at least one carry signal line related to the initial operation of the gate driver, at least one clock signal line supplying clock signals of different phases, and at least one gate low voltage line.
In the third paragraph,
A display device including the above gate driver including first to third switching elements composed of N-MOS transistors and a fourth switching element composed of P-MOS transistors.
In the fourth paragraph,
The above gate driver includes a Q node,
The above first switching element has a gate terminal and a source terminal connected to the previous (n-1th) gate line, and a drain terminal connected to the Q node.
The second switching element has a gate terminal connected to the Q node, a source terminal connected to the first clock signal line, and a drain terminal connected to the current (nth) gate line.
The third switching element is connected to the second clock signal line, the source terminal is connected to the gate low voltage line, and the drain terminal is connected to the Q node.
The above fourth switching element is a display device in which the gate terminal is connected to the Q node, the source terminal is connected to the gate low voltage line, and the drain terminal is connected to the current (n) gate line.
In the first paragraph,
A display device in which each gate driver of the gate driving unit arranged to correspond to each of the above gate lines is arranged continuously to correspond to a certain number of consecutive sub-pixel columns.
delete In a display device including a display panel having a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels arranged along rows and columns,
A step of supplying a scan signal to a gate driver arranged in a display area of the display panel from the previous (n-1th) gate line among the plurality of gate lines;
A step in which the voltage level of the Q node of the gate driver increases by the supplied scan signal;
A step of outputting a first clock signal as a scan signal to the current (nth) gate line in response to the above-mentioned increased Q node voltage;
A step in which the Q node of the above gate driver drops to a gate low voltage in response to a second clock signal;
The above voltage level comprises a step of supplying and maintaining a gate low voltage to the current (nth) gate line in response to the Q node voltage being lowered,
The above display panel further includes a plurality of blank areas,
The gate drivers and blank areas corresponding to the nth gate line among the above plurality of gate lines are arranged alternately,
A display device driving method wherein the gate drivers and blank areas corresponding to the n+1th gate line among the plurality of gate lines are arranged so as not to overlap with the gate drivers and blank areas corresponding to the nth gate line.
In Article 8,
A method for driving a display device, wherein the gate driver includes first to third switching elements composed of N-MOS transistors and a fourth switching element composed of P-MOS transistors.
In Article 9,
The above gate driver includes a Q node,
The above first switching element has a gate terminal and a source terminal connected to the previous (n-1th) gate line, and a drain terminal connected to the Q node.
The second switching element has a gate terminal connected to the Q node, a source terminal connected to the first clock signal line, and a drain terminal connected to the current (nth) gate line.
The third switching element has a gate terminal connected to a second clock signal line, a source terminal connected to a gate low voltage line, and a drain terminal connected to the Q node.
A method for driving a display device, wherein the fourth switching element has a gate terminal connected to the Q node, a source terminal connected to a gate low voltage line, and a drain terminal connected to the current (n) gate line.
In Article 10,
A display device driving method in which the first switching element is turned on in response to a scan signal supplied from a previous (n-1th) gate line to raise the Q node to the voltage level of the supplied scan signal.
In Article 10,
A display device driving method in which the second switching element is turned on in response to the above-mentioned increased Q node to output a scan signal to the current (nth) gate line by the first clock signal.
In Article 10,
A method for driving a display device, wherein the third switching element is turned on in response to a second clock signal to supply a gate low voltage to the Q node, and the fourth switching element is turned on as the Q node voltage drops to the gate low voltage.
In Article 13,
A display device driving method in which the fourth switching element supplies a gate low voltage to the current (nth) gate line in response to turn-on.

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