KR102730625B1 - SSD buffer management technique that minimizes performance degradation in situations where the battery is limited - Google Patents

Abstract

An embodiment of the present invention provides an SSD buffer management method for minimizing performance degradation in a battery-limited situation, the method comprising: a step in which a control unit of a DDS checks a user write request existing in a write buffer of the SSD within a certain time window in an SSD in which the amount of data on a buffer that the battery can write when power is cut off is limited to a maximum number of protected pages; a step in which the control unit schedules an order for flushing the user write request so that the number of changed mapping table pages generated when flushing to a flash memory of the SSD in response to the corresponding user write request becomes equal to or less than a first set value having the maximum number of protected pages as an upper limit; and a step in which the control unit processes the user write request to be flushed according to the scheduling.

Description

SSD buffer management technique that minimizes performance degradation in situations where the battery is limited

The present invention relates to a method for managing an SSD buffer to minimize performance degradation in a battery-limited situation, and more specifically, to a method for managing an SSD buffer to minimize performance degradation in a battery-limited situation by efficiently managing an internal buffer of an SSD.

With the continuous explosion of digital data, the demand for high-capacity storage devices is increasing. Solid State Disks (SSDs) have continuously grown based on their characteristics of high performance, high reliability, and low power consumption, and have established themselves as the most widely used secondary storage devices, replacing HDDs (Hard Disk Drives). However, there are difficulties in producing high-capacity SSDs required by recent cloud systems. In order to ensure high reliability and high performance, enterprise SSDs use batteries to prevent data in volatile buffers inside the SSD from being lost even when power is cut off. In other words, batteries (capacitors) provide energy to safely store data stored in volatile DRAM in NAND flash memory when power is cut off, and are thus key to the reliability and data integrity of SSDs. However, the rate of increase in the density of batteries installed inside SSDs (approximately 10 times over 40 years) is significantly lower than the rate of increase in the density of NAND flash memory, which is the storage medium (100 times over 10 years), making it difficult to manufacture high-capacity SSDs with current technology.

The technical problem to be achieved by the present invention is to provide an SSD buffer management method that minimizes performance degradation in a situation where the battery for managing the SSD internal buffer is limited, while using a smaller amount of battery than before and minimizing performance degradation.

The technical problem to be achieved by the present invention is to provide an SSD buffer management method that can ultimately contribute to improving the productivity of high-capacity SSDs while reducing manufacturing costs by efficiently managing the internal buffer of the SSD in a situation where the battery is limited, thereby minimizing performance degradation.

The technical problems to be achieved by the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the present invention belongs from the description below.

In order to achieve the above technical problem, an embodiment of the present invention provides an SSD buffer management method for minimizing performance degradation in a battery-limited situation, the method comprising: a step in which a control unit of the DDS checks a user write request existing in a write buffer of the SSD within a certain time window in an SSD in which the amount of data on a buffer that the battery can record when power is cut off is limited to a maximum number of protected pages; a step in which the control unit schedules an order for flushing the user write request so that the number of changed mapping table pages generated when flushing to a flash memory of the SSD in response to the corresponding user write request becomes equal to or less than a first set value having the maximum number of protected pages as an upper limit; and a step in which the control unit processes the user write request to be flushed according to the scheduling.

In an embodiment of the present invention, the step of scheduling the flushing order may include the steps of: rearranging data of the mapping table so that user write requests that update the same mapping table page are grouped and processed together; scheduling the processing with a first priority if a page of the mapping table to be changed by the corresponding user write request has already been changed (dirty state); and scheduling the processing with a second priority if the number of user write requests to modify an entry of the same mapping table page is greater than or equal to a second set value.

In an embodiment of the present invention, the maximum number of protected pages may be the number of pages that protect user write requests and some mapping tables existing in the buffer due to limitations of the battery during a flush operation performed using Power-Loss Protection (PLP) at the time of power-off.

In an embodiment of the present invention, when the number of changed mapping table pages that occur when flushing the flash memory in response to the corresponding user write request based on an LRU (Last-recently Used) algorithm is used as the cost of flushing the corresponding pages, the second set value may be the minimum value of the cost.

In an embodiment of the present invention, the method may include a step of not processing the user write request and leaving it in a buffering state when the number of user write requests to modify entries in the same mapping table page is less than the second setting value.

In an embodiment of the present invention, by performing a step of processing to flush the user write request according to the scheduling, the number of continuously changed mapping table pages can be made less than or equal to the first set value.

In an embodiment of the present invention, the step of preferentially flushing a user write request existing in the write buffer when the power is cut off may be included.

In an embodiment of the present invention, the step of flushing the user write request first when the power is cut off, and then flushing the matching table of a part included in the maximum number of protected pages may be included.

In an embodiment of the present invention, in the step of processing to flush the user write request according to the scheduling, the matching table includes a plurality of blocks, each of the blocks includes a plurality of pages, and a corresponding block in which a changed mapping table page exceeding the first set value is generated by the scheduling can be flushed.

In an embodiment of the present invention, the step of rearranging data of the mapping table may include a step of rearranging page entries of the mapping table before the change so as to minimize an increase in dirty memory footprint when comparing the mapping table before the change and the changed mapping table based on an LRU (Last-recently Used) algorithm.

In an embodiment of the present invention, the step of rearranging data of the mapping table may include a step of remapping between a physical address of the flash memory and a logical address of the user write request.

According to an embodiment of the present invention, a method for managing an SSD buffer can be provided to minimize performance degradation in a situation where a battery is limited to manage an SSD internal buffer while using a smaller amount of battery than before.

According to an embodiment of the present invention, an SSD buffer management method can be provided that can ultimately contribute to improving the productivity of high-capacity SSDs while reducing manufacturing costs, by efficiently managing the SSD internal buffer in a situation where the battery is limited, thereby minimizing performance degradation.

According to an embodiment of the present invention, a new scheme for managing internal DRAM of an SSD, Hexa-SSD (SSD buffer management method), which can contribute to overcoming the limitation of SSD capacity expansion due to slow growth of a capacitor (battery) can be provided. Hexa-SSD manages internal DRAM of an SSD using a fundamentally different approach. Instead of caching most of the mapping tables and buffering minimal user writes, it buffers more user writes to reduce the number of modified mapping pages. This can provide an SSD buffer management method that can significantly reduce the amount of mapping table-related write traffic and improve the overall performance of an SSD device.

The effects of the present invention are not limited to the effects described above, and should be understood to include all effects that can be inferred from the detailed description of the present invention or the composition of the invention described in the claims.

Figure 1 shows an example of an SSD structure.
Figure 2 is a drawing showing the data protection operation of the SSD of the comparative example.
FIG. 3 illustrates a protective operation by an SSD buffer management method that minimizes performance degradation in a battery-limited situation according to one embodiment of the present invention.
FIG. 4 is a flowchart illustrating an SSD buffer management method for minimizing performance degradation in a battery-limited situation according to one embodiment of the present invention.
Figure 5 is a diagram showing an example of a mapping table.
Figure 6 is a diagram showing the operation of the comparative example method (FIFO).
Figure 7 is a drawing visually illustrating the operation of the method of the comparative example.
FIG. 8 is a diagram illustrating an SSD buffer management method (Hexa) according to one embodiment of the present invention.
FIG. 9 is a drawing visually illustrating an SSD buffer management method (Hexa) according to one embodiment of the present invention.

The present invention can be modified in various ways and can take various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to specific disclosed forms, but should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention. In describing each drawing, similar reference numerals are used for similar components.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms defined in commonly used dictionaries, such as those defined in common dictionaries, should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly defined in this application.

Hereinafter, with reference to the attached drawings, a preferred embodiment of the present invention will be described in more detail.

A method for managing an SSD buffer to minimize performance degradation in a situation where a battery is limited according to one embodiment of the present invention relates to a method for minimizing performance degradation by efficiently managing an internal buffer of an SSD in a situation where the integration or capacity of a battery is limited.

Figure 1 shows an example of an SSD structure.

An SSD device may include an interface (such as a connection port) connected to a PC, flash memory for data storage, a microcontroller (control unit) for controlling data exchange between the interface and the flash memory, and a volatile buffer for reducing a difference in processing speed between an external device and the SSD. FIG. 1 illustrates a NAND flash memory and a volatile buffer (typically DRAM or SRAM) mounted thereon. In addition, the SSD device may be equipped with multiple data buses for connecting multiple flash memories, and the aforementioned microcontroller may act as a processor. In addition, the enterprise SSD may include a battery mounted internally. In order to ensure high reliability and high performance, the enterprise SSD may use this built-in battery to prevent data in the volatile buffer inside the SSD from being lost even when power is cut off.

DRAM buffers are used for two main purposes. First, they are used to cache a mapping table that has information that maps the physical address of data stored in flash memory to the logical address requested by the operating system. Second, they are used as a write buffer to quickly process write requests arriving from the host (user) and increase the response speed. The battery provides emergency power in the event of a power outage, allowing data in the volatile buffer to be written to flash memory.

Figure 2 is a drawing showing the data protection operation of the SSD of the comparative example.

The comparative example illustrated in Figure 2 illustrates a situation where the battery has enough power to protect all data in the volatile buffer. That is, it shows how both the mapping table and the user data (user write requests) in the volatile buffer are protected.

FIG. 3 illustrates a protective operation by an SSD buffer management method that minimizes performance degradation in a battery-limited situation according to one embodiment of the present invention.

FIG. 3 illustrates a situation in which it is difficult to protect all data in a volatile buffer that increases along with an increase in the capacity of an SSD due to a low speed of improvement in battery integration. That is, the SSD buffer management method (hereinafter, referred to as the SSD buffer management method) for minimizing performance degradation in a situation in which the battery is limited according to the present embodiment assumes a situation in which only a portion of the buffer is protected, as illustrated in FIG. 3, and the amount of data that can be written when the power is cut off is limited. In this situation, if an update of data occurs in the buffer beyond the range that the battery can write, the changes must be forcibly written to the flash memory. At this time, performance degradation occurs. The SSD buffer management method of the present embodiment adopts a strategy to minimize write traffic that is forcibly written to the flash by efficiently scheduling data flowing into the write buffer.

FIG. 4 is a flowchart illustrating an SSD buffer management method for minimizing performance degradation in a battery-limited situation according to one embodiment of the present invention.

The SSD buffer management method of the present embodiment described above can determine the processing priority in the following order among user write requests existing in the write buffer.

In an SSD in which the amount of data on a buffer that the battery can write when the power is cut off is limited by the maximum number of protected pages, the control unit of the DDS checks for a user write request existing in the write buffer within a certain time window (S10). The maximum number of protected pages may be the number of pages that protect the user write request existing in the buffer and some of the mapping tables due to the limitation of the battery during a flush operation performed using PLP (Power-Loss Protection) when the power is cut off. For example, the microcontroller (control unit) described above can check for a write request (user write request) from a host existing in the DRAM buffer as a volatile buffer within a certain time window. For example, as illustrated in FIG. 8 described below, it can check a write request sent from the host to the device queue.

The control unit schedules the order of flushing the user write request so that the number of changed mapping table pages that occur when flushing to the flash memory of the SSD in response to the user write request is less than or equal to a first set value that sets the maximum number of protected pages as an upper limit (S20).

The control unit processes the user write request to flush according to scheduling (S30).

Below, each process is explained in more detail.

In the step (20) of scheduling the flushing order, the data of the mapping table can be rearranged so that user write requests that update the same mapping table page are grouped and processed together (S21). If the page of the mapping table to be changed by the corresponding user write request has already been changed (dirty state), it can be scheduled to be processed with the first priority (S22). Since the execution of the corresponding write request does not increase the number of changed pages of the mapping table, it can be processed with priority. If the user write request to modify the entry of the same mapping table page is greater than or equal to the second setting value, it can be scheduled to be processed with the second priority (S23). For example, if the page of the mapping table to be changed by the corresponding write request has not already been changed, it can be compared with the second setting value of the write request to modify the entry of the same mapping table page. That is, as described in Fig. 3, in a situation where only a part of the buffer is protected and the amount of data that can be written when the power is cut off is limited, if an update of data occurs in the buffer beyond the range that the battery can write, the changes must be forcibly written to the flash memory. That is, the SSD buffer management method of the present embodiment can set a second setting value that serves as a criterion in taking a strategy of efficiently scheduling data flowing into the write buffer to minimize write traffic that is forcibly written to flash.

Unlike the present embodiment, if the user's requests are written to the flash memory in the order in which they arrive, the mapping table may be randomly updated, which may result in a large number of dirty pages being generated in one unit of time. This random generation of dirty pages is not desirable because the I/O load may increase as the number of mapping table pages that are flushed increases.

In this embodiment, as described above, in a situation of limited battery (capacitor) capacity, a strategy is used to protect user data first and protect some mapping tables when power is cut off, while minimizing write traffic to flash memory. That is, if the number of write requests to modify entries in the same mapping table page exceeds the second setting value in normal times, the write requests are processed. That is, changes are forcibly written to flash memory, but in this case, the cost of increasing the number of mapping table change pages is shared by a number of write requests exceeding the setting value, so that performance degradation can be minimized.

When the number of changed mapping table pages that occur when flushing the flash memory in response to the user write request based on the LRU (Least-recently Used) algorithm is used as the cost of flushing the pages, the second setting value may be the minimum value of the cost.

If the number of user write requests to modify entries in the same mapping table page is less than the second setting value, the user write request may not be processed and may be left in a buffered state (S24). Afterwards, if a write request to modify entries in the corresponding mapping table page is confirmed again, the cost of flushing to the flush memory may be calculated by comparing it with the second setting value again.

By processing to flush user write requests according to the above scheduling, the number of continuously changed mapping table pages can be made less than or equal to the first set value. According to this algorithm, in an SSD using Power-Loss Protection (PLP), the flushing operation that should be performed when the power is cut off can be avoided or minimized, so that mitigating the negative impact of the flushing is important for maintaining the performance of the SSD device under battery density (capacitance) constraints.

Meanwhile, the SSD buffer management method of the embodiment of the present invention can preferentially flush a user write request existing in a write buffer when power is cut off (S40). In addition, after preferentially flushing the user write request when power is cut off, the matching table of the part included in the maximum number of protected pages can be flushed (S50).

In the step of processing to flush the user write request according to the above scheduling, the matching table includes a plurality of blocks, each of the blocks includes a plurality of pages, and a corresponding block in which a changed mapping table page exceeding the first setting value is generated by the scheduling can be flushed.

The step of rearranging data in the mapping table may include a process of rearranging page entries of the mapping table before the change to minimize an increase in a dirty memory footprint when comparing the mapping table before the change and the changed mapping table based on an LRU (Least-recently Used) algorithm. The step of rearranging data in the mapping table may also include a process of remapping between a physical address of the flash memory and a logical address of the user write request.

In this way, according to the SSD buffer management method of the present embodiment, when the SSD capacity increases, the DRAM size cannot be increased indefinitely, and since the data of DRAM is volatile, it is difficult to preserve the data when the power is suddenly turned off. Therefore, an architecture can be provided that gives priority to some data of DRAM, particularly USER DATA items, to protect the data, and protects only a part of the mapping table. In particular, in a situation where priority is given to such USER DATA, the DRAM requests in the DRAM BUFFER are grouped to minimize the number of FLUSH times and then FLUSHed to NAND FLASH.

Hereinafter, the SSD buffer management method according to the present embodiment will be described in more detail. The flush overhead of the comparative example method (FIFO-SSD) and the SSD buffer management method of the present embodiment (Hexa-SSD) will be compared and explained.

Figure 5 is a diagram showing an example of a mapping table.

The mapping table initially has one dirty page (m0). The number in the prefix m indicates the index of the mapping table page. Assume that two of the five pages in the mapping table are protected.

The comparative example method (FIFO) illustrated in FIGS. 6 and 7 described below and the SSD buffer management method (Hexa-SSD) according to the present embodiment described below in FIGS. 8 and 9 are both structures in which the write buffer, which is used to buffer the host's request, is protected and only a portion of the mapping table is protected.

Figure 6 is a diagram showing the operation of the method (FIFO) of the comparative example. Figure 7 is a diagram visually illustrating the operation of the method of the comparative example.

The method of comparison (FIFO) writes to flash memory in the order in which user requests arrive. Since flash memory does not allow overwriting of existing data, reflecting the host's write to flash memory also causes an update to the mapping table. Although the mapping information update modifies only one entry, when the mapping table is written to flash, it can be written in units of pages.

In the FIFO illustrated in Fig. 6, there are seven write requests in the device queue sent from the host in the following order: W(4), W(17), W(12), W(2), W(6), W(18), W(7). The numbers in the parentheses represent logical page numbers (LPNs). FIFO-SSD writes user data in the buffer to the flash memory in the order of arrival. This scheme may cause the mapping table to be randomly updated, which may generate a large number of dirty pages per unit time. As illustrated in Fig. 7, FIFO-SSD causes a total of five flushes of the mapping table pages during the write process. This random generation of dirty pages is not desirable because an increase in the number of flushes of the mapping table pages may increase the I/O load.

FIG. 8 is a drawing showing an SSD buffer management method (Hexa) according to one embodiment of the present invention. FIG. 9 is a drawing visually illustrating an SSD buffer management method (Hexa) according to one embodiment of the present invention.

Referring to FIG. 8, the SSD buffer management method of the present embodiment schedules user write requests in a way that minimizes the number of changed mapping table pages (dirty pages) that occur within a certain time window. In particular, the key is to prevent an increase in the number of changed pages of the mapping table by processing requests that update the same mapping table page together.

In the example of Fig. 6, when only two mapping table pages can be protected by the battery, if the existing FIFO method is used, the number of mapping table pages that change at each point in time becomes 3, which causes a phenomenon in which a total of 5 flash memory writes occur. On the other hand, in the SSD buffer management method of the present embodiment, requests to update the same mapping page are grouped and processed together. That is, in the examples of Figs. 8 and 9, according to the SSD buffer management method of the present embodiment, the number of mapping pages that are continuously changed is maintained at 2 or less, so only a total of 2 flushes occur.

The SSD (Hexa-SSD) to which the SSD buffer management method of this embodiment is applied partially protects the mapping table with a limited capacity. If the dirty page of the mapping table exceeds the maximum number of protected pages, Hexa-SSD flushes the page to the flash memory based on the LRU (Least Recently Used) algorithm. Since the flush operation does not occur in the SSD using PLP, mitigating the negative impact of the flush is important to maintain performance under capacitance constraints.

To achieve this, Hexa-SSD uses a cost-effective scheduling scheme for buffers in storage. Hexa-SSD selectively forces user data to be stored in flash memory, which minimizes the increase in dirtyness of the mapping table. This scheme improves the locality of updates, reducing the dirty memory space of the mapping table at a given moment. As a result, the frequency of flush operations for the mapping table can be significantly reduced.

On the other hand, Hexa-SSD computes the write cost per data, which represents the increase of dirty pages when the mapping table is flushed, and processes the request with the least cost first. In the example of Fig. 8, the write request W(2) has the highest priority because its associated mapping table page (m0) is already dirty and is not added to the number of dirty translation pages. Next, write requests W(4), W(6), and W(7) are processed. The flush cost is reduced by 1/3 because the address mapping entries are in the same page of the mapping table. With this scheme, Hexa-SSD provides only two flushes of the mapping table for the same operation.

According to the above-described embodiments, we propose a SSD buffer management method that minimizes performance degradation in a battery-limited situation and a novel SSD design called Hexa-SSD to which the method is applied. Hexa-SSD protects a portion of the internal storage buffer to overcome the capacitance constraints of high-capacity SSDs. Hexa-SSD improves performance by reducing the dirty memory footprint of data in DRAM through cost-effective reordering.

Performance evaluations for various workloads show that our SSD buffer management approach, which minimizes performance degradation under battery-constrained situations, delivers up to 42.7% higher IOPS and 49% less write traffic when capacitance is very limited. Hexa-SSD is designed to maximize the use of protected DRAM capacity to overcome capacitance constraints, while smaller dirty pages in the mapping table can improve crash avoidance and recovery processes.

The above description of the present invention is for illustrative purposes, and those skilled in the art will understand that the present invention can be easily modified into other specific forms without changing the technical idea or essential characteristics of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive. For example, each component described as a single component may be implemented in a distributed manner, and likewise, components described as distributed may be implemented in a combined form.

The scope of the present invention is indicated by the claims described below, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

Claims (11)

In a method of SSD buffer management that minimizes performance degradation in battery-limited situations,
In an SSD, the amount of data on a buffer that can be written by a battery installed inside the SSD when power is cut off is limited to the maximum number of protected pages, wherein a step of a control unit of the SSD confirming a user write request existing in a write buffer of the SSD;
A step of scheduling the order of flushing the user write request so that the number of changed mapping table pages that occur when the control unit flushes the flash memory of the SSD in response to the corresponding user write request is less than or equal to a first set value that sets the maximum number of protected pages as an upper limit; and
characterized in that it includes a step of processing the control unit to flush the user write request according to the scheduling;
The step of scheduling the above flushing order is:
A step of reordering page entries in the mapping table based on the number of user write requests that update the same mapping table page;
A step of scheduling to process with the first priority if the page of the mapping table to be changed by the corresponding user write request has already been changed (dirty state); and
A method for managing an SSD buffer to minimize performance degradation in a battery-limited situation, characterized by comprising: a step of scheduling a user write request to modify an entry in the same mapping table page to be processed with a second priority if the number of user write requests to modify the entry in the same mapping table page is greater than or equal to a second setting value;
delete In claim 1,
A method for managing an SSD buffer that minimizes performance degradation in a battery-limited situation, characterized in that the maximum number of protected pages is a number of pages that protect user write requests and some mapping tables existing in the buffer due to battery limitations during a flush operation performed using PLP (Power-Loss Protection) at the time of power-off.
delete In claim 3,
A method for managing an SSD buffer to minimize performance degradation in a battery-limited situation, characterized in that it includes a step of not processing the user write request and leaving it in a buffered state when the number of user write requests to modify entries in the same mapping table page is less than the second setting value.
In claim 3,
A method for managing an SSD buffer that minimizes performance degradation in a battery-limited situation, characterized in that the number of continuously changed mapping table pages becomes less than or equal to the first set value by performing a step of processing to flush the user write request according to the above scheduling.
In claim 6,
A method for managing an SSD buffer to minimize performance degradation in a battery-limited situation, characterized by including a step of preferentially flushing a user write request existing in the write buffer when the power is cut off.
In claim 7,
A method for managing an SSD buffer that minimizes performance degradation in a battery-limited situation, characterized by including a step of flushing a portion of a matching table included in the maximum number of protected pages after preferentially flushing the user write request when the power is cut off.
In claim 3,
In the step of processing to flush the user write request according to the above scheduling,
The above mapping table includes a plurality of blocks, each block including a plurality of pages,
A SSD buffer management method for minimizing performance degradation in a battery-limited situation, characterized in that a block in which a changed mapping table page exceeding the first setting value is flushed by the scheduling is generated.
delete delete