KR102651252B1 - Display device, display deviceand driving method for the same - Google Patents

Abstract

Embodiments of the present invention include a display panel including a data line and a plurality of pixels connected to the gate line, applying a data signal to the data line in a first period and a second period, and transmitting a data signal to the data line between the first period and the second period. A data driver for applying a parking voltage with a variable voltage level to the data line in the third period, a gate driver for applying a gate signal to the gate line in the first and second periods, and a data driver and gate driver for controlling the data driver and the gate driver. A display device including a timing controller and a method of driving the same can be provided.

Description

Display device and its driving method {DISPLAY DEVICE, DISPLAY DEVICEAND DRIVING METHOD FOR THE SAME}

This specification relates to a display device and a driving method thereof, and more specifically, to a display device and a driving method thereof that can reduce power consumption and improve image quality.

As the information society develops, the demand for display devices to display images is increasing in various forms, such as liquid crystal display devices (LCDs) and quantum dot light emitting displays (QLEDs). Various types of display devices such as OLED (Organic Light Emitting Display Device) are being used.

The display device displays an image by sequentially displaying a plurality of frames for a preset time. Additionally, the display device can display photos, games, and videos. The greater the number of frames displayed during a preset time, that is, the shorter the time of one frame, the more naturally the games and videos displayed on the display device will be displayed. You can.

In addition, when the display device is applied to a mobile device such as a smartphone or tablet PC, in order to reduce the power consumption of the mobile device, after a certain period of time has elapsed after the device is used, the display device may display only simple information using low gradation. You can. Additionally, when only simple information is displayed, the time of one frame of an image displayed on a display device may be maintained for a long time.

Additionally, when a still image such as a photo is displayed, the image displayed on the display device can be displayed naturally even if the number of frames displayed during the preset time is small, and the time of one frame can be maintained long to reduce power consumption.

If the time of one frame in the display device becomes longer, the power consumption of the display device can be reduced, but as the time of one frame becomes longer, the time that the data voltage must be maintained becomes longer and the display device's power consumption during the time of one frame becomes longer. There was a problem with the luminance changing.

Accordingly, the inventors of the present specification have invented a display device and a driving method thereof that reduce power consumption and do not deteriorate image quality because the luminance of the display device does not change during one frame.

In order to reduce the power consumption of the display device, the length of the third period disposed between the first period and the second period in which the image signal is input is shorter than the first period and the second period, and the length of the third period in the second mode is shorter than the first period and the second period. can be longer than the first and second periods. However, there was a problem that the luminance could decrease. Accordingly, the inventors of this specification invented a display device with a new structure and a method of driving the display device to solve the problem of low luminance.

The problem according to an embodiment of the present specification is to provide a display device and a method of driving the same that can reduce power consumption.

The problem according to an embodiment of the present specification is to provide a display device and a method of driving the same that can minimize deterioration in image quality without deteriorating luminance.

The problems to be solved according to an embodiment of the present specification are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A data driver that applies a parking voltage whose voltage level is variable to the data line in a third period disposed between the first and second periods in which images are input in response to a plurality of frames according to an embodiment of the present specification, A display device including a gate driver and data driver that applies a gate signal to a gate line in a first period and a second period and a timing controller that controls the gate driver is provided.

It includes a timing controller that operates in a first mode and a second mode according to an embodiment of the present specification, and the timing controller operates in a third period disposed between the first period and the second period in which the video signal is input in the first mode. The length of is shorter than the first period and the second period, and the length of the third period in the second mode is longer than the first period and the second period, and the parking voltage at which the voltage level on the data line is variable in the third period in the second mode. A display device is provided to control the data driver so that this is approved.

An image signal corresponding to an image including at least a first frame and a second frame according to an embodiment of the present specification is supplied to the data driver, and a data signal converted from the image signal corresponding to the first frame is transmitted to a plurality of data lines. Write to a plurality of pixels, apply a parking voltage with a variable voltage level to the plurality of data lines while the connection between the plurality of data lines and the plurality of pixels is disconnected, and the video signal corresponding to the second frame is converted. A method of driving a display device in which data signals are written to a plurality of pixels through a plurality of data lines is provided.

By providing a display device and its driving method according to the embodiments of the present specification, there is an effect of reducing power consumption.

Additionally, by using the above display device and its driving method, there is an effect of preventing image quality from deteriorating.

The effects of the present specification are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

1 is a structural diagram showing the structure of a display device according to embodiments of the present invention.
Figure 2 is a circuit diagram showing a pixel according to embodiments of the present invention.
Figure 3 is a circuit diagram showing a pixel according to embodiments of the present invention.
Figure 4 is a timing diagram showing a first mode and a second mode in a display device according to embodiments of the present invention.
Figure 5 is a graph comparing power consumption in the first mode and the second mode.
Figure 6 is a timing diagram showing a signal being input in a second mode in a display device according to embodiments of the present invention.
Figure 7 is a graph showing the change in luminance in the display device in the first mode and the second mode.
FIG. 8 is a circuit diagram for explaining the operation of the pixel shown in FIG. 2 by the parking voltage.
Figure 9 is a graph showing a change in luminance when a parking voltage is applied to a display device according to embodiments of the present invention.
10A to 10C are timing diagrams showing the waveform of the parking voltage input in the second mode in the display device according to embodiments of the present invention.
Figure 11 is a graph showing the results of measuring the luminance of the display device when the parking voltage is adjusted in the display device according to embodiments of the present invention.
Figure 12 is a flowchart showing a method of driving a display device according to embodiments of the present invention.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and the present embodiments only serve to ensure that the disclosure of the present specification is complete and that common knowledge in the technical field to which the present specification pertains is provided. It is provided to fully inform those who have the scope of the invention, and this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative, and the present specification is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present specification, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present specification, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as ‘after’, ‘after’, ‘after’, ‘before’, etc., ‘immediately’ or ‘directly’ Non-consecutive cases may also be included unless ' is used.

In the case of a description of the signal flow relationship, for example, 'a signal is transmitted from node A to node B', unless 'immediately' or 'directly' is used, it is transmitted from node A via another node. This may include cases where a signal is transmitted to the B node.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical idea of the present specification.

Each feature of the various embodiments of the present specification can be combined or combined with each other, partially or entirely, and various technological interconnections and operations are possible, and each embodiment may be implemented independently of each other or together in a related relationship. It may be possible.

1 is a structural diagram showing the structure of a display device according to embodiments of the present invention.

Referring to FIG. 1 , the display device 100 includes a display panel 110, a data driver 120, a gate driver 130, and a timing controller 140.

The display panel 110 may include a plurality of data lines (DL1 to DLm) extending in a first direction and a plurality of gate lines (GL1 to GLn) extending in a second direction. Here, the first direction and the second direction may be perpendicular to each other, but are not limited thereto.

Additionally, the display panel 110 may include a plurality of pixels 101. One pixel 101 may be connected to one data line and a first gate line and a second gate line among a plurality of gate lines. It can operate by receiving a data signal transmitted through a data line connected to the pixel (1010) in response to the first and second gate signals transmitted through the first and second gate lines connected to the pixel (101). there is.

The data driver 120 is connected to a plurality of data lines DL1 to DLm and can supply data signals to the plurality of pixels 101 through the plurality of data lines DL1 to DLm. The signals supplied from the data driver 140 are not limited to data signals.

The data driver 140 may apply a data signal to the data line in the first period and the second period and supply a parking voltage to the third period disposed between the first period and the second period. The voltage level of the parking voltage can be varied. The voltage level of the parking voltage may correspond to the data voltage corresponding to the data signal input to the data line in the first period.

Additionally, the data driver 120 may include a plurality of source drivers. Each of the plurality of source drivers may be implemented as an integrated circuit.

The gate driver 130 is connected to a plurality of gate lines GL1 to GLn and may supply gate signals to the plurality of gate lines GL1 to GLn. The plurality of gate lines GL1 to GLn may include a plurality of first gate lines and a plurality of second gate lines.

The pixel 101 can receive a reference voltage in response to the first gate signal transmitted through the first gate line and receive a data signal in response to the second gate signal transmitted through the second gate line. Additionally, the pixel 101 can receive a data signal in response to a first gate signal transmitted through the first gate line and receive a reference voltage in response to a second gate signal transmitted through the second gate line. However, the operation of the pixel is not limited to this. The signal supplied from the gate driver 130 is not limited to the gate signal.

The gate driver 130 is shown as being disposed outside the display panel 110, but is not limited thereto, and the gate driver 130 may include a gate signal generator disposed on the display panel 110. . Additionally, the gate driver 130 may be implemented with a plurality of integrated circuits.

In addition, the gate driver 130 is shown as being disposed on one side of the display panel 110, but is not limited to this. It is disposed on both sides of the display panel 110, and the gate driver disposed on the left is odd-numbered. The gate driver connected to the gate line and disposed on the right side of the display panel 110 may be connected to the even-numbered gate line.

The timing controller 140 can control the data driver 120 and the gate driver 130. The timing controller 140 may supply a data control signal to the data driver 120 and a gate control signal to the gate driver 130. The data control signal or gate control signal may include a clock, vertical synchronization signal, horizontal synchronization signal, and start pulse. However, the signal output from the timing controller 140 is not limited to this.

Additionally, the timing controller 140 may supply an image signal to the data driver 120. The timing controller 140 may receive an image signal corresponding to an image including at least the first frame and the second frame and supply the image signal to the data driver 12. The data driver 120 can convert the video signal received from the timing controller 140 into a data signal using a data control signal and supply it to a plurality of data lines.

Additionally, the timing controller 140 may operate in the first mode and the second mode. The second mode may be a mode in which the display device 100 consumes less power than the first mode. Additionally, the second mode can display images with low gray levels on the display panel 110. In addition, the second mode is a first period corresponding to one frame in an image including a plurality of frames displayed on the display panel 110, a second period corresponding to the next frame, and a second period between the first period and the second period. Three periods are arranged, and the length of the third period may be at least longer than the length of either the first period or the second period. Additionally, the driving frequency of the display device 100 may be slower in the second mode compared to the first mode.

In the first mode, the timing controller 140 supplies the video signal corresponding to the first frame to the data driver 120 in the first period and supplies the video signal corresponding to the second frame to the data driver 120 in the second period. can be supplied. Additionally, the timing controller 140 may distinguish the first frame and the second frame by a third period and may not supply a video signal to the data driver 120. Additionally, in the second mode, the timing controller 140 supplies an image signal to the data driver 120 in the first and second periods, and supplies a parking voltage to the data line from the data driver 120 in the third period. You can control it. The parking voltage may not be directly transmitted to the pixel 101.

Figure 2 is a circuit diagram showing a pixel according to embodiments of the present invention.

Referring to FIG. 2, the pixel 101 may include a first transistor (M1), a second transistor (M2), a third transistor (M3), a storage capacitor (Cst), and an organic light emitting diode (OLED).

The first transistor M1 may have a first electrode connected to a first node N1 through which the first power EVDD is transmitted, and a second electrode connected to a second node N2. The gate electrode of the first transistor (M1) may be connected to the third node (N3). The first transistor M1 may cause the driving current generated by the first power source EVDD supplied to the first node N1 to flow to the second electrode in response to the voltage delivered to the gate electrode.

The first electrode of the second transistor M2 may be connected to the reference voltage line VL2 that transmits the reference voltage Vref, and the second electrode may be connected to the third node N3. Additionally, the gate electrode of the second transistor M2 may be connected to the first gate line GL1 that supplies the first gate signal. The second transistor M2 may receive the first gate signal and supply the reference voltage transmitted to the reference voltage line VL2 to the gate electrode of the first transistor M1. The first gate signal may be supplied from the gate driver 130 shown in FIG. 1.

The first electrode of the third transistor M3 may be connected to the data line DL and the second electrode may be connected to the second node N2. Additionally, the gate electrode of the third transistor M3 may be connected to the second gate line GL2. The third transistor M3 receives the second gate signal and responds to the data signal transmitted to the data line DL. The data voltage can be applied to the second electrode of the first transistor (M1). The second gate signal may be supplied from the gate driver 130 shown in FIG. 1. Additionally, the data signal may be supplied from the data driver 120 shown in FIG. 1.

The storage capacitor Cst may have a first electrode connected to the third node N3 and a second electrode connected to the second node N2. The storage capacitor Cst may be disposed between the gate electrode of the first transistor M1 and the second electrode of the first transistor M1 to maintain a voltage difference between the gate electrode and the second electrode.

The organic light emitting diode (OLED) may have an anode connected to a second node (N2) and a cathode electrode connected to a second power source (EVSS). The voltage level of the second power source (EVSS) may be lower than the voltage level of the first power source (EVDD). Organic light-emitting diodes (OLEDs) can emit light in response to current flowing from the anode electrode to the cathode electrode. Organic light-emitting diodes (OLEDs) may include a light-emitting layer that emits light by current flowing between an anode electrode and a cathode electrode. The light emitting layer may include an organic layer.

In the pixel 101 configured as above, the first transistor M1 and the second transistor M2 may be N MOS type transistors, and the third transistor M3 may be a P MOS type transistor. However, it is not limited to this. Additionally, the first and second electrodes of the first to third transtors (M1 to M3) may be a drain electrode and a source electrode, respectively. However, it is not limited to this.

Additionally, the driving current supplied from the first transistor M1 may flow in accordance with Equation 1 below.

Here, Id represents the amount of driving current supplied by the first transistor (M1), Vgs represents the voltage difference between the voltage of the gate electrode and the source electrode of the first transistor (M1), and Vth represents the amount of driving current supplied by the first transistor (M1). ) means the threshold voltage. Also, k means mobility.

As shown in Equation 1 above, the driving current corresponds to the voltage difference between the gate electrode and the source electrode of the first transistor (M1), so when the second electrode is the source electrode, the source electrode corresponds to the data signal. When the data voltage (Vdata) is transmitted and the reference voltage (Vref) is transmitted to the gate electrode, the driving current may flow in response to the data signal.

Additionally, the pixel 101 may include a fourth transistor (M4). The fourth transistor M4 may have a first electrode connected to the first power line VL1 that supplies the first power EVDD and a second electrode connected to the first node N1. Additionally, the gate electrode of the fourth transistor M4 may be connected to the emission control signal line (EML) that transmits the emission control signal. The emission control signal line (EML) is connected to the gate driver 130 shown in FIG. 1 and can receive an emission control signal from the gate driver 130. When the fourth transistor M4 is turned on by the light emission control signal, the voltage of the first power source EVDD can be applied to the first node N1. The fourth transistor M4 may be an N MOS type transistor. there is.

Figure 3 is a circuit diagram showing a pixel according to embodiments of the present invention.

Referring to FIG. 3, the pixel 101 may include a first transistor (M1), a second transistor (M2), a third transistor (M3), a storage capacitor (Cst), and an organic light emitting diode (OLED).

The first transistor M1 may have a first electrode connected to a first node N1 through which the first power EVDD is transmitted, and a second electrode connected to a second node N2. The gate electrode of the first transistor M1 may be connected to the third node N3. The first transistor M1 may cause the driving current generated by the first power source EVDD supplied to the first node N1 to flow to the second electrode in response to the voltage transmitted to the gate electrode.

The first electrode of the second transistor M2 may be connected to the reference voltage line VL2 that transmits the reference voltage Vref, and the second electrode may be connected to the third node N3. Additionally, the gate electrode of the second transistor M2 may be connected to the first gate line GL1 that supplies the first gate signal. The second transistor (M2) can receive the first gate signal and supply the reference voltage (Vref) transmitted to the reference voltage line (VL2) to the gate electrode of the first transistor (M1). The first gate signal may be supplied from the gate driver 130 shown in FIG. 1.

The first electrode of the third transistor M3 may be connected to the data line DL and the second electrode may be connected to the second node N2. Additionally, the gate electrode of the third transistor M3 may be connected to the second gate line GL2. The third transistor M3 may receive the second gate signal and apply the data voltage Vdata corresponding to the data signal transmitted to the data line DL to the second electrode of the first transistor M1. The second gate signal may be supplied from the gate driver 130 shown in FIG. 1. Additionally, the data signal may be supplied from the data driver 120 shown in FIG. 1.

The storage capacitor Cst may have a first electrode connected to the third node N3 and a second electrode connected to the second node N2. The storage capacitor Cst may be disposed between the gate electrode of the first transistor M1 and the second electrode of the first transistor M1 to maintain a voltage difference between the gate electrode and the second electrode.

The organic light emitting diode (OLED) may have an anode connected to a second node (N2) and a cathode electrode connected to a second power source (EVSS). The voltage level of the second power source (EVSS) may be lower than the voltage level of the first power source (EVDD). Organic light-emitting diodes (OLEDs) can emit light in response to current flowing from the anode electrode to the cathode electrode. An organic light-emitting diode (OLED) may include a light-emitting layer that emits light by electric current between an anode electrode and a cathode electrode, and the light-emitting layer may include an organic film.

In the pixel 101 configured as above, the first transistor M1 and the second transistor M2 may be N MOS type transistors, and the third transistor M3 may be a P MOS type transistor. However, it is not limited to this. Additionally, the first and second electrodes of the first to third transistors M1 to M3 may be a drain electrode and a source electrode, respectively. However, it is not limited to this.

Additionally, the driving current supplied from the first transistor M1 may flow in accordance with Equation 1 above.

As shown in Equation 1 above, the driving current corresponds to the voltage difference between the gate electrode and the source electrode of the first transistor (M1), so when the second electrode is the source electrode, the gate electrode corresponding to the data signal When the data voltage is transmitted and the reference voltage (Vref) is transmitted to the source electrode, the driving current may flow in response to the data signal.

Additionally, the pixel 101 may include a fourth transistor (M4). The fourth transistor M4 may have a first electrode connected to the first power line VL1 that supplies first power, and a second electrode connected to the first node N1. Additionally, the gate electrode of the fourth transistor M4 may be connected to the emission control signal line (EML) that transmits the emission control signal. The emission control signal line (EML) is connected to the gate driver 130 shown in FIG. 1 and can receive an emission control signal from the gate driver 130. When the fourth transistor M4 is turned on by the light emission control signal, the voltage of the first power source EVDD can be applied to the first node N1. The fourth transistor M4 may be an N MOS type transistor.

FIG. 4 is a timing diagram showing a first mode and a second mode in a display device according to embodiments of the present invention, and FIG. 5 is a graph comparing power consumption in the first mode and the second mode.

Referring to FIG. 4, a vertical synchronization signal (Vsync) that is input in a high state on a frame basis is generated, and an image can be displayed within a certain time after the vertical synchronization signal (Vsync) ends. Here, it is shown that one first gate signal (gs1) and one second gate signal (gs2) are generated between the vertical synchronization signals (Vsync). For convenience of explanation, this means that the operation of only one pixel is shown. It is for explanation.

And, because the second transistor M2 shown in FIGS. 2 and 3 is an N MOS type transistor and the third transistor M3 is a P MOS type transistor, the first gate signal gs1 is transmitted in a high state. The second gate signal gs2 may be transmitted in a low state.

The display device 100 may operate in the first mode (A) or the second mode (B). In FIG. 4, the display device 100 indicates that four vertical synchronization signals (Vsync) are generated during a certain period of time in the first mode (A), and two vertical synchronization signals (Vsync) are generated during a certain period of time in the second mode (A). A signal appears. The number of first gate signals (gs1) and second gate signals (gs2) supplied to the first gate line (GL1) and second gate line (GL2) in the first mode (A) is the same as in the second mode (B). The number may be four times the number of the first gate signal gs1 and the second gate signal gs2 supplied to the first gate line GL1 and the second gate line GL2.

When the first gate signal gs1 and the second gate signal gs2 are transmitted to the pixel 101, the pixel 101 may receive a data voltage Vdata corresponding to the data signal. Therefore, when the data voltage is transmitted four times in the first mode (A), the data voltage (Vdata) can be transmitted once in the second mode (B). That is, the number of data signals input to the display device 100 in the second mode (B) during a preset time may be less than the number of data signals input to the display device 100 in the first mode (A).

And, Figure 5 compares the power consumption in the first mode (A) and the second mode (B), respectively. The power consumption generated in the first mode (A) and the second mode (B) is the organic light emission It includes a diode (OLED) and a logic element (Logic) and may occur in the data driver 120, gate driver 130, or timing controller 140 for supplying driving current to the organic light emitting diode (OLED).

When the display device 100 expresses the same gradation in the first mode (A) and the second mode (B), the amount of driving current supplied to the organic light emitting diode (OLED) is the same, so that the As shown, the amount of power consumption generated by organic light emitting diodes (OLEDs) may be the same. However, as shown in the upper part of the dotted line (L1), the logic element (Logic) operates differently depending on the driving frequency, so that the amount of power consumed by the display device 100 in the second mode (B) is smaller than that of the first mode. It may be less than the amount of power consumed by the display device 100 in (A).

FIG. 6 is a timing diagram showing a signal being input in a second mode in a display device according to embodiments of the present invention, and FIG. 7 is a timing diagram showing a change in luminance in the display device in the first mode and the second mode. It's a graph.

Referring to FIG. 6, in the second mode (B), the data voltage (Vdata) corresponding to the data signal in the first period (T1) and the second period (T2) corresponding to the first frame and the second frame among the plurality of frames. ) can be input to all pixels 101s of the display panel 110. Additionally, a third period (T3) may be arranged between the first period (T1) and the second period (T2). Generally, in the display device 100, the third period T3 may be a period in which the timing controller 140 receives a vertical synchronization signal and distinguishes one frame from the next frame.

In the second mode (B), the length of the third period (T3) can be set to be longer than that in the first mode (A). If the length of the third period (T3) is set long, it may take a long time for the next data signal to be input after the data signal is input to the data line (DL), so the period of one frame becomes long, and As shown in Figure 5, the power consumption of the display device 100 can be reduced.

On the other hand, wiring including a data line (DL) and power lines (VL1 and VL2) may be disposed around the pixel 101, and a parasitic capacitor may be formed with these wirings in the pixel 101. Additionally, as the size of the voltage applied to the wiring changes, the size of the parasitic capacitor may vary, and as the size of the parasitic capacitor varies, the voltage stored in the storage capacitor (Cst) may vary. If the voltage stored in the storage capacitor (Cst) changes, the amount of light emitted from the pixel 101 may change and the luminance of the display device 100 may change. Due to the change in luminance, the user may experience flicker on the display device 100. It can be recognized as occurring.

And, Figure 7 compares the luminance set in the display device 100 with the luminance actually displayed in the display device 100. The straight line represents the luminance set in the display panel 110, and the straight line with an arrow represents the luminance set in the display panel 110. 110) indicates the actual displayed luminance.

As shown in (a) of FIG. 7, in the first mode (A), the time of one frame (1 frame) is short and the time at which a new data signal is input to the pixel 101 is reached quickly, so the display device The time during which the luminance of the display device 100 is lowered becomes very short, and the user may not be able to visually recognize that the luminance of the display device 100 is lowered.

On the other hand, as shown in (b) of FIG. 7, in the case of the second mode (B), the length of the third period (T3) is very long, and thus the time of one frame (1 frame) is lengthened, resulting in the pixel 101 The time when new data is entered is delayed. In reality, the time taken for the luminance of the display device 100 to decrease may be prolonged, so a problem may occur in which the user visually perceives the luminance of the display device 100 to decrease within the time of one frame.

In order to solve the above problem, the parking voltage (Vpark) may be applied in the third period (T3). The parking voltage Vpark applied to the pixel 101 can prevent luminance from decreasing in the third period T3.

FIG. 8 is a circuit diagram for explaining an operation in which a parking voltage is applied to the pixel shown in FIG. 2.

Referring to FIG. 8, the second transistor M2 of the pixel 101 is turned off in the third period T3. Accordingly, the third node (N3) and the data line (DL) may be in an open state. The storage capacitor Cst can store the voltage difference between the data voltage Vdata and the reference voltage Vref and supply it to the organic light emitting diode (OLED) corresponding to the difference between the data voltage Vdata and the reference voltage Vref.

Additionally, a parasitic capacitor Cpara may be formed between the data line DL and the gate electrode of the first transistor M1. Due to changes in the voltage charged to the parasitic capacitor Cpara, the voltage applied to the gate electrode of the first transistor M1 may become unstable, causing the size of the driving current to vary. Accordingly, a luminance change may occur in the display device 100, which may cause a problem in which the image quality of the display device 100 deteriorates.

When the parking voltage (Vpark) is applied to the data line (DL) while the second transistor (M2) is turned off, the magnitude of the voltage applied to the data line (DL) becomes constant due to the parking voltage (Vpark), thereby reducing the parasitic capacitor. The size of (Cpara) can be made constant. As a result, the luminance of the display device 100 can be suppressed from being lowered, and the image quality of the display device 100 can be improved.

Although only the pixel shown in FIG. 2 is described here, the parking voltage (Vpark) can also be applied to the pixel shown in FIG. 3. The parking voltage Vpark may also be transmitted to the pixel shown in FIG. 3 through the data line DL.

Figure 9 is a graph showing a change in luminance when a parking voltage is applied to a display device according to embodiments of the present invention.

Referring to FIG. 9, an experiment was conducted in which a data voltage corresponding to 150 gray levels was written to the pixel 101 by a data signal. (a) shows the case where the parking voltage (Vpark) has the same voltage level as the data voltage (Vdata) corresponding to the 0 gray level, and (b) shows the case where the parking voltage (Vpark) has the same voltage level as the data voltage (Vdata) corresponding to the 125 gray level. represents the case where the parking voltage (Vpark) has the same voltage level as the data voltage (Vdata) corresponding to 150 gray levels, (d) represents the case where the parking voltage (Vpark) has the same voltage level as This indicates a case where the voltage level is the same as the data voltage (Vdata) corresponding to the 200 gray scale. And, in FIG. 9, the arrow indicates the point in time at which the data signal is written. And, the period between the arrows may correspond to the third period (T3). Additionally, the display device 100 was driven at 3Hz.

Looking at (a) to (d), it can be seen that the luminance falls after the data voltage (Vdata) is applied and then rises again. However, (a) shows that the luminance in the third period (T3) becomes lower than when the data was applied. (b) shows that the difference between the luminance in the third period (T3) and the luminance at the time the data voltage (Vdata) is applied is small. (c) shows that the luminance in the third period (T3) becomes higher than when the data voltage (Vdata) is applied. And, (d) also shows that the luminance in the third period (T3) becomes higher than when the data signal is applied to the data voltage (Vdata).

Accordingly, it can be seen that the luminance of the display device 100 changes in the third period T3 even if the parking voltage Vpark is applied to the data line DL. Additionally, it can be seen that the luminance of the display device 100 varies depending on the size of the parking voltage (Vpark). Therefore, it is necessary to apply an appropriate parking voltage (Vpark) to each pixel 101 in the third period (T3). However, the voltage level of the data voltage (Vdata) applied to the pixel 101 is not constant, so it is difficult to calculate the appropriate voltage level of the parking voltage (Vpark). As the third period (T3) becomes longer, the third period (T3) becomes longer. At T3), the decrease in luminance of the display device 100 may be greater.

10A to 10C are timing diagrams showing the waveform of the parking voltage input in the second mode in the display device according to embodiments of the present invention. And, the voltage level of the parking voltage applied in the second mode may correspond to the data voltage.

Referring to FIG. 10A, if the data voltage (Vdata) corresponding to the data signal in the first period (T1) is higher than the preset voltage, the voltage level of the parking voltage (Vpark) is set to the voltage level of the parking voltage (Vpark) in the third period (T3). ), it may be input in a state lower than the data voltage (Vdata) in the first period (T3a) and then gradually change to lower as time passes within the third period (T3).

Referring to FIG. 10b, if the data voltage (Vdata) corresponding to the data signal in the first period (T1) is lower than the preset voltage, the voltage level of the parking voltage (Vpark) is the voltage level of the parking voltage (Vpark) in the third period (T1). In the first period (Ta) of T3), the voltage level of the data voltage (Vdata) is inputted in a state higher than that of the data voltage (Vdata), and then can be changed to gradually become higher as time passes within the third period (T3).

Referring to FIG. 10C, if the data voltage (Vdata) corresponding to the data signal in the first period (T1) is a preset voltage, the voltage level of the parking voltage (Vpark) is the voltage level of the parking voltage (Vpark) in the third period (T3). It may be input in a state lower than the voltage level of the data voltage (Vdata) in the first period (Ta) and then gradually change to become higher as time passes within the third period (T3). If the voltage level of the data voltage (Vdata) is not input in the first period (Ta) of the third period (T3), the luminance rapidly increases in the first period (Ta), allowing the user to recognize the luminance change. . To solve this problem, the data voltage (Vdata) can be input in a state lower than the voltage level in the first period (Ta) of the third period (T3).

As shown in FIGS. 10A to 10C, the voltage level of the parking voltage Vpark may change every horizontal time. And, the voltage level of the parking voltage can be adjusted by Equation 2 below.

Here, Vpark1 represents the voltage level of the parking voltage (Vpark) input in the first period (Ta) of the third period (T3), Vdata represents the data voltage in the first period (T1), and VparkN represents the third period (T3). It represents the parking voltage (Vpark) input in the Nth period of the third period (T3), and Vpark(N+1) represents the parking voltage (Vpark) input in the N+1th period of the third period (T3). Additionally, x has a value less than 1. For example, x may have a value of 0.14.

Figure 11 is a graph showing the results of measuring the luminance of the display device when the voltage level of the parking voltage is adjusted in the display device according to embodiments of the present invention.

Referring to FIG. 11, the parking voltage (Vpark) in the first period (T3a) of the third period (T3) corresponds to the data voltage (Vdata) corresponding to 100 gradations, and the second period (T3b) in the third period (T3). ), the parking voltage (Vpark) corresponds to the data voltage (Vdata) corresponding to 50 gray levels, and in the third period (T3c) of the third period (T3), the parking voltage (Tc) corresponds to the data voltage (Vdata) corresponding to 25 gray levels. ) can respond. Additionally, in the first period (T1) and the second period (T2), the data voltage (Vdata) may correspond to 230 gray levels.

As shown in FIG. 11, when the parking voltage Vpark is varied, the luminance difference of the display device 100 is reduced in the third period T3.

Figure 12 is a flowchart showing a method of driving a display device according to embodiments of the present invention.

Referring to FIG. 12, according to a method of driving a display device, an image signal corresponding to an image including at least a first frame and a second frame can be supplied to the data driver.

An image signal corresponding to the first frame may be written to a plurality of pixels through a plurality of data lines. (S1200) An image displayed on a display device includes a plurality of frames including a first frame and a second frame. , the time at which the data signal is written in the first frame can be set as the first period, and the time at which the data signal is written in the second frame can be set as the second period. Additionally, the period disposed between the first period and the second period can be set as the third period.

And, in a state where the connection between the plurality of data lines and the plurality of pixels is disconnected, a parking voltage with a variable voltage level can be applied to the plurality of data lines. (S1210) The period during which the parking voltage is applied may be a third period. . The disconnection between a plurality of data lines and a plurality of pixels may mean that the data voltage is not transmitted to one electrode of the storage capacitor of the pixel through the data line.

If the data voltage corresponding to the data signal in the first period is higher than a preset voltage, the parking voltage may be changed in a direction to gradually decrease than the voltage level of the data voltage in the third period.

In addition, if the data voltage corresponding to the data signal in the first period is lower than the preset voltage, the parking voltage may be changed in a direction to gradually increase than the voltage level of the data voltage in the third period. .

Additionally, if the data voltage corresponding to the data signal in the first period is a preset voltage, the parking voltage may vary from decreasing to increasing in the third period.

And, the video signal corresponding to the second frame can be written to a plurality of pixels through a plurality of data lines (S1220).

Also, the length of the third period may be longer than at least one of the first period and the second period. Because of this, the time for which the data voltage written to the pixel is maintained may be long. Also, as the time for which the data voltage is maintained is increased, the power consumption of the display device can be reduced.

Although the embodiments of the present specification have been described in more detail with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present specification. . Accordingly, the embodiments disclosed in this specification are not intended to limit the technical idea of the present specification, but rather to explain it, and the scope of the technical idea of the present specification is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of this specification should be interpreted in accordance with the claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of this specification.

100: display device
110: display panel
120: data driver
130: gate driver
140: Timing controller

Claims (20)

A display panel including a data line and a plurality of pixels connected to a gate line;
Data for applying a data signal to the data line in a first period and a second period, and applying a parking voltage whose voltage level is variable to the data line in a third period disposed between the first period and the second period. driver;
a gate driver that applies a gate signal to the gate line in the first period and the second period; and
Includes a timing controller that controls the data driver and the gate driver,
Each of the plurality of pixels includes a first transistor that generates a driving current flowing from the first electrode to the second electrode in response to the data signal, and a first transistor that receives the gate signal and corresponds to the data signal transmitted to the data line. A second transistor that applies a data voltage to the second electrode of the first transistor, and an organic light emitting diode that emits light in response to the driving current,
If the data voltage corresponding to the data signal in the first period is higher than a preset voltage, the parking voltage is input in a state lower than the data voltage in the first period of the third period. A display device that changes to gradually lower as time passes within the third period.
According to paragraph 1,
The timing controller is,
Supplying an image signal corresponding to an image including at least a first frame and a second frame to the data driver,
The data driver writes data signals converted into video signals corresponding to the first frame to the plurality of pixels in the first period, and data converted into data signals corresponding to the second frames in the second period. A display device that writes signals to the plurality of pixels.
delete According to paragraph 1,
If the data voltage corresponding to the data signal in the first period is lower than a preset voltage, the parking voltage is input at a level higher than the data voltage in the first period of the third period. A display device that gradually changes to become higher as time passes within the third period.
According to paragraph 1,
If the data voltage corresponding to the data signal in the first period is a preset voltage, the parking voltage has a voltage level lower than the data voltage in the first period of the third period. A display device that changes to gradually increase over time within 3 periods.
In paragraph 1
The pixel is,
a third transistor that receives a gate signal different from the gate signal and supplies a reference voltage transmitted to a reference voltage line to the gate electrode of the first transistor;
A display device including a storage capacitor disposed between a gate electrode of the first transistor and a second electrode of the first transistor.
According to clause 6,
The pixel is disposed between a first power line that supplies first power and the first electrode of the first transistor, and connects the first power line and the first electrode of the first transistor in response to a light emission control signal. A display device including a fourth transistor.
A display panel including a data line and a plurality of pixels connected to a gate line;
Data for applying a data signal to the data line in a first period and a second period, and applying a parking voltage whose voltage level is variable to the data line in a third period disposed between the first period and the second period. driver;
a gate driver that applies a gate signal to the gate line in the first period and the second period; and
Includes a timing controller that controls the data driver and the gate driver,
The pixel is
a first transistor that generates a driving current flowing from the first electrode to the second electrode in response to the data signal;
a second transistor that receives a first gate signal and supplies a data voltage corresponding to the data signal transmitted to the data line to the gate electrode of the first transistor;
a third transistor that receives a second gate signal and applies a reference voltage transmitted to the reference voltage line to the second electrode of the first transistor;
a storage capacitor disposed between the gate electrode of the first transistor and the second electrode of the first transistor; and
A display device including an organic light emitting diode that emits light in response to the driving current.
According to clause 8,
The pixel is disposed between a first power line that supplies first power and the first electrode of the first transistor, and connects the first power line and the first electrode of the first transistor in response to a light emission control signal. A display device including a fourth transistor.
According to clause 9,
A display device wherein the light emission control signal is supplied from the gate driver.
According to paragraph 1,
The length of the third period is longer than at least one of the first period and the second period.
A display panel including a data line and a plurality of pixels connected to a gate line;
a data driver that applies a data signal to the data line;
a gate driver that applies a gate signal to the gate line; and
A timing controller that controls the data driver and the gate driver and operates in a first mode and a second mode,
The timing controller is configured such that the length of the third period disposed between the first period and the second period in which the video signal is input in the first mode is shorter than the first period and the second period, and the length of the third period in the second mode is shorter than the first period and the second period. The length of the period is longer than the first period and the second period, and the data driver is controlled so that a parking voltage with a variable voltage level is applied to the data line in the third period in the second mode,
If the data voltage corresponding to the data signal in the first period is lower than a preset voltage, the parking voltage is input at a level higher than the data voltage in the first period of the third period. A display device that gradually changes to become higher as time passes within the third period.
According to clause 12,
If the data voltage corresponding to the data signal in the first period is higher than a preset voltage, the parking voltage is input in a state lower than the data voltage in the first period of the third period. A display device that changes to gradually lower as time passes within the third period.
delete According to clause 12,
If the data voltage corresponding to the data signal in the first period is a preset voltage, the parking voltage has a voltage level lower than the data voltage in the first period of the third period. A display device that changes to gradually increase over time within 3 periods.
A first transistor comprising a data line and a plurality of pixels connected to the gate line, each of the plurality of pixels generating a driving current flowing from the first electrode to the second electrode in response to the data signal through the data line. , a second transistor that receives a gate signal through the gate line and applies a data voltage corresponding to the data signal transmitted to the data line to the second electrode of the first transistor, and that emits light in response to the driving current. In a display device including an organic light emitting diode,
providing an image signal corresponding to an image including at least a first frame corresponding to a first period and a second frame corresponding to a second period;
Writing a data signal converted from an image signal corresponding to the first frame to the plurality of pixels through a plurality of data lines;
applying a parking voltage whose voltage level varies to the plurality of data lines while the plurality of data lines are disconnected from the plurality of pixels; and
Comprising the step of writing a data signal converted from an image signal corresponding to the second frame to the plurality of pixels through the plurality of data lines,
If the data voltage corresponding to the data signal in the first period is a preset voltage, the parking voltage level is higher than the data voltage in the first period of the third period between the first and second periods. A method of driving the display device in which the display device is input in a low state and then gradually changed to a high level as time passes within the third period.
According to clause 16,
If the data voltage corresponding to the data signal in the first period is higher than a preset voltage, the parking voltage level is higher than the data voltage in the first period of the third period between the first and second periods. A method of driving a display device that is input to a lower state and then changes to gradually lower as time passes within the third period.
According to clause 16,
If the data voltage corresponding to the data signal in the first period is lower than a preset voltage, the voltage level of the parking voltage is set to the data voltage in the first period of the third period between the first and second periods. A method of driving a display device in which the voltage is input in a state higher than the voltage and then varies to gradually increase over time within the third period.
delete According to clause 16,
Between the first and second periods A method of driving a display device, wherein the length of the third period is longer than at least one of the first period and the second period.

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