KR102568596B1 - Buffer circuit for reducing reference voltage level fluctuating - Google Patents

Abstract

A buffer circuit for reducing reference voltage level fluctuations is disclosed. In the buffer circuit of the present invention, a mitigation capacitor driven to mitigate the fluctuation of the reference voltage and / or the effect thereof due to the coupling noise of the parasitic capacitor unintentionally generated between the channel of the reference transistor and the reference voltage during operation is provided do. Accordingly, according to the buffer circuit of the present invention, fluctuations in the reference voltage level during operation and/or effects thereof are remarkably reduced.

Description

Buffer circuit reducing reference voltage level fluctuation {BUFFER CIRCUIT FOR REDUCING REFERENCE VOLTAGE LEVEL FLUCTUATING}

The present invention relates to a buffer circuit, and more particularly, to a buffer circuit that reduces a reference voltage level fluctuation.

A buffer circuit in a semiconductor device is a circuit that buffers a reception signal based on a reference voltage, and is generally implemented by including a reception transistor formed of a MOS type transistor and a reference transistor.

At this time, the receiving transistor and the reference transistor are connected in parallel to a common terminal. Also, the common terminal is controlled to a constant voltage level according to the activation of the enable signal, the reception signal is applied to a gate terminal of a receiving transistor, and the reference voltage is applied to a gate terminal of a reference transistor.

This buffer circuit is generated by comparing the voltage level of the received signal with a reference voltage as a reference and amplifying the compared result.

Meanwhile, the reference voltage is a voltage provided as a reference for not only the corresponding buffer circuit but also other buffer circuits in the semiconductor device. Therefore, when a change in the reference voltage level occurs during operation of the buffer circuit, a malfunction of the semiconductor device may occur.

An object of the present invention is to provide a buffer circuit that reduces a reference voltage level fluctuation during operation.

One aspect of the present invention for achieving the above object relates to a buffer circuit for buffering a received signal based on a reference voltage. A buffer circuit according to an aspect of the present invention includes a first supply voltage; a second supply voltage; common terminal; a first sensing terminal; a second sensing terminal; an enable switching transistor electrically connecting the first supply voltage and the common terminal in response to activation of an enable signal; a receiving transistor formed between the common terminal and the first sensing terminal and gated by the received signal; a reference transistor formed between the common terminal and the second sensing terminal and gated by the reference voltage; A sensing amplifier connected to the second supply voltage, sensing and amplifying a voltage difference between the first sensing terminal and the second sensing terminal, and providing the voltage difference between the first amplifying terminal and the second amplifying terminal, wherein the first amplifying unit a voltage difference between the terminal and the second amplification terminal is amplified with respect to a voltage difference between the first sensing terminal and the second sensing terminal; and a relaxation capacitor having one end connected to the enable signal and the other end connected to the reference voltage, the relaxation capacitor for alleviating a change in the reference voltage according to the operation of the reference transistor.

Another aspect of the present invention for achieving the above object relates to a buffer circuit for buffering a received signal based on a reference voltage, wherein the received signal is loaded with a plurality of unit data information continuously provided. Buffer circuits according to another aspect of the present invention are enabled in response to activation of corresponding first to nth sub-enable signals (where n is 2 to the power of k, and k is a natural number equal to or greater than 1). First to n-th buffering units for detecting and buffering the voltage level of the received signal with respect to the reference voltage, wherein the first to n-th sub-enable signals have phases shifted by 2π/n at the same period, and the plurality of units the first to n-th buffering units sequentially activated in response to data information; and a sub-enable generator configured to sequentially activate the first through n-th sub-enable signals while the global enable signal is activated. Each of the first to n-th buffering units may include a first supply voltage; a second supply voltage; common terminal; a first sensing terminal; a second sensing terminal; an enable switching transistor electrically connecting the first supply voltage and the common terminal in response to activation of the first through n-th sub-enable signals corresponding thereto; a receiving transistor formed between the common terminal and the first sensing terminal and gated by the received signal; a reference transistor formed between the common terminal and the second sensing terminal and gated by the reference voltage; and a sensing amplification unit connected to the second supply voltage, sensing and amplifying a voltage difference between the first sensing terminal and the second sensing terminal and providing the voltage difference between the first amplifying terminal and the second amplifying terminal, wherein the first and the sensing amplifier configured to amplify a voltage difference between the amplification terminal and the second amplification terminal with respect to a voltage difference between the first sensing terminal and the second sensing terminal. The buffer circuit is a relaxation capacitor having one end connected to the reference voltage and the other end connected to a preliminary signal, the preliminary signal transitioning according to the transition of the global enable signal, wherein the transition of the global enable signal The alleviation capacitor for mitigating the change of the reference voltage according to is further provided.

Another aspect of the present invention for achieving the above object also relates to a buffer circuit for buffering a received signal based on a reference voltage. A buffer circuit according to another aspect of the present invention includes a first supply voltage; a second supply voltage; common terminal; a first sensing terminal; a second sensing terminal; an enable switching transistor electrically connecting the first supply voltage and the common terminal in response to activation of an enable signal; a receiving transistor formed between the common terminal and the first sensing terminal and gated by the received signal; a reference transistor formed between the common terminal and the second sensing terminal and gated by the reference voltage; A sensing amplification unit formed between the first supply voltage and the second supply voltage, which is enabled in response to activation of the enable signal and compares voltage levels of the first sensing terminal and the second sensing terminal to the sensing amplification unit outputting an amplified signal, wherein the amplified signal is controlled to a logical state according to a result of comparing voltage levels between the first sensing terminal and the second sensing terminal; and a relaxation capacitor having one end connected to the reference voltage and the other end connected to the amplification signal, wherein a difference between a change in the received signal and the reference voltage according to a difference in voltage level between the input signal and the reference voltage is alleviated. It is provided with the mitigation capacitor for

In the buffer circuit of the present invention configured as described above, the fluctuation of the reference voltage due to the coupling noise of the parasitic capacitor unintentionally generated between the channel of the reference transistor and the reference voltage during operation and / or driving to mitigate the effect thereof A relaxation capacitor is provided.

Accordingly, according to the buffer circuit of the present invention, fluctuations in the reference voltage level during operation and/or effects thereof are remarkably reduced.

A brief description of each figure used in the present invention is provided.
1 is a diagram for explaining reference voltage level variation due to coupling noise.
2 is a diagram showing a buffer circuit according to a first embodiment of the present invention.
FIG. 3 is a diagram for explaining an effect according to the buffer circuit of FIG. 2 .
4 is a diagram showing a buffer circuit according to a second embodiment of the present invention.
FIG. 5 is a diagram showing one of the plurality of buffering units of FIG. 4 as an example.
FIG. 6 is a diagram for explaining an effect of the buffer circuit of FIG. 4, and is a diagram showing timing of main signals.
7 is a diagram showing a buffer circuit according to a third embodiment of the present invention.

In order to fully understand the present invention and its operational advantages and objectives achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed content will be thorough and complete, and the spirit of the present invention will be sufficiently conveyed to those skilled in the art.

And, in understanding each drawing, it should be noted that the same members are intended to be shown with the same reference numerals as much as possible. In addition, in the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it is apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. In addition, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

Meanwhile, in the present specification, reference numerals are added in <> along with the same reference numerals for components performing the same configuration and action. At this time, these components are commonly referred to by reference numerals. And, if it is necessary to distinguish them individually, '<>' is added after the reference numeral.

In describing the content of the present invention throughout the specification, the meaning of the terms 'electrically connected', 'connected', and 'connected' between individual components means not only direct connection but also properties to a certain degree or more. It includes everything that is connected through an intermediate medium while maintaining it. Terms such as 'transferred' and 'derived' of individual signals also include not only direct meanings, but also indirect meanings through an intermediate medium while maintaining the properties of signals to some extent or more. In addition, terms such as 'applied', 'applied', 'input' of a voltage or signal are also used throughout the specification in the same meaning.

In addition, a plurality of expressions for each component may be omitted. For example, even a configuration composed of a plurality of switches or a plurality of signal lines may be expressed as 'switches' or 'signal lines', or may be expressed as a singular word such as 'switch' or 'signal line'. This is because the switches sometimes operate complementary to each other, and sometimes operate independently, and when a signal line is made of a bundle, such as several signal lines having the same property, for example, data signals, It is also because there is no need to differentiate in plural. In this respect, these descriptions are justified. Accordingly, similar expressions should also be interpreted in the same sense throughout the specification.

Prior to describing embodiments of the present invention, a reference voltage variation according to coupling noise is described with reference to FIG. 1 .

As shown in FIG. 1, the reference transistor 10 implemented as a MOS transistor is composed of two junctions 11 and 13 formed on the substrate SUB and a gate terminal 15, and the substrate SUB ) and the gate terminal 15, a gate oxide film 17 is formed.

In the reference transistor 10 , a channel layer 19 connecting the two junctions 11 and 13 by a reference voltage VREF may be formed on the gate terminal 15 . In addition, an unintentional parasitic capacitor Cpar in which the gate oxide film 17 is a dielectric layer is formed between the gate terminal 15 and the channel layer 19, and the reference voltage VREF is applied to the channel layer ( 19) coupled to

Also, the reference voltage VREF is provided from the reference voltage generator 20 implemented inside the semiconductor device.

The reference voltage generator 20 is composed of a resistance string 21 and a switching unit 22. The resistor string 21 includes a plurality of resistors R1 to R4 formed between a power supply voltage VDD and a ground voltage VSS. A plurality of divided voltages VDV<1> to VDV<5> having voltage levels between the power supply voltage VDD and the ground voltage VSS are formed by the resistance string 21 .

Further, the switching unit 22 corresponds to the plurality of divided voltages VDV<1> to VDV<5>, and gates a plurality of corresponding selection signals RSEL<1> to RSEL<5>. It includes two reference switching transistors 22<1> to 22<5>.

Accordingly, when any one of the selection signals RSEL<1> to RSEL<5> is activated according to the reference selection code, one of the corresponding divided voltages VDV<1> to VDV<5> One is provided as the reference voltage VREF.

Meanwhile, the voltage level of the channel layer 19 may be changed by the intensity of current flowing between the two junctions 11 and 13 .

However, the reference voltage generator 20 does not have a storage capacitor for storing the reference voltage VREF, or even if provided, has a very small capacitance in consideration of the operating speed of the reference voltage generator 20. it is common

In this case, the reference voltage VREF is coupled to the channel layer 19 due to the parasitic capacitor Cpar. Accordingly, the level of the reference voltage VREF may change considerably according to the change in the voltage level of the channel layer 19 .

That is, in the reference transistor 10, a reference voltage fluctuation may occur due to coupling noise.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

(First embodiment)

2 is a diagram showing a buffer circuit according to a first embodiment of the present invention, buffering a received signal XIN based on a reference voltage VREF. At this time, the received signal XIN may be loaded with a plurality of unit data information DAs continuously provided (see FIG. 3), and the buffer circuit of FIG. 2 may be used as a data input buffer circuit.

The buffer circuit of FIG. 2 includes a first supply voltage VPW1, a second supply voltage VPW1, a common terminal NCOM, a first sensing terminal NSEN1, a second sensing terminal NSEN2, an enable switching transistor 110 ), a receiving transistor 130, a reference transistor 140, and a sensing amplifier 150.

In the embodiment of FIG. 2 , the first supply voltage VPW1 is the power supply voltage VDD, and the second supply voltage VPW2 is the ground voltage VSS.

The enable switching transistor 110 electrically connects the power supply voltage VDD and the common terminal NCOM in response to activation of the enable signal ENB. In the embodiment of FIG. 2 , the enable switching transistor 110 is implemented as a PMOS type transistor.

Accordingly, the common terminal NCOM is controlled from the ground voltage VSS to the power supply voltage VDD when the enable signal ENB is activated to “L”. Also, when the enable signal ENB is deactivated at “H”, the common terminal NCOM is controlled from the power supply voltage VDD to the ground voltage VSS.

The receiving transistor 130 is formed between the common terminal NCOM and the first sensing terminal NSEN1 and is gated by the receiving signal XIN. The reference transistor 140 is formed between the common terminal NCOM and the second sensing terminal NSEN2 and is gated by the reference voltage VREF.

In the embodiment of FIG. 2 , each of the receiving transistor 130 and the reference transistor 140 is implemented as a PMOS type transistor.

The voltage of the channel layer of the receiving transistor 130 and the reference transistor 140 is controlled from the ground voltage VSS to the power supply voltage VDD when the enable signal ENB is activated to “L”. , is controlled from the power supply voltage VDD side to the ground voltage VSS side when the enable signal ENB is inactivated to “H”.

The sensing amplification unit 150 is connected to the ground voltage VSS, and senses and amplifies the voltage difference between the first sensing terminal NSEN1 and the second sensing terminal NSEN2 to generate the first amplification terminal NAMP1 and the second sensing terminal NSEN2. It is provided by 2 amplification terminals (NAMP2).

Also, the voltage difference between the first amplification terminal NAMP1 and the second amplification terminal NAMP2 is amplified with respect to the voltage difference between the first sensing terminal NSEN1 and the second sensing terminal NSEN2.

Meanwhile, the receiving transistor 130 and the reference transistor 140 may be turned on by the receiving signal XIN and the reference voltage VREF, respectively, to form a channel layer. In this case, the reception signal XIN and the reference voltage VREF may be coupled to channel layers of the reception transistor 130 and the reference transistor 140 .

At this time, since the reception signal XIN is provided from an external system, etc., it has a relatively stable voltage level despite coupling by the channel layer of the reception transistor 130 .

On the other hand, as described above, since the reference voltage VREF is coupled to the channel layer of the reference transistor 140, a significant level change may occur (see t11 and t12 of FIG. 3).

In order to reduce such 'reference voltage variation according to coupling noise', the buffer circuit of FIG. 2 further includes a relaxation capacitor 160.

The relaxation capacitor 160 has one end connected to the enable signal ENB and the other end connected to the reference voltage VREF. The variation of the reference voltage VREF according to the operation of the reference transistor 140 is largely alleviated by the relaxation capacitor 160 as shown in FIG. 3 .

In this case, the relaxation capacitor 160 is preferably implemented as a PMOS type transistor having a gate terminal connected to the reference voltage VREF and a source terminal and a drain terminal connected to the enable signal ENB in common. .

Further, it is more preferable that the relaxation capacitor 160 has the same size as the reference transistor 140 . In this case, since the parasitic capacitance of the reference transistor 140 is substantially equal to the parasitic capacitance of the mitigation capacitor 160, coupling noise caused by the channel layer of the reference transistor 140 is effectively canceled.

Of course, the relaxation capacitor 160 may be implemented as an NMOS transistor having a gate terminal connected to the enable signal ENB and a source terminal and a drain terminal commonly connected to the reference voltage VREF. It is obvious to those skilled in the art. Even in this case, 'reference voltage variation due to coupling noise' is greatly reduced.

Also, in FIG. 2 , the latch unit 170 amplifies and latches the voltages of the first amplification terminal NAMP1 and the second amplification terminal NAMP2 to generate an output signal XOUT. At this time, the output signal XOUT swings to a CMOS level and has a data value that changes according to a change in the value of the unit data information DA.

The MOS transistors 181 to 184 of FIG. 2 include the first sensing terminal NSEN1 , the second sensing terminal NSEN2 , the first amplifying terminal NAMP1 and NAMP1 when the enable signal ENB is inactivated. The second amplification terminal NAMP2 is controlled by the ground voltage VSS.

In the embodiment of FIG. 2 , the first supply voltage VPW1 is the power supply voltage VDD, and the second supply voltage VPW2 is shown and described as the ground voltage VSS.

However, the technical idea according to the first embodiment of the present invention is also implemented by an embodiment in which the first supply voltage VPW1 is the ground voltage VSS and the second supply voltage VPW2 is the power supply voltage VDD. It is obvious to those skilled in the art that it can be. In this case, each of the enable switching transistor 110, the receiving transistor 130, and the reference transistor 140 is implemented as an NMOS type transistor. Also, the enable signal ENB is activated in a logic state of “H”.

Meanwhile, the technical idea according to the first embodiment of the present invention can be extended to the second embodiment.

(Second embodiment)

4 is a diagram showing a buffer circuit according to a second embodiment of the present invention, buffering the received signal XIN based on the reference voltage VREF. At this time, the received signal XIN may be loaded with a plurality of unit data information DAs continuously provided together with the sub enable signal SENB (see FIG. 6 ), and the buffer circuit of FIG. 4 is a data input buffer. can be used as a circuit.

The buffer circuit of FIG. 4 includes a plurality of buffering units 300 and a sub-enable generator 400 . At this time, the number of buffering units 300 is n. Here, n is 2 to the power of k, and k is a natural number greater than or equal to 1. In this embodiment, it is assumed that n is '4', and first to fourth buffering units 300<1> to 300<4> are provided.

Each of the first to fourth buffering units 300<1> to 300<4> is enabled in response to activation of corresponding first to fourth sub-enable signals SENB<1> to SENB<4>. do. Also, when enabled, each of the first to fourth buffering units 300<1> to 300<4> senses the voltage level of the received signal XIN with respect to the reference voltage VREF and buffers the received signal XIN.

The first to fourth buffering units 300<1> to 300<4> may be implemented in a similar configuration.

FIG. 5 is a diagram illustrating one of the plurality of buffering units 300 of FIG. 4, that is, the ith buffering unit 300<i>. Here, i is an integer from 1 to 4.

Referring to FIG. 5 , the i-th buffering unit 300<i> includes a first supply voltage VPW1, a second supply voltage VPW1, a common terminal NCOM, a first sensing terminal NSEN1, and a second supply voltage VPW1. A sensing terminal NSEN2 , an enable switching transistor 310 , a receiving transistor 330 , a reference transistor 340 and a sensing amplifier 350 are provided.

In the i-th buffering unit 300<i> of FIG. 5 , the first supply voltage VPW1 is the power supply voltage VDD, and the second supply voltage VPW2 is the ground voltage VSS.

The enable switching transistor 310 electrically connects the power supply voltage VDD and the common terminal NCOM in response to activation of the i-th sub enable signal SENB<i>. In the i-th buffering unit 300<i> of FIG. 5 , the enable switching transistor 310 is implemented as a PMOS type transistor.

Accordingly, when the i-th sub-enable signal SENB<i> is activated to “L”, the common terminal NCOM is controlled from the ground voltage VSS to the power supply voltage VDD. Also, when the ith sub-enable signal SENB<i> is deactivated to “H”, the common terminal NCOM is controlled from the power supply voltage VDD to the ground voltage VSS.

The receiving transistor 330 is formed between the common terminal NCOM and the first sensing terminal NSEN1 and is gated by the receiving signal XIN. The reference transistor 340 is formed between the common terminal NCOM and the second sensing terminal NSEN2 and is gated by the reference voltage VREF.

In the i-th buffering unit 300<i> of FIG. 5 , each of the receiving transistor 330 and the reference transistor 340 is implemented as a PMOS type transistor.

The voltage of the channel layer of the receiving transistor 330 and the reference transistor 340 is the power supply voltage at the side of the ground voltage VSS when the ith sub-enable signal SENB<i> is activated to “L”. (VDD), and is controlled from the power supply voltage VDD to the ground voltage VSS when the ith sub-enable signal SENB<i> is deactivated to “H”.

The sensing amplification unit 350 is connected to the ground voltage VSS, senses and amplifies the voltage difference between the first sensing terminal NSEN1 and the second sensing terminal NSEN2, and generates the first amplification terminal NAMP1 and the second sensing terminal NSEN2. It is provided by 2 amplification terminals (NAMP2).

Also, the voltage difference between the first amplification terminal NAMP1 and the second amplification terminal NAMP2 is amplified with respect to the voltage difference between the first sensing terminal NSEN1 and the second sensing terminal NSEN2.

In FIG. 5 , the latch unit 370 amplifies and latches the voltages of the first amplification terminal NAMP1 and the second amplification terminal NAMP2 to generate an output signal XOUT<i>. At this time, the output signal XOUT<i> swings to the CMOS level.

Also, the MOS transistors 381 to 384 of FIG. 5 provide the first sensing terminal NSEN1 , the second sensing terminal NSEN2 , and the The first amplification terminal NAMP1 and the second amplification terminal NAMP2 are controlled by the ground voltage VSS.

In the i-th buffering unit 300<i> of FIG. 5 , the first supply voltage VPW1 is a power supply voltage VDD, and the second supply voltage VPW2 is a ground voltage VSS. has been described

However, the technical idea according to the second embodiment of the present invention is also implemented by an embodiment in which the first supply voltage VPW1 is the ground voltage VSS and the second supply voltage VPW2 is the power supply voltage VDD. It is obvious to those skilled in the art that it can be. In this case, each of the enable switching transistor 310, the receiving transistor 330, and the reference transistor 340 is implemented as an NMOS type transistor. Also, the i-th sub enable signal SENB<i> is activated in a logic state of “H”.

Referring back to FIG. 4 , while the global enable signal GEN is activated, the sub-enable generator 400 sequentially activates first to fourth sub-enable signals using the data stove signal DQS. (SENB<1> to SENB<4>). That is, the first to fourth sub-enable signals SENB<1> to SENB<4> are sequentially corresponding to a plurality of unit data information DAs continuously provided to the received signal XIN. Activated.

In this embodiment, the global enable signal GEN has a logic state of “H” when activated.

The first to fourth sub-enable signals SENB<1> to SENB<4> have the same period and phase shifted by 2π/4. As a result, the first sub-enable signal SENB<1> and the third sub-enable signal SENB<3> have phases opposite to each other, and the second sub-enable signal SENB<1> and the fourth sub-enable signal (SENB<4>) have phases opposite to each other (see FIG. 6).

Since the sub-enable generation unit 400 can be easily implemented by those skilled in the art, a detailed description thereof is omitted in the present specification for simplification of description.

Referring back to FIG. 4 , the buffer circuit according to the second embodiment of the present invention further includes a relaxation capacitor 500 .

The relaxation capacitor 500 has one end connected to the reference voltage VREF and the other end connected to the preliminary signal XPRE. Here, the preliminary signal XPRE is a signal that transitions according to the transition of the global enable signal GEN, and is preferably an inverted signal of the global enable signal GEN.

Next, in the buffer circuit of FIG. 4 , 'level variation of the reference voltage due to coupling noise' is reduced, referring to FIG. 6 .

6 shows timings of the global enable signal GEN and the first to fourth sub-enable signals SENB<1> to SENB<4>.

Referring to FIG. 6 , when the global enable signal GEN is in an inactive state of “L”, all of the first to fourth sub-enable signals SENB<1> to SENB<4> are “H”. remain disabled.

At an enable start time point t_st when the global enable signal GEN transitions to activation of “H”, the first and second sub-enable signals SENB<1> and SENB<2> are The state of “H” is maintained, and the state of “L” is transitioned to by the third and fourth sub-enable signals SENB<3> and SENB<4>.

That is, at the enable start time point t_st, half of the first to fourth sub-enable signals SENB<1> to SENB<4> maintain the same logic state as before, and the other half maintains "H" transitions from the logic state of " to the logic state of "L".

The first to fourth sub-enable signals SENB<1> to SENB<4> are sequentially activated after the global enable signal GEN is activated and a predetermined preliminary time T_pr elapses.

Specifically, the first sub-enable signal SENB<1> is activated at time t21, the second sub-enable signal SENB<2> is activated at time t22, and the third sub-enable signal SENB<2> is activated. SENB<3> is activated at time t23, and the fourth sub-enable signal SENB<4> is activated at time t24.

At the enable end time point t_fn when the global enable signal GEN transitions to inactivation of “L”, the first and second sub-enable signals SENB<1> and SENB<2> are State transitions to "H", and the third and fourth sub-enable signals SENB<3> and SENB<4> maintain the "H" state.

That is, at the enable end time point t_fn, half of the first to fourth sub-enable signals SENB<1> to SENB<4> maintain the same logic state as before, and the other half maintains "L" transitions from the logic state of " to the logic state of "H".

Meanwhile, referring to FIG. 5 again, the receiving transistor 330 and the reference transistor 340 are turned on by the receiving signal XIN and the reference voltage VREF, respectively, so that a channel layer may be formed. In this case, the reception signal XIN and the reference voltage VREF may be coupled to channel layers of the reception transistor 330 and the reference transistor 340 .

At this time, since the reception signal XIN is provided from an external system or the like, it has a relatively stable voltage level despite coupling by the channel layer of the reception transistor 330 .

On the other hand, as described above, since the reference voltage VREF is coupled to the channel layer of the reference transistor 340, a significant level change may occur.

In other words, at the transition point of the ith sub-enable signal SENB<i>, 'variation in the reference voltage due to coupling noise' may occur by the ith buffering unit 300<i>. there is.

However, at each of the time points t21 to t24 of FIG. 6 , two signals among the first to fourth sub-enable signals SENB<1> to SENB<4> maintain the same logic state. The other signal transitions from the logic state of "H" to the logic state of "L", and the other signal transitions from the logic state of "L" to the logic state of "H".

That is, the number of sub-enable signals SENB transitioning from the logic state of “H” to the logic state of “L” and the number of sub-enable signals SENB transitioning from the logic state of “L” to the logic state of “H” ) is the same.

Accordingly, from the viewpoint of the entirety of the first to fourth buffering units 300<1> to 300<4>, coupling noise with respect to the reference voltage is canceled, and thus, the level of the reference voltage VREF is substantially It stays the same.

However, the enable start time t_st at which the global enable signal GEN transitions to activation of “H” and the enable end time t_fn at which the global enable signal GEN transitions to inactivation of “L” ), 'variation of the reference voltage according to coupling noise' is greatly generated.

In order to reduce the 'variation of the reference voltage due to coupling noise' at the enable start time (t_st) and the enable end time (t_fn), the buffer circuit of FIG. 4 further includes a relaxation capacitor 500. .

The relaxation capacitor 500 is preferably implemented as a PMOS type transistor having a gate terminal connected to the reference voltage VREF and a source terminal and a drain terminal commonly connected to the preliminary signal XPRE.

Of course, the relaxation capacitor 500 may be implemented as an NMOS transistor having a gate terminal connected to the preliminary signal XPRE and a source terminal and a drain terminal commonly connected to the reference voltage VREF. self-evident to Even in this case, 'variation of the reference voltage due to coupling noise' at the enable start time point (t_st) and the enable end time point (t_fn) is greatly reduced.

Meanwhile, the technical idea according to the first and second embodiments of the present invention can be extended to the third embodiment.

(Third Embodiment)

7 is a diagram showing a buffer circuit according to a third embodiment of the present invention, buffering the received signal XIN based on the reference voltage VREF. In this case, the received signal XIN may be an address signal, a command signal, and the like, and the buffer circuit of FIG. 7 may be used as an address buffer and a command buffer circuit for buffering the address signal and command signal.

The buffer circuit of FIG. 7 includes a first supply voltage VPW1, a second supply voltage VPW1, a common terminal NCOM, a first sensing terminal NSEN1, a second sensing terminal NSEN2, an enable switching transistor 610 ), a receiving transistor 630, a reference transistor 640, and a sensing amplifier 650.

In the embodiment of FIG. 7 , the first supply voltage VPW1 is the power supply voltage VDD, and the second supply voltage VPW2 is the ground voltage VSS.

The buffer circuit of FIG. 7 is enabled according to the activation of the enable signal ENB.

Specifically, the enable switching transistor 610 electrically connects the power supply voltage VDD and the common terminal NCOM according to activation of the enable signal ENB. In the embodiment of FIG. 7 , the enable switching transistor 610 is implemented as a PMOS type transistor.

Accordingly, when the enable signal ENB is activated to “L”, the common terminal NCOM is controlled from the ground voltage VSS to the power supply voltage VDD.

The receiving transistor 630 is formed between the common terminal NCOM and the first sensing terminal NSEN1 and is gated by the receiving signal XIN. The reference transistor 640 is formed between the common terminal NCOM and the second sensing terminal NSEN2 and is gated by the reference voltage VREF.

In the embodiment of FIG. 7 , each of the receiving transistor 630 and the reference transistor 640 is implemented as a PMOS type transistor.

Accordingly, when the voltage of the received signal XIN is lower than the reference voltage VREF, the first sensing terminal NSEN1 has a higher voltage level than the second sensing terminal NSEN2.

On the other hand, when the voltage of the received signal XIN is higher than the reference voltage VREF, the first sensing terminal NSEN1 has a lower voltage level than the second sensing terminal NSEN2.

The sensing amplifier 650 is connected between the power supply voltage VDD and the ground voltage VSS, and is enabled when the enable signal ENB is activated.

The sensing amplifier 650 compares voltage levels of the first sensing terminal NSEN1 and the second sensing terminal NSEN2 to generate an amplification signal XAMP. That is, the amplified signal XAMP has a logic state according to a result of comparing the voltage levels of the first sensing terminal NSEN1 and the second sensing terminal NSEN2.

Specifically, when the voltage of the received signal XIN is higher than the reference voltage VREF, the voltage of the first sensing terminal NSEN1 is lower than the voltage of the second sensing terminal NSEN2, and the The amplification signal XAMP is controlled from the power supply voltage VDD to the ground voltage VSS.

On the other hand, when the voltage of the received signal XIN is lower than the reference voltage VREF, the voltage of the first sensing terminal NSEN1 becomes higher than the voltage of the second sensing terminal NSEN2, and the amplification signal ( XAMP) is controlled from the ground voltage (VSS) side to the power supply voltage (VDD) side.

Meanwhile, the receiving transistor 630 and the reference transistor 640 may be turned on by the receiving signal XIN and the reference voltage VREF, respectively, to form a channel layer. In this case, the reception signal XIN and the reference voltage VREF may be coupled to channel layers of the reception transistor 630 and the reference transistor 640 .

At this time, the level of the reference voltage VREF may change according to the change of the received signal XIN.

For example, it is assumed that the voltage level of the received signal XIN is higher than the level of the reference voltage VREF.

Then, the voltage of the common node NCOM is lowered, the voltage of the channel layer of the reference transistor 640 is lowered, and accordingly, the level of the reference voltage VREF is also lowered.

In addition, when the voltage level of the received signal XIN is lower than the level of the reference voltage VREF, the voltage of the common node NCOM increases and the voltage of the channel layer of the reference transistor 640 increases, Accordingly, the level of the reference voltage VREF also increases.

The level change of the reference voltage VREF according to the change of the received signal XIN causes performance degradation of other buffer circuits using the reference voltage VREF.

In order to mitigate the 'influence of the level variation of the reference voltage due to coupling noise', that is, the level variation of the reference voltage VREF according to the change of the received signal XIN, the buffer circuit of FIG. A capacitor 660 is further provided.

The relaxation capacitor 660 has one end connected to the reference voltage VREF and the other end connected to the amplification signal XAMP. A level variation of the reference voltage VREF according to a change in the received signal XIN is alleviated by the mitigation capacitor 660 .

Specifically, when the voltage level of the received signal XIN becomes higher than the level of the reference voltage VREF, the level of the channel layer of the reference transistor 640 increases, and the level of the reference voltage VREF also increases. can rise

However, the amplification signal XAMP applied to the other end of the relaxation capacitor 660 is controlled from the power supply voltage VDD to the ground voltage VSS. Accordingly, the level of increase of the reference voltage VREF is reduced, and performance degradation of other buffer circuits using the reference voltage VREF is mitigated.

In addition, when the voltage level of the received signal XIN is lower than the level of the reference voltage VREF, the level of the channel layer of the reference transistor 640 may decrease, and the level of the reference voltage VREF may also decrease. there will be

However, the amplification signal XAMP applied to the other end of the relaxation capacitor 660 is controlled from the ground voltage VSS to the power supply voltage VDD. Accordingly, the drop width of the level of the reference voltage VREF is reduced, and performance degradation of other buffer circuits using the reference voltage VREF is mitigated.

As a result, the level variation of the reference voltage VREF according to the change of the received signal XIN is alleviated by the relaxation capacitor 660 .

The relaxation capacitor 660 is preferably implemented as a PMOS type transistor having a gate terminal connected to the reference voltage VREF and a source terminal and a drain terminal commonly connected to the amplification signal XAMP.

Also, while the amplification signal XAMP swings between the power supply voltage VDD and the ground voltage VSS, the channel layer of the reference transistor 640 is changed to a relatively small level. Therefore, it is more preferable that the relaxation capacitor 660 be implemented in a smaller size than the reference transistor 640 . That is, it is preferable that the relaxation capacitor 660 has a smaller parasitic capacitance than the parasitic capacitance of the reference transistor 640 .

Also, it is known to those skilled in the art that the relaxation capacitor 660 may be implemented as an NMOS type transistor having a gate terminal connected to the amplification signal XAMP and a source terminal and a drain terminal commonly connected to the reference voltage VREF. self-evident to Even in this case, the difference between the change of the received signal XIN and the reference voltage VREF is greatly reduced.

And, in FIG. 7 , the inverter 670 inverts the amplification signal XAMP to generate an output signal XOUT.

Resistors 681 to 682 of FIG. 7 control the first sensing terminal NSEN1 and the second sensing terminal NSEN2 to a ground voltage VSS when the enable signal ENB is inactivated.

In the embodiment of FIG. 7 , the first supply voltage VPW1 is the power supply voltage VDD, and the second supply voltage VPW2 is shown and described as the ground voltage VSS.

However, the technical idea according to the third embodiment of the present invention is also implemented by an embodiment in which the first supply voltage VPW1 is the ground voltage VSS and the second supply voltage VPW2 is the power supply voltage VDD. It is obvious to those skilled in the art that it can be. In this case, each of the enable switching transistor 610, the receiving transistor 630, and the reference transistor 640 is implemented as an NMOS type transistor. Also, the enable signal ENB is activated in a logic state of “H”.

As described above, although the embodiments have been described with limited examples and drawings, those skilled in the art can make various modifications and variations from the above description. For example, the described techniques may be performed in an order different from the method described, and/or components of the described system, structure, device, circuit, etc. may be combined or combined in a different form than the method described, or other components may be used. Or even if it is replaced or substituted by equivalents, appropriate results can be achieved.

For example, in this specification, an enable transistor gated on an enable signal is implemented as a PMOS formed between a common terminal and a power supply voltage, and a receive transistor and a reference transistor gated on a received signal and a reference voltage are also PMOS. The implemented PMOS-type buffer circuit has been centrally shown and described.

However, the technical idea of the present invention is that an enable transistor gated on an enable signal is implemented as an NMOS formed between a common terminal and a power supply voltage, and a receive transistor and a reference transistor gated on a receive signal and a reference voltage are also NMOS. It is obvious to those skilled in the art that it can also be implemented by the implemented NMOS type buffer circuit.

Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the attached claims.

Claims (15)

A buffer circuit for buffering a received signal based on a reference voltage,
a first supply voltage;
a second supply voltage;
common terminal;
a first sensing terminal;
a second sensing terminal;
an enable switching transistor electrically connecting the first supply voltage and the common terminal in response to activation of an enable signal;
a receiving transistor formed between the common terminal and the first sensing terminal and gated by the received signal;
a reference transistor formed between the common terminal and the second sensing terminal and gated by the reference voltage;
A sensing amplifier connected to the second supply voltage, sensing and amplifying a voltage difference between the first sensing terminal and the second sensing terminal, and providing the voltage difference between the first amplifying terminal and the second amplifying terminal, wherein the first amplifying unit a voltage difference between the terminal and the second amplification terminal is amplified with respect to a voltage difference between the first sensing terminal and the second sensing terminal; and
a buffer having one end connected to the enable signal and the other end connected to the reference voltage, the buffer for mitigating a change in the reference voltage according to the operation of the reference transistor. Circuit.
According to claim 1,
The first supply voltage is a power supply voltage,
the second supply voltage is a ground voltage;
Each of the enable switching transistor, the receiving transistor, and the reference transistor
A buffer circuit characterized in that it is a PMOS type transistor.
3. The method of claim 2, wherein the relaxation capacitor
A buffer circuit according to claim 1 , wherein the buffer circuit is a PMOS type transistor having a gate terminal connected to the reference voltage and a source terminal and a drain terminal connected to the enable signal in common.
3. The method of claim 2, wherein the relaxation capacitor
Buffer circuit according to claim 1 , wherein the buffer circuit is an NMOS type transistor having a gate terminal connected to the enable signal and a source terminal and a drain terminal connected to the reference voltage in common.
According to claim 1,
the first supply voltage is a ground voltage;
The second supply voltage is a power supply voltage,
Each of the enable switching transistor, the receiving transistor, and the reference transistor
A buffer circuit characterized in that it is an NMOS type transistor.
A buffer circuit for buffering a received signal based on a reference voltage, wherein the received signal is loaded with a plurality of unit data information continuously provided,
Enabled in response to activation of corresponding first to nth sub-enable signals (where n is 2 to the power of k, and k is a natural number greater than or equal to 1), each controlling the voltage level of the received signal with respect to the reference voltage 1st to nth buffering units for detecting and buffering, wherein the first to nth sub-enable signals have phases shifted by 2π/n in the same cycle, and are sequentially activated in response to the plurality of unit data information The first to n-th buffering units; and
a sub-enable generator for sequentially activating the first through n-th sub-enable signals while the global enable signal is activated;
Each of the first to n-th buffering units is
a first supply voltage;
a second supply voltage;
common terminal;
a first sensing terminal;
a second sensing terminal;
an enable switching transistor electrically connecting the first supply voltage and the common terminal in response to activation of the first through n-th sub-enable signals corresponding thereto;
a receiving transistor formed between the common terminal and the first sensing terminal and gated by the received signal;
a reference transistor formed between the common terminal and the second sensing terminal and gated by the reference voltage; and
A sensing amplifier connected to the second supply voltage, sensing and amplifying a voltage difference between the first sensing terminal and the second sensing terminal, and providing the voltage difference between the first amplifying terminal and the second amplifying terminal, wherein the first amplifying unit A voltage difference between the terminal and the second amplification terminal is amplified with respect to a voltage difference between the first sensing terminal and the second sensing terminal;
The buffer circuit
One end is connected to the reference voltage and the other end is connected to a preliminary signal, wherein the preliminary signal is a relaxation capacitor that transitions according to the transition of the global enable signal, and the transition of the reference voltage according to the transition of the global enable signal The buffer circuit characterized in that it further comprises the alleviation capacitor for alleviating the change.
The method of claim 6, wherein each of the first to n-th buffering units
The first supply voltage is a power supply voltage,
the second supply voltage is a ground voltage;
Each of the enable switching transistor, the receiving transistor, and the reference transistor
A buffer circuit characterized in that it is a PMOS type transistor.
8. The method of claim 7, wherein the relaxation capacitor is
A buffer circuit, characterized in that a PMOS type transistor having a gate terminal connected to the reference voltage and a source terminal and a drain terminal connected to the preliminary signal in common.
8. The method of claim 7, wherein the relaxation capacitor is
Buffer circuit according to claim 1 , wherein the buffer circuit is an NMOS type transistor having a gate terminal connected to the preliminary signal and a source terminal and a drain terminal connected to the reference voltage in common.
The method of claim 6, wherein each of the first to n-th buffering units
the first supply voltage is a ground voltage;
The second supply voltage is a power supply voltage,
Each of the enable switching transistor, the receiving transistor, and the reference transistor
A buffer circuit characterized in that it is an NMOS type transistor.
A buffer circuit for buffering a received signal based on a reference voltage,
a first supply voltage;
a second supply voltage;
common terminal;
a first sensing terminal;
a second sensing terminal;
an enable switching transistor electrically connecting the first supply voltage and the common terminal in response to activation of an enable signal;
a receiving transistor formed between the common terminal and the first sensing terminal and gated by the received signal;
a reference transistor formed between the common terminal and the second sensing terminal and gated by the reference voltage;
A sensing amplification unit formed between the first supply voltage and the second supply voltage, which is enabled in response to activation of the enable signal and compares voltage levels of the first sensing terminal and the second sensing terminal to the sensing amplification unit outputting an amplified signal, wherein the amplified signal is controlled to a logical state according to a result of comparing voltage levels between the first sensing terminal and the second sensing terminal; and
A buffer circuit comprising a relaxation capacitor having one end connected to the reference voltage and the other end connected to the amplification signal, the relaxation capacitor for mitigating a change in the reference voltage according to a change in the received signal. .
According to claim 11,
The first supply voltage is a power supply voltage,
the second supply voltage is a ground voltage;
Each of the enable switching transistor, the receiving transistor, and the reference transistor
A buffer circuit characterized in that it is a PMOS type transistor.
13. The method of claim 12, wherein the relaxation capacitor
A buffer, characterized in that a PMOS transistor implemented to have a gate terminal connected to the reference voltage, a source terminal and a drain terminal connected to the amplification signal in common, and having a parasitic capacitance smaller than the parasitic capacitance of the reference transistor Circuit.
13. The method of claim 12, wherein the relaxation capacitor
A buffer characterized in that it is an NMOS type transistor implemented to have a gate terminal connected to the amplification signal, a source terminal and a drain terminal connected to the reference voltage in common, and having a parasitic capacitance smaller than the parasitic capacitance of the reference transistor Circuit.
According to claim 11,
the first supply voltage is a ground voltage;
The second supply voltage is a power supply voltage,
Each of the enable switching transistor, the receiving transistor, and the reference transistor
A buffer circuit characterized in that it is an NMOS type transistor.

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