KR102565083B1 - Display apparatus - Google Patents

Abstract

A display device according to the present application includes a display panel having a display area including pixels connected to gate lines and a non-display area surrounding the display area, and a main stage disposed on one side of the non-display area and driving the gate lines. A first gate driver including a first gate driver, and a second gate driver including an auxiliary stage disposed on the other side opposite to one side of the non-display area and driving the gate line, wherein the area of the auxiliary stage may be smaller than that of the main stage. there is.

Description

Display device {DISPLAY APPARATUS}

This application relates to a display device.

Display devices are widely used as display screens of notebook computers, tablet computers, smart phones, portable display devices, and portable information devices in addition to display devices of televisions or monitors. Such a display device includes a liquid crystal display device and a light emitting display device. Since the light emitting display device displays an image using a self-emitting device, it has a high response speed, low power consumption, and no problem in a viewing angle, and thus has attracted attention as a next-generation display device.

The display device may include a gate driver supplying gate pulses to a plurality of gate lines, and the gate driver may sequentially shift the gate pulses applied to the plurality of gate lines using a shift register. . Also, the display device may have a Gate in Panel (GIP) structure by mounting the shift register together with the pixel array on the substrate of the display panel.

In a conventional display device, gate pulses may be supplied through a double feeding method or an interlacing method by arranging shift registers in left and right bezel regions of a substrate. At this time, the double feeding method has a problem that the design area of the shift register increases and the left and right bezel areas increase, and the interlacing method has a problem that the delay of the gate pulse occurs as the distance from the input end of the gate pulse when applied to a large panel have

The present application provides a display device capable of easily implementing high-speed driving by reducing left and right bezel areas and eliminating gate pulse delay by including a main stage disposed on one side of a gate line and an auxiliary stage disposed on the other side of the gate line. is to provide

In addition, the present application can reduce a bezel area and prevent a difference in output of gate pulses in a display area by driving a gate line through a main stage and an auxiliary stage composed of a smaller number of circuit elements than circuit elements of the main stage. It is to provide a display device with

A display device according to the present application includes a display panel having a display area including pixels connected to gate lines and a non-display area surrounding the display area, and a main stage disposed on one side of the non-display area and driving the gate lines. A first gate driver and a second gate driver including an auxiliary stage disposed on the other side opposite to one side of the non-display area to drive gate lines, wherein the auxiliary stage may have a smaller area than the main stage.

Other example details are included in the detailed description and drawings.

The display device according to the present application includes a main stage disposed on one side of a gate line and an auxiliary stage disposed on the other side of the gate line, thereby reducing a left and right bezel area and eliminating a gate pulse delay, thereby easily implementing high-speed driving. there is.

In the display device according to the present application, a gate line is driven through a main stage and an auxiliary stage having a smaller number of circuit elements than circuit elements of the main stage, thereby reducing a bezel area and preventing an output difference between gate pulses within the display area. can do.

In addition to the effects of the present application mentioned above, other features and advantages of the present application will be described below, or will be clearly understood by those skilled in the art from such description and description.

1 is a plan view illustrating a display device according to an exemplary embodiment of the present application.
FIG. 2 is a diagram illustrating a connection relationship between a gate driver, a gate line, and an emission line in the display device of FIG. 1 .
FIG. 3 is a diagram illustrating a first gate driver in the display device illustrated in FIG. 2 .
FIG. 4 is a diagram illustrating a second gate driver in the display device illustrated in FIG. 2 .
FIG. 5 is a waveform diagram illustrating a signal applied to a gate driver and a signal output from the gate driver in the display device shown in FIG. 2 .
FIG. 6 is a circuit diagram showing internal configurations of a first main stage and a first auxiliary stage shown in FIG. 2 .
FIG. 7 is a diagram explaining an effect of reducing a bezel area in the display device illustrated in FIG. 2 .

Advantages and features of the present application, and methods of achieving them, will become clear with reference to the examples described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the examples disclosed below, but will be implemented in a variety of different forms, and only these examples make the disclosure of the present invention complete, and to those skilled in the art to which the present invention belongs. It is provided to fully inform the scope of the invention, and the invention is only defined by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining examples of the present application are exemplary, the present invention is not limited to the illustrated details. Like reference numbers designate like elements throughout the specification. In addition, in describing the present application, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present application, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this application is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal precedence relationship is described in terms of 'after', 'following', 'next to', 'before', etc. It can also include non-continuous cases unless is used.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

In describing the components of the present application, terms such as first and second may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term. When an element is described as being “connected,” “coupled to,” or “connected” to another element, that element is or may be directly connected to that other element, but intervenes between each element. It will be understood that may be "interposed", or each component may be "connected", "coupled" or "connected" through other components.

Each feature of the various examples of the present application can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each example can be implemented independently of each other or can be implemented together in a related relationship. .

Hereinafter, preferred examples of the light emitting display device according to the present application will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings.

FIG. 1 is a plan view illustrating a display device according to an example of the present application, and FIG. 2 is a diagram illustrating a connection relationship between a gate driver, a gate line, and an emission line in the display device of FIG. 1 .

Referring to FIGS. 1 and 2 , the display device 10 includes a display panel 100 , a display driver 200 , and a gate driver 300 .

The display panel 100 includes a display area AA and a non-display area NA.

The display area AA is an area where an image is displayed and may be defined in the central portion of the substrate. The display area AA may correspond to an active area of the pixel array layer. For example, the display area AA includes a plurality of pixels (not shown) formed in each pixel area crossed by a plurality of gate lines GL, a plurality of emission lines EML, and a plurality of data lines DL. can be made with Here, each of the plurality of pixels may be defined as a minimum unit area emitting light.

The non-display area NA is an area in which an image is not displayed, and may be defined at an edge portion of the substrate surrounding the display area AA.

According to an example, one side of the non-display area NA can accommodate the first gate driver 310 , and the other side of the non-display area NA can accommodate the second gate driver 320 . Here, one side and the other side of the non-display area NA may respectively correspond to the left and right sides of the non-display area NA, but are not necessarily limited thereto.

Also, the other side of the non-display area NA may be connected to the display driving unit 200 and may include a pad unit (not shown) electrically connected to the display driving unit 200 . For example, another side of the non-display area NA may correspond to an upper side of the non-display area NA, and the pad part may be connected to the plurality of circuit films 210 of the display driver 200 .

The display panel 100 may further include a plurality of gate lines GL, a plurality of emission lines EML, and a plurality of data lines DL.

Each of the plurality of gate lines GL may extend long along a first direction and may be spaced apart from each other along a second direction crossing the first direction. Also, each of the plurality of gate lines GL may be driven by the first and second gate drivers 310 and 320 . For example, the plurality of gate lines GL may receive gate output signals or gate pulses from the first and second gate drivers 310 and 320 to sequentially drive each of the plurality of pixels.

The plurality of gate lines GL may include odd gate lines GL1 to GL(2n−1) and even gate lines GL2 to GL(2n). The odd gate lines GL1 to GL(2n-1) may correspond to odd-numbered gate lines among the plurality of gate lines GL, and the even gate lines GL2 to GL(2n) may correspond to even-numbered gate lines. can do.

For example, one end of the odd gate lines GL1 to GL(2n-1) is connected to the odd main stage MST1 to MST(2n-1) of the first gate driver 310 to receive a gate output signal. The other ends of the odd gate lines GL1 to GL(2n-1) may be connected to the odd auxiliary stages AST1 to AST(2n-1) of the second gate driver 320 to receive gate output signals. there is. The odd main stages (MST1 to MST(2n-1)) and the odd auxiliary stages (AST1 to AST(2n-1)) send the same gate output signal to both ends of the odd gate lines (GL1 to GL(2n-1)). can provide

Also, one end of the even gate lines GL2 to GL(2n) may be connected to the even auxiliary stages AST2 to AST(2n) of the first gate driver 310 to receive a gate output signal, and the even gate line The other ends of (GL2 to GL(2n)) may be connected to the even main stages (MST2 to MST(2n)) of the second gate driver 320 to receive gate output signals. Each of the even main stages MST2 to MST(2n) and the even auxiliary stages AST2 to AST(2n) may provide the same gate output signal to both ends of the even gate lines GL2 to GL(2n).

Each of the plurality of emission lines EML may elongate along a first direction and may be spaced apart from each other along a second direction crossing the first direction. For example, the plurality of emission lines EML may be disposed parallel to the plurality of gate lines GL, but are not necessarily limited thereto.

In addition, each of the plurality of emission lines EML may be driven by the first and second gate drivers 310 and 320 . For example, the plurality of emission lines EML may receive emission signals from the first and second gate drivers 310 and 320 to sequentially drive each of the plurality of pixels.

The plurality of emission lines EML may include odd emission lines EML1 to EML(2n−1) and even emission lines EML2 to EML(2n). The odd emission lines EML1 to EML(2n-1) may correspond to odd-numbered emission lines among the plurality of emission lines EML, and the even emission lines EML2 to EML(2n) may correspond to even-numbered emission lines. It may correspond to the emission line.

For example, one end of the odd emission lines EML1 to EML(2n-1) is connected to the odd main stage MST1 to MST(2n-1) of the first gate driver 310 to receive an emission signal. and the other ends of the odd emission lines EML1 to EML(2n-1) are connected to the odd auxiliary stages AST1 to AST(2n-1) of the second gate driver 320 to receive the emission signal can do. The odd main stage (MST1~MST(2n-1)) and the odd auxiliary stage (AST1~AST(2n-1)) send the same emission signal to both ends of the odd emission line (EML1~EML(2n-1)). can be provided to

In addition, one end of the even emission lines EML2 to EML(2n) may be connected to the even auxiliary stages AST2 to AST(2n) of the first gate driver 310 to receive an emission signal, and an even emission signal may be received. The other ends of the shunt lines EML2 to EML(2n) may be connected to the even main stage MST2 to MST(2n) of the second gate driver 320 to receive an emission signal. Each of the even main stages MST2 to MST(2n) and the even auxiliary stages AST2 to AST(2n) may provide the same emission signal to both ends of the even emission lines EML2 to EML(2n).

Each of the plurality of data lines DL may extend long along the second direction and may be spaced apart from each other along the first direction. The plurality of data lines DL may receive data voltages from the display driver 200 and control the luminance of the light emitting element of each of the plurality of pixels.

Each of the plurality of pixels may be disposed in each pixel area defined by the gate line GL and the data line DL disposed on the display area AA. According to an example, each of the plurality of pixels may include a pixel circuit having a driving transistor and a light emitting element connected to the pixel circuit.

The display driver 200 is connected to a pad provided in the non-display area NA of the display panel 100 to display an image corresponding to image data supplied from the display driving system on each pixel. According to an example, the display driver 200 may include a plurality of circuit films 210 , a plurality of data driving integrated circuits 220 , a printed circuit board 230 , and a timing controller 240 .

Input terminals provided on one side of each of the plurality of circuit films 210 are attached to the printed circuit board 230 by a film attaching process, and output terminals provided on the other side of each of the plurality of circuit films 210 are attached to the printed circuit board 230 by a film attaching process. It can be attached to the pad part. According to an example, each of the plurality of circuit films 210 may be implemented as a flexible circuit film and bent to reduce a bezel area of the display device 10 . For example, the plurality of circuit films 210 may be formed of TCP (Tape Carrier Package) or COF (Chip On Flexible Board or Chip On Film).

Each of the plurality of data driving integrated circuits 220 may be individually mounted on each of the plurality of circuit films 210 . Each of the plurality of data driving integrated circuits 220 receives pixel data and a data control signal provided from the timing controller 240, converts the pixel data into an analog data signal for each pixel according to the data control signal, and converts the corresponding pixel data into an analog data signal. You can feed the data line.

The printed circuit board 230 may support the timing controller 240 and transmit signals and power between components of the display driver 200 . The printed circuit board 230 may provide signals supplied from the timing controller 240 and driving power to the plurality of data driving integrated circuits 220 and the scan driving circuit 220 in order to display an image in each pixel. To this end, signal transmission wires and various power wires may be provided on the printed circuit board 230 . For example, one or more printed circuit boards 230 may be formed according to the number of circuit films 210 .

The timing controller 240 may be mounted on the printed circuit board 230 and receive image data and a timing synchronization signal provided from the display driving system through a user connector provided on the printed circuit board 230 . The timing controller 240 may generate pixel data by arranging image data to fit the pixel arrangement structure based on the timing synchronization signal, and may provide the generated pixel data to the corresponding data driving integrated circuit 220 . Further, the timing controller 240 generates a data control signal and a gate control signal, respectively, based on the timing synchronization signal, controls the driving timing of each of the plurality of data driving integrated circuits 220 through the data control signal, and controls the gate. The driving timing of the gate driver 300 may be controlled through a signal. Here, the gate control signal may be supplied to the corresponding gate driver 300 through the first or/or last flexible circuit film among the plurality of circuit films 210 and the non-display area NA.

The gate driver 300 may be connected to the plurality of gate lines GL and the plurality of emission lines EML provided on the display panel 100 . For example, the gate driver 300 may generate a gate output signal or a gate pulse according to a predetermined order based on a gate control signal supplied from the timing controller 240 and supply the generated gate output signal or gate pulse to a corresponding gate line GL. In addition, the gate driver 300 may generate an emission signal according to a predetermined order based on the emission control signal supplied from the timing controller 240 and supply the emission signal to the corresponding emission line EML.

According to one example, the gate driving unit 300 may include first and second gate driving units 310 and 320 .

The first gate driver 310 includes odd main stages MST1 to MST(2n-1) corresponding to odd gate lines GL1 to GL(2n-1) and even gate lines GL2 to GL(2n). Even auxiliary stages (AST2 to AST(2n)) corresponding to each may be included. According to an example, the first gate driver 310 may be integrated on the left edge of the display panel 100 according to the manufacturing process of the thin film transistor, and the odd main stages MST1 to MST(2n-1) may have odd gates. The even auxiliary stages AST2 to AST(2n) may be connected to the even gate lines GL2 to GL(2n) in one-to-one connection. As such, the first gate driver 310 may include odd main stages MST1 to MST(2n−1) and even auxiliary stages AST2 to AST(2n) alternately disposed with each other. The first gate driver 310 may provide a gate output signal to one end of the plurality of gate lines GL.

Further, each of the odd main stages MST1 to MST(2n-1) of the first gate driver 310 may correspond to the odd emission lines EML1 to EML(2n-1), and the even auxiliary stage AST2 Each of ~AST(2n)) may correspond to an even emission line (EML2~EML(2n)). The odd main stages MST1 to MST(2n-1) and the even auxiliary stages AST2 to AST(2n) may provide emission signals to one end of the plurality of emission lines EML.

The second gate driver 320 includes odd sub-stages AST1 to AST(2n-1) and even gate lines GL2 to GL(2n) corresponding to the odd gate lines GL1 to GL(2n-1). It may include even main stages MST2 to MST(2n) corresponding to each. According to an example, the second gate driver 320 may be integrated on the right edge of the display panel 100 according to the manufacturing process of the thin film transistor, and the odd auxiliary stages AST1 to AST(2n-1) are odd gates. The even main stages MST2 to MST(2n) may be connected to the even gate lines GL2 to GL(2n) in one-to-one connection. As such, the second gate driver 320 may include odd auxiliary stages AST1 to AST(2n−1) and even main stages MST2 to MST(2n) alternately disposed with each other. The second gate driver 320 may provide a gate output signal to the other end of the plurality of gate lines GL. Accordingly, each of the first and second gate drivers 310 and 320 may provide the same gate output signal to both ends of each of the plurality of gate lines GL.

Further, each of the odd auxiliary stages AST1 to AST(2n-1) of the second gate driver 320 may correspond to the odd emission lines EML1 to EML(2n-1), and the even main stage MST2 Each of ~MST(2n) may correspond to an even emission line EML2~EML(2n). The odd auxiliary stages AST1 to AST(2n-1) and the even main stages MST2 to MST(2n) may provide an emission signal to the other end of the plurality of emission lines EML. Accordingly, each of the first and second gate drivers 310 and 320 may provide the same emission signal to both ends of each of the plurality of emission lines EML.

FIG. 3 is a diagram illustrating a first gate driver in the display device illustrated in FIG. 2 .

Referring to FIG. 3 , the first gate driver 310 supplies an odd gate output signal (or gate pulse) to the odd gate lines GL1 to GL(2n-1) (MST1 to MST(2n-1)). )) and even auxiliary stages AST2 to AST(2n) supplying gate output signals (or gate pulses) to the even gate lines GL2 to GL(2n). For example, the first gate driver 310 may include the number of odd main stages MST1 to MST(2n-1) corresponding to the total number of odd gate lines GL1 to GL(2n-1). and the number of even auxiliary stages AST2 to AST(2n) corresponding to the total number of even gate lines GL2 to GL(2n). Also, the gate output signal may swing between the gate high voltage (VGH) and the gate low voltage (VGL).

The odd main stages MST1 to MST(2n-1) of the first gate driver 310 receive the gate high voltage VGH and gate low voltage VGL from the common signal line CGS provided from the display driver 200. and receive the first clock signal CLK1 from the clock line CL. Also, the even auxiliary stages AST2 to AST(2n) may receive the gate high voltage VGH from the common signal line CGS provided from the display driver 200, and may receive first and second gate high voltages VGH from the clock line CL. 2 clock signals CLK1 and CLK2 can be received. Here, the first and second clock signals CLK1 and CLK2 may have sequentially shifted phases.

According to an example, the first main stage MST1 is enabled by the gate start signal GVST to receive the first clock signal CLK1, the gate high voltage VGH, and the gate low voltage VGL. The first gate output signal Gout1 may be provided to one end of the first gate line GL1. Also, the first main stage MST1 may provide the first gate output signal Gout1 to the second auxiliary stage AST2, and the first gate output signal Gout1 may be applied to the gate in the second auxiliary stage AST2. It can serve as a start signal.

The second auxiliary stage AST2 is enabled by the first gate output signal Gout1 to receive the first and second clock signals CLK1 and CLK2 and the gate high voltage VGH. The gate output signal Gout2 may be provided to one end of the second gate line GL2. Also, the second auxiliary stage AST2 may provide the second gate output signal Gout2 to the third main stage MST3, and the second gate output signal Gout2 may be a gate in the third main stage MST3. It can serve as a start signal.

In this way, the third to 2n−1 main stages MST3 to MST(2n−1) and the fourth to 2n auxiliary stages AST4 to AST(2n) are each connected by the gate output signal of the previous stage. It is enabled to selectively receive the first and second clock signals CLK1 and CLK2, the gate high voltage VGH, and the gate low voltage VGL, and the third to 2n gate lines GL3 to GL (2n)), gate output signals Gout3 to Gout(2n) may be provided to each.

Each of the odd main stages MST1 to MST(2n-1) of the first gate driver 310 sends an emission signal EM1 to EM(2n-1) to an odd emission line EML1 to EML(2n-1). ), and each of the even auxiliary stages AST2 to AST(2n) may provide the emission signals EM2 to EM(2n) to the even emission lines EML2 to EML(2n). For example, the total number of odd main stages MST1 to MST(2n-1) of the first gate driver 310 may correspond to the total number of odd emission lines EML1 to EML(2n-1). , and the total number of even auxiliary stages AST2 to AST(2n) may correspond to the total number of even emission lines EML2 to EML(2n). For example, the emission signal may swing between a gate high voltage (VGH) and a gate low voltage (VGL), but is not necessarily limited thereto.

According to an example, the first main stage MST1 is enabled by the emission start signal EVST to receive the first clock signal CLK1, the gate high voltage VGH, and the gate low voltage VGL. and the first emission signal EM1 can be provided to one end of the first emission line EML1. Also, the first main stage MST1 may provide the first emission signal EM1 to the second auxiliary stage AST2, and the first emission signal EM1 may transmit the first emission signal EM1 to the second auxiliary stage AST2. It may serve as a start signal.

The second auxiliary stage AST2 is enabled by the first emission signal EM1 to receive the first and second clock signals CLK1 and CLK2 and the gate high voltage VGH. The emission signal EM2 may be provided to one end of the second emission line EML2. Also, the second auxiliary stage AST2 may provide the second emission signal EM2 to the third main stage MST3, and the second emission signal EM2 may transmit the second emission signal EM2 to the third main stage MST3. It may serve as a start signal.

In this way, each of the third to 2n−1 main stages MST3 to MST(2n−1) and the fourth to 2n auxiliary stages AST4 to AST(2n) is generated by the emission signal of the previous stage. It is enabled to selectively receive the first and second clock signals CLK1 and CLK2, the gate high voltage VGH, and the gate low voltage VGL, and the third to 2n emission lines EML3 to Emission signals EM3 to EM(2n) may be provided to each of the EMLs 2n.

FIG. 4 is a diagram illustrating a second gate driver in the display device illustrated in FIG. 2 .

Referring to FIG. 4 , the second gate driver 320 includes odd auxiliary stages AST1 to AST(2n-1) supplying gate output signals (or gate pulses) to odd gate lines GL1 to GL(2n-1). )) and even main stages MST2 to MST(2n) supplying gate output signals (or gate pulses) to the even gate lines GL2 to GL(2n). For example, the second gate driver 320 may include odd auxiliary stages AST1 to AST(2n-1) corresponding to the total number of odd gate lines GL1 to GL(2n-1). and the number of even main stages MST2 to MST(2n) corresponding to the total number of even gate lines GL2 to GL(2n). Also, the gate output signal may swing between the gate high voltage (VGH) and the gate low voltage (VGL).

The odd auxiliary stages AST1 to AST(2n-1) of the second gate driver 320 may receive the gate high voltage VGH from the common signal line CGS provided from the display driver 200, and may receive the gate high voltage VGH from the clock line. The first and second clock signals CLK1 and CLK2 may be received from CL. Also, the even main stages MST2 to MST(2n) may receive the gate high voltage VGH and the gate low voltage VGL from the common signal line CGS provided from the display driver 200, and the clock line ( The second clock signal CLK2 may be received from CL). Here, the first and second clock signals CLK1 and CLK2 may have sequentially shifted phases.

According to an example, the first auxiliary stage AST1 is enabled by the gate start signal GVST to receive the first and second clock signals CLK1 and CLK2 and the gate high voltage VGH. , the first gate output signal Gout1 may be provided to the other end of the first gate line GL1. Also, the first auxiliary stage AST1 may provide the first gate output signal Gout1 to the second main stage MST2, and the first gate output signal Gout1 may be applied to the gate in the second main stage MST2. It can serve as a start signal.

The second main stage MST2 is enabled by the first gate output signal Gout1 to receive the second clock signal CLK2, the gate high voltage VGH, and the gate low voltage VGL. The second gate output signal Gout2 may be applied to the other end of the second gate line GL2. Also, the second main stage MST2 may provide the second gate output signal Gout2 to the third auxiliary stage AST3, and the second gate output signal Gout2 may be passed to the gate in the third auxiliary stage AST3. It can serve as a start signal.

In this way, each of the third to 2n−1 auxiliary stages (AST3 to AST(2n−1)) and the fourth to 2n main stages (MST4 to MST(2n)) are connected by the gate output signal of the previous stage. It is enabled to selectively receive the first and second clock signals CLK1 and CLK2, the gate high voltage VGH, and the gate low voltage VGL, and the third to 2n gate lines GL3 to GL (2n)), gate output signals Gout3 to Gout(2n) may be provided to each.

Each of the odd auxiliary stages AST1 to AST(2n-1) of the second gate driver 320 generates an emission signal EM1 to EM(2n-1) to an odd emission line EML1 to EML(2n-1). ), and each of the even main stages MST2 to MST(2n) may provide the emission signals EM2 to EM(2n) to the even emission lines EML2 to EML(2n). For example, the total number of odd auxiliary stages AST1 to AST(2n-1) of the second gate driver 320 may correspond to the total number of odd emission lines EML1 to EML(2n-1). The total number of even main stages MST2 to MST(2n) may correspond to the total number of even emission lines EML2 to EML(2n). For example, the emission signal may swing between a gate high voltage (VGH) and a gate low voltage (VGL), but is not necessarily limited thereto.

According to an example, the first auxiliary stage AST1 is enabled by the emission start signal EVST to receive the first and second clock signals CLK1 and CLK2 and the gate high voltage VGH. and may provide the first emission signal EM1 to the other end of the first emission line EML1. Also, the first auxiliary stage AST1 may provide the first emission signal EM1 to the second main stage MST2, and the first emission signal EM1 may be transmitted to the second main stage MST2. It may serve as a start signal.

The second main stage MST2 is enabled by the first emission signal EM1 to receive the second clock signal CLK2, the gate high voltage VGH, and the gate low voltage VGL. The second emission signal EM2 may be provided to the other end of the second emission line EML2. Also, the second main stage MST2 may provide the second emission signal EM2 to the third auxiliary stage AST3, and the second emission signal EM2 may transmit the second emission signal EM2 to the third auxiliary stage AST3. It may serve as a start signal.

In this way, each of the third to 2n−1 auxiliary stages (AST3 to AST(2n−1)) and the fourth to 2n main stages (MST4 to MST(2n)) are generated by the emission signal of the previous stage. It is enabled to selectively receive the first and second clock signals CLK1 and CLK2, the gate high voltage VGH, and the gate low voltage VGL, and the third to 2n emission lines EML3 to Emission signals EM3 to EM(2n) may be provided to each of the EMLs 2n.

5 is a waveform diagram illustrating a signal applied to a gate driver and a signal output from the gate driver in the display device shown in FIG. 2 , and FIG. 6 is a diagram illustrating insides of a first main stage and a first auxiliary stage shown in FIG. 2 . It is a circuit diagram showing the configuration.

5 and 6 , the first main stage MST1 may include a first gate driving circuit GDC1 and a first emission driving circuit EDC1, and the first auxiliary stage AST1 may It may include a 2 gate driving circuit (GDC2) and a second emission driving circuit (EDC2).

The first gate driving circuit GDC1 of the first main stage MST1 receives the gate start signal GVST, the first clock signal CLK1, the gate high voltage VGH, and the gate low voltage VGL to control One gate output signal Vout1 may be provided to one end of the first gate line GL1. For example, the first gate driving circuit GDC1 may include a first node controller NC1 , first and second thin film transistors T1 and T2 , and a first capacitor C1 .

The first node controller NC1 controls voltages of the first node Q1 and the second node QB1 based on the gate start signal GVST, the gate high voltage VGH, and the gate low voltage VGL. You can control it. Here, the gate high voltage VGH may have a high potential voltage level to be used as a scan signal for driving a pixel, and the gate low voltage VGL may have a low potential voltage level.

According to an example, the first node control unit NC1 may charge the first node Q1 with the gate high voltage VGH based on the high-level gate start signal GVST, and may charge the second node QB1. may be discharged to the gate low voltage VGL based on the gate high voltage VGH charged in the first node Q1. Also, the first node controller NC1 can discharge the first node Q1 to the gate low voltage VGL based on the low-level gate start signal GVST, and generate a gate high voltage to the second node QB1. Voltage VGH can be provided. For example, the first node controller NC1 receives the gate start signal GVST, the gate high voltage VGH, and the gate low voltage VGL, and converts the voltage of the first node Q1 to the second node ( It can be controlled to be opposite to the voltage of QB1).

The first thin film transistor T1 may include a gate terminal connected to the first node Q1, a first terminal receiving the first clock signal CLK1, and a second terminal connected to the first output node O1. there is. Here, the first output node O1 may be connected to one end of the first gate line GL1. For example, the first thin film transistor T1 can be turned on based on the voltage of the first node Q1 and uses the first clock signal CLK1 as the first gate output signal Gout1 as the first output node. (O1) can be provided. Also, the first gate output signal Gout1 may be supplied as a gate start signal of the second auxiliary stage AST2. For example, the second auxiliary stage AST2 may be driven in the same manner as the first auxiliary stage AST1 by receiving the first gate output signal Gout1 of the first main stage MST1 as a gate start signal. there is.

The second thin film transistor T2 may include a gate terminal connected to the second node QB1 , a first terminal connected to the first output node O1 , and a second terminal receiving the gate low voltage VGL. . For example, the second thin film transistor T2 may be turned on based on the voltage of the second node QB1 to discharge the voltage of the first output node O1 to the gate low voltage VGL.

Also, one end of the first capacitor C1 may be connected to the first node Q1, and the other end of the first capacitor C1 may be connected to the first output node O1. Accordingly, the first capacitor C1 may store a difference voltage between the first node Q1 and the first output node O1.

The second gate driving circuit GDC2 of the first auxiliary stage AST1 receives the gate start signal GVST and the first and second clock signals CLK1 and CLK2 and outputs the first gate output signal Vout1 to the first It may be provided at the other end of the gate line GL1. For example, the second gate driving circuit GDC2 may include third and fourth thin film transistors T3 and T4 and a third capacitor C3.

The third thin film transistor T3 may include a gate terminal connected to the third node Q3, a first terminal receiving the first clock signal CLK1, and a second terminal connected to the second output node O2. there is. Here, the second output node O2 may be connected to the other end of the first gate line GL1. For example, the third thin film transistor T3 can be turned on based on the voltage of the third node Q3 and uses the first clock signal CLK1 as the first gate output signal Gout1 as the second output node. (O2) can be provided. In this way, the first auxiliary stage AST1 applies the same output signal as the first gate output signal Gout1 provided to one end of the first gate line GL1 from the first main stage MST1 to the first gate line GL1. ) can be provided at the other end. Also, the first gate output signal Gout1 may be supplied as a gate start signal of the second main stage MST2. For example, the second main stage MST2 may be driven in the same manner as the first main stage MST1 by receiving the first gate output signal Gout1 of the first auxiliary stage AST1 as a gate start signal. there is.

The fourth thin film transistor T4 may include a gate terminal receiving the second clock signal CLK2, a first terminal receiving the gate start signal GVST, and a second terminal connected to the third node Q3. there is. For example, the fourth thin film transistor T4 may be turned on based on the second clock signal CLK2 to charge the gate start signal GVST to the third node Q3. Here, the rising time of the gate start signal GVST may be synchronized with the rising time of the second clock signal CLK2. Also, one end of the third capacitor C3 is connected to the third node Q3 and the other end of the third capacitor C3 is connected to the second output node O2, so that the third capacitor C3 is connected to the third node A difference voltage between Q3 and the second output node O2 may be stored. Accordingly, the fourth thin film transistor T4 receives the gate start signal GVST based on the second clock signal CLK2 so that the voltage of the third node Q3 is synchronized with the voltage of the first node Q1. You can control it.

In this way, the first sub-stage AST1 is composed of fewer circuit elements than the circuit elements of the first main stage MST1, so that the area of the first sub-stage AST1 is the area of the first main stage MST1. may be smaller than For example, the area of the first main stage MST1 may be larger than that of the first auxiliary stage AST1 by the area of the first node controller NC1. Accordingly, the display device 10 according to the present application includes the first main stage MST1 and the first auxiliary stage AST1 including circuit elements smaller than those of the first main stage MST1. By driving the gate line GL1, a bezel area can be reduced and an output difference between gate output signals within the display area can be prevented.

An operation of the first gate driving circuit GDC1 of the first main stage MST1 according to an example of the present application will be described with reference to FIGS. 5 and 6 .

First, when the gate start signal GVST has a high level, the first node controller NC1 can charge the first node Q1 with the gate high voltage VGH and set the second node QB1 to the gate low. It can be discharged with voltage (VGL). Here, the first capacitor C1 stores the difference voltage between the first node Q1 and the first output node O1 so that the first clock signal CLK1 is transmitted through the first thin film transistor T1. The voltage of the first node Q1 may be maintained at the gate high voltage VGH until the first voltage is supplied to the output node O1. Also, the first node controller NC1 may maintain the voltage of the second node QB1 at the gate low voltage VGL based on the voltage of the first node Q1 at the high level.

Next, when the gate start signal GVST has a low level and the first clock signal CLK1 has a high level, the first clock signal CLK1 is still turned-on via the first thin film transistor T1. It may be applied to the first output node O1, which is the other end of the first capacitor C1. Accordingly, the first node Q1, which is one end of the first capacitor C1, may be bootstrapping to have a voltage higher than the gate high voltage VGH. Therefore, the first thin film transistor T1 is fully turned on and can supply the first clock signal CLK1 as the first gate output signal Gout1 to one end of the first gate line GL1 without voltage loss. . At this time, the voltage of the second node QB1 may still be maintained at the gate low voltage VGL.

Finally, when both the gate start signal GVST and the first clock signal CLK1 have low-level voltages, the first node controller NC1 converts the voltage of the first node Q1 to the gate low voltage VGL. can discharge. Accordingly, the first thin film transistor T1 may be turned off and not provide the first clock signal CLK1 to the first output node O1. Also, the first node controller NC1 may turn on the second thin film transistor T2 by providing the gate high voltage VGL to the second node QB1, and may turn on the voltage of the first output node O1. can be discharged with the gate low voltage (VGL). As a result, the first gate driving circuit GDC1 may provide the gate-off voltage to the first gate line GL1 when the voltage of the first output node O1 is discharged to the gate low voltage VGL.

An operation of the second gate driving circuit GDC2 of the first auxiliary stage AST1 according to an example of the present application will be described as follows.

First, the rising time of the gate start signal GVST may be synchronized with the rising time of the second clock signal CLK2. For example, the fourth thin film transistor T4 may be turned on by the second clock signal CLK2 when the gate start signal GVST has a high level, and the gate start signal is applied to the third node Q3. (GVST) can be charged. Here, the third capacitor C3 stores the difference voltage between the third node Q3 and the second output node O2 so that the first clock signal CLK1 is transmitted through the third thin film transistor T3. The voltage of the third node Q3 may be maintained as the gate start signal GVST until it is supplied to the second output node O2. Here, the high-level gate start signal GVST has the same magnitude as the gate high voltage VGH, so that the second gate driving circuit GDC2 applies the voltage of the third node Q3 to the first node Q1. can be kept equal to the voltage of

Next, when the gate start signal GVST has a low level and the first clock signal CLK1 has a high level, the first clock signal CLK1 is still turned-on via the third thin film transistor T3. It may be applied to the second output node O2, which is the other end of the third capacitor C3. Accordingly, the third node Q3, which is one end of the third capacitor C3, may be bootstrapping to have a higher level voltage than the gate start signal GVST. Also, since the voltage of the third node Q3 is bootstrapped by the magnitude of the first clock signal CLK1, the voltage of the bootstrapped third node Q3 is maintained equal to the voltage of the first node Q1. can Therefore, the third thin film transistor T3 is fully turned on and can supply the first clock signal CLK1 as the first gate output signal Gout1 to the other end of the first gate line GL1 without voltage loss. . As described above, the second gate driving circuit GDC2 applies the same output signal as the first gate output signal Gout1 provided to one end of the first gate line GL1 from the first gate driving circuit GDC1 to the first gate line. It can be provided at the other end of (GL1).

Finally, when the second clock signal CLK2 has a high level voltage and the gate start signal GVST has a low level voltage, the fourth thin film transistor T4 turns based on the second clock signal CLK2. - By being turned on, the voltage of the third node Q3 can be discharged to the low-level gate start signal GVST. Here, the low-level gate start signal GVST has the same magnitude as the gate low voltage VGL, so that the second gate driving circuit GDC2 applies the voltage of the third node Q3 to the first node Q1. can be kept equal to the voltage of Accordingly, the third thin film transistor T3 may be turned off and not provide the first clock signal CLK1 to the second output node O2. Also, the second gate driving circuit GDC2 may discharge the second output node O2, which is the other end of the third capacitor C3, by discharging the third node Q3, which is one end of the third capacitor C3. there is. As a result, the second gate driving circuit GDC2 may provide a gate-off voltage to the first gate line GL1 when the voltage of the second output node O2 is discharged to the gate low voltage VGL.

Accordingly, in the display device 10 according to the present application, the first gate driving circuit GDC1 of the first main stage MST1 and the second gate driving circuit GDC2 of the first auxiliary stage AST1 By providing the same first gate output signal Gout1 to both ends of the line GL1, delay in the first gate output signal Gout1 is prevented, so that an output difference between both ends of the first gate line GL1 occurs. occurrence can be prevented. Accordingly, the display device 10 according to the present application prevents occurrence of a delay even when driven at high speed (or driven at a high frequency), thereby easily implementing high-speed driving even on a large panel and improving image quality.

The first emission driving circuit EDC1 of the first main stage MST1 receives the emission start signal EVST, the first clock signal CLK1, the gate high voltage VGH, and the gate low voltage VGL. Thus, the first emission signal EM1 may be provided to one end of the first emission line EML1. For example, the first emission driving circuit EDC1 may include a second node controller NC2, fifth and sixth thin film transistors T5 and T6, and a fourth capacitor C4.

The second node controller NC2 controls the voltages of the fourth node Q4 and the fifth node QB4 based on the emission start signal EVST, the first clock signal CLK1, and the gate low voltage VGL. voltage can be controlled.

According to an example, the second node control unit NC2 may charge the first clock signal CLK1 to the fourth node Q4 based on the high-level emission start signal EVST, and the fifth node ( QB4) may be discharged to the gate low voltage VGL based on the first clock signal CLK1 charged in the fourth node Q4. Further, the second node controller NC2 may discharge the fourth node Q4 to the gate low voltage VGL based on the low-level emission start signal EVST, and the fifth node QB4 may discharge the second node QB4. 1 clock signal CLK1 may be provided. For example, the second node controller NC2 receives the emission start signal EVST, the first clock signal CLK1, and the gate low voltage VGL, and sets the voltage of the fourth node Q4 to a fifth voltage. It can be controlled to be opposite to the voltage of node QB4.

The fifth thin film transistor T5 may include a gate terminal connected to the fourth node Q4, a first terminal receiving the gate high voltage VGH, and a second terminal connected to the third output node O3. . Here, the third output node O3 may be connected to one end of the first emission line EML1. For example, the fifth thin film transistor T5 may be turned on based on the voltage of the fourth node Q4, and the gate high voltage VGH is used as the first emission signal EM1 by the third output node ( O3) can be provided. Also, the first emission signal EM1 may be supplied as an emission start signal of the second auxiliary stage AST2. For example, the second auxiliary stage AST2 is driven in the same manner as the first auxiliary stage AST1 by receiving the first emission signal EM1 of the first main stage MST1 as an emission start signal. can

The sixth thin film transistor T6 may include a gate terminal connected to the fifth node QB4, a first terminal connected to the third output node O3, and a second terminal receiving the gate low voltage VGL. . For example, the sixth thin film transistor T6 may be turned on based on the voltage of the fifth node QB4 to discharge the voltage of the third output node O3 to the gate low voltage VGL.

Also, one end of the fourth capacitor C4 may be connected to the fourth node Q4, and the other end of the fourth capacitor C4 may be connected to the third output node O3. Accordingly, the fourth capacitor C4 may store a difference voltage between the fourth node Q4 and the third output node O3.

The second emission driving circuit EDC2 of the first auxiliary stage AST1 receives the emission start signal EVST, the first clock signal CLK1, and the gate high voltage VGH to generate the first emission signal ( EM1) may be provided to the other end of the first emission line EML1. For example, the second emission driving circuit EDC2 may include seventh and eighth thin film transistors T7 and T8 and a sixth capacitor C6.

The seventh thin film transistor T7 may include a gate terminal connected to the sixth node Q6, a first terminal receiving the gate high voltage VGH, and a second terminal connected to the fourth output node O4. . Here, the fourth output node O4 may be connected to the other end of the first emission line EML1. For example, the seventh thin film transistor T7 may be turned on based on the voltage of the sixth node Q6, and the gate high voltage VGH is used as the first emission signal EM1 by the fourth output node ( O4) can be provided. As such, the first auxiliary stage AST1 transmits the same output signal as the first emission signal EM1 provided to one end of the first emission line EML1 from the first main stage MST1 to the first emission line. It can be provided at the other end of (EML1). Also, the first emission signal EM1 may be supplied as an emission start signal of the second main stage MST2. For example, the second main stage MST2 is driven in the same manner as the first main stage MST1 by receiving the first emission signal EM1 of the first auxiliary stage AST1 as an emission start signal. can

The eighth thin film transistor T8 may include a gate terminal receiving the first clock signal CLK1, a first terminal receiving the emission start signal EVST, and a second terminal connected to the sixth node Q6. can For example, the eighth thin film transistor T8 may be turned on based on the first clock signal CLK1 to charge the sixth node Q6 with the emission start signal EVST. Here, the rising time of the emission start signal EVST may be synchronized with the rising time of the first clock signal CLK1. And, one end of the sixth capacitor C6 is connected to the sixth node Q6 and the other end of the sixth capacitor C6 is connected to the fourth output node O4, so that the sixth capacitor C6 is connected to the sixth node A difference voltage between Q6 and the fourth output node O4 may be stored. Accordingly, the eighth thin film transistor T8 synchronizes the voltage of the sixth node Q6 with the voltage of the fourth node Q4 by receiving the emission start signal EVST based on the first clock signal CLK1. can be controlled as much as possible.

In this way, the first sub-stage AST1 is composed of fewer circuit elements than the circuit elements of the first main stage MST1, so that the area of the first sub-stage AST1 is the area of the first main stage MST1. may be smaller than For example, the area of the first main stage MST1 may be larger than that of the first auxiliary stage AST1 by the area of the first node controller NC1. Accordingly, the display device 10 according to the present application includes the first main stage MST1 and the first auxiliary stage AST1 including circuit elements smaller than those of the first main stage MST1. By driving the emission line EML1, it is possible to reduce the bezel area and prevent the output difference of the emission signals within the display area.

In addition, an operation of the first emission driving circuit EDC1 of the first main stage MST1 according to an example of the present application will be described as follows.

First, when the emission start signal EVST has a high level, the second node control unit NC2 can charge the fourth node Q4 with the first clock signal CLK1 and charge the fifth node QB4. It can be discharged with the gate low voltage (VGL). Here, the fourth capacitor (C4) stores the difference voltage between the fourth node (Q4) and the third output node (O3), so that while the emission start signal (EVST) has a high level, the first clock signal ( CLK1) may be periodically charged to the fourth node Q4. Accordingly, the voltage of the fourth node Q4 may maintain the high level from the rising point of the first clock signal CLK1 after the emission start signal EVST has the high level, and the fifth thin film transistor T5 may provide the gate high voltage VGH as the first emission signal EM1 to the third output node O3 based on the voltage of the fourth node Q4.

Next, when the first clock signal CLK1 has a high level after the emission start signal EVST has a low level, the second node controller NC2 converts the voltage of the fourth node Q4 to a gate low voltage ( VGL) can be discharged. Accordingly, the fifth thin film transistor T5 may be turned off and may not provide the gate high voltage VGH to the third output node O3. Also, the second node control unit NC2 may turn on the sixth thin film transistor T6 by providing the first clock signal CLK1 to the fifth node QB4, and may turn on the third output node O3. The voltage may be discharged to the gate low voltage (VGL). As a result, the first emission driving circuit EDC1 may provide an emission off signal to the first emission line EML1 when the voltage of the third output node O3 is discharged to the gate low voltage VGL. there is.

An operation of the second emission driving circuit EDC2 of the first auxiliary stage AST1 according to an example of the present application will be described as follows.

First, the rising time of the emission start signal EVST may be synchronized with the rising time of the first clock signal CLK1. For example, the eighth thin film transistor T8 may be turned on by the first clock signal CLK1 when the emission start signal EVST has a high level, and the sixth node Q6 emits an emission signal. The start signal EVST may be charged. Here, the sixth capacitor C6 stores the difference voltage between the sixth node Q6 and the fourth output node O4, so that whenever the first clock signal CLK1 has a high level, the emission start signal is generated. (EVST) may be periodically charged to the sixth node Q6. Accordingly, the voltage of the sixth node Q6 may maintain a high level from the rising point of the first clock signal CLK1 after the emission start signal EVST has a high level, and the seventh thin film transistor T7 may provide the gate high voltage VGH based on the voltage of the sixth node Q6 to the fourth output node O4 as the first emission signal EM1.

Next, when the first clock signal CLK1 has a high level after the emission start signal EVST has a low level, the eighth thin film transistor T8 is turned on based on the first clock signal CLK1. As a result, the voltage of the sixth node Q6 can be discharged to the low-level emission start signal EVST. Here, the low-level emission start signal EVST has the same magnitude as the gate low voltage VGL, so that the second emission driving circuit EDC2 converts the voltage of the sixth node Q6 to the fourth node ( It can be kept the same as the voltage of Q4). Accordingly, the seventh thin film transistor T7 may be turned off and not provide the gate high voltage VGH to the fourth output node O4 . In addition, the second emission driving circuit EDC2 discharges the fourth output node O4, which is the other end of the sixth capacitor C6, by discharging the sixth node Q6, which is one end of the sixth capacitor C6. can As a result, the second emission driving circuit EDC2 may provide an emission off signal to the first emission line EML1 when the voltage of the fourth output node O4 is discharged to the gate low voltage VGL. there is.

Accordingly, the display device 10 according to the present application provides the first emission driving circuit EDC1 of the first main stage MST1 and the second emission driving circuit EDC2 of the first auxiliary stage AST1. 1 By providing the same first emission signal EM1 to both ends of the first emission line EML1, delay in the first emission signal EM1 is prevented, so that both ends of the first gate line GL1 It is possible to prevent an output difference from occurring. Accordingly, the display device 10 according to the present application prevents occurrence of a delay even when driven at high speed (or driven at a high frequency), thereby easily implementing high-speed driving even on a large panel and improving image quality.

FIG. 7 is a diagram explaining an effect of reducing a bezel area in the display device illustrated in FIG. 2 .

Referring to FIG. 7 , a conventional display device having a large panel supplies gate output signals or gate pulses to a plurality of gate lines through a double feeding method or an interlacing method.

For example, in a conventional display device driven by a double feeding method, each of a plurality of stages ST1 to ST4 is disposed in left and right bezel areas of a substrate. At this time, the conventional display device has a problem in that the left and right bezel areas increase by the width w1 of the plurality of stages ST1 to ST4. Such a conventional display device has a problem in that a bezel area increases as the gate driver is driven at a high speed (or high frequency).

To solve this problem, the display device 10 according to the present application includes a first gate driver 310 including odd main stages MST1 and MST3 and even auxiliary stages AST2 and AST4 that are alternately disposed with each other; Odd auxiliary stages AST1 and AST3 and even main stages MST2 and MST4 are alternately arranged. Accordingly, the first gate driver 310 can reduce the width w2 of the odd main stages MST1 and MST3 and the even auxiliary stages AST2 and AST4 compared to the conventional display device, and the second gate driver 320 ) can reduce the width w2 of the odd auxiliary stages AST1 and AST3 and the even main stages MST2 and MST4 compared to the conventional display device.

For example, in a conventional display device driven by a double feeding method, the second width w2 increases to accommodate the first to fourth stages ST1 to ST4 within a certain period.

In contrast, the display device 10 according to the present application may drive the gate line through the auxiliary stages AST1 to AST4 including fewer circuit elements than the circuit elements of the main stages MST1 to MST4 . For example, since the auxiliary stages AST1 to AST4 include fewer thin-film transistors than the main stages MST1 to MST4, the area of the auxiliary stages AST1 to AST4 is larger than that of the main stages MST1 to MST4. can be small As a result, in the display device 10 according to the present application, the widths w2 of the first and second gate drivers 310 and 320 may be reduced by reducing the size of the auxiliary stages AST1 to AST4 accommodated within a certain section. can Accordingly, the display device 10 according to the present application includes auxiliary stages AST1 to AST4 having a smaller number of circuit elements than the circuit elements of the main stages MST1 to MST4, so that even when a large panel is driven, the bezel area can reduce

As a result, the display device 10 according to the present application reduces the left and right bezel areas by including the first and second gate drivers 310 and 320 and removes the delay of the gate output signal or the emission signal, thereby providing high-speed driving. can be easily implemented. In other words, the display device 10 reduces the bezel area and outputs differences between gate pulses within the display area by driving the gate line through the main stage and the auxiliary stage having a smaller number of circuit elements than the circuit elements of the main stage. can prevent

A display device according to an exemplary embodiment of the present specification includes a display panel having a display area including pixels connected to a gate line and a non-display area surrounding the display area, and a main stage disposed on one side of the non-display area and driving the gate line. A first gate driver including a first gate driver, and a second gate driver including an auxiliary stage disposed on the other side opposite to one side of the non-display area and driving the gate line, wherein the area of the auxiliary stage may be smaller than that of the main stage. there is.

According to the exemplary embodiment of the present specification, the auxiliary stage may include a smaller number of thin film transistors than the main stage.

According to an embodiment of the present specification, the auxiliary stage may provide the first clock signal as a gate output signal to an output node connected to the gate line based on the gate start signal and the second clock signal.

According to an embodiment of the present specification, an auxiliary stage may provide a first clock signal to an output node connected to a gate line as a gate output signal of a corresponding stage based on a gate output signal and a second clock signal of a previous stage.

According to an embodiment of the present specification, the main stage receives the gate start signal, the first clock signal, the gate high voltage, and the gate low voltage and provides a gate output signal to one end of the gate line, and the auxiliary stage receives the gate start signal, The same output signal as the gate output signal may be provided to the other end of the gate line by receiving the first clock signal and the second clock signal.

According to an embodiment of the present specification, the main stage receives the gate output signal, the first clock signal, the gate high voltage, and the gate low voltage of the previous stage, provides the gate output signal of the corresponding stage to one end of the gate line, and The stage may receive the gate output signal, the first clock signal, and the second clock signal of the previous stage and provide the same output signal as the gate output signal of the corresponding stage to the other end of the gate line.

According to an embodiment of the present specification, the main stage includes a first gate driving circuit for driving a gate line, and the first gate driving circuit connects a first clock signal to one end of the gate line based on a voltage of a first node. A first thin film transistor providing voltage to the first output node, a second thin film transistor discharging the voltage of the first output node based on the voltage of the second node, a first capacitor connected between the first node and the first output node, And it may include a first node control unit for controlling the voltage of each of the first and second nodes.

According to an embodiment of the present specification, the first node control unit receives a gate start signal or a gate output signal of a previous stage, a gate high voltage, and a gate low voltage, and sets the voltage of the first node to be opposite to the voltage of the second node. You can control it.

According to an embodiment of the present specification, the auxiliary stage includes a second gate driving circuit for driving a gate line, and the second gate driving circuit generates a first clock signal based on a voltage of a third node synchronized with a voltage of the first node. A third thin film transistor for providing a signal to a second output node connected to the other end of the gate line, a fourth thin film transistor for providing a gate start signal or a gate output signal of a previous stage to the third node based on the second clock signal, and It may include a third capacitor connected between the third node and the second output node.

According to an exemplary embodiment of the present specification, the display device may further include emission lines connected to pixels and driven by the first and second gate drivers.

According to an embodiment of the present specification, the auxiliary stage may provide a gate high voltage as an emission signal to an output node connected to the emission line based on the emission start signal and the first clock signal.

According to an embodiment of the present specification, an auxiliary stage may provide a gate high voltage to an output node connected to an emission line as an emission signal of a corresponding stage based on an emission signal and a first clock signal of a previous stage.

According to an embodiment of the present specification, the main stage receives the emission start signal, the first clock signal, the gate high voltage, and the gate low voltage and provides the emission signal to one end of the emission line, and the auxiliary stage A start signal, a first clock signal, and a gate high voltage may be received and an output signal identical to the emission signal may be provided to the other end of the emission line.

According to an embodiment of the present specification, the main stage receives the emission signal, the first clock signal, the gate high voltage, and the gate low voltage of the previous stage, and provides the emission signal of the corresponding stage to one end of the emission line; The auxiliary stage may receive the emission signal, the first clock signal, and the gate high voltage of the previous stage and provide the same output signal as the emission signal of the corresponding stage to the other end of the emission line.

According to an embodiment of the present specification, the main stage includes a first emission driving circuit for driving an emission line, and the first emission driving circuit generates a gate high voltage of the emission line based on a voltage of a fourth node. A fifth thin film transistor providing voltage to the third output node connected to one end, a sixth thin film transistor discharging the voltage of the third output node based on the voltage of the fifth node, and a third thin film transistor connected between the fourth node and the third output node. 4 capacitors, and a second node controller controlling voltages of the fourth and fifth nodes, respectively.

According to an embodiment of the present specification, the second node control unit receives an emission start signal or an emission signal of a previous stage, a first clock signal, and a gate low voltage, and sets a voltage of a fourth node to a voltage of a fifth node. You can control it to be the opposite.

According to an embodiment of the present specification, the auxiliary stage includes a second emission driving circuit for driving an emission line, and the second emission driving circuit is based on a voltage of a sixth node synchronized with a voltage of a fourth node. A seventh thin film transistor providing a gate high voltage to a fourth output node connected to the other end of the emission line, and an eighth transistor providing an emission start signal or an emission signal of a previous stage to a sixth node based on a first clock signal. It may include a thin film transistor and a sixth capacitor connected between the sixth node and the fourth output node.

The present application described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which this application belongs that various substitutions, modifications, and changes are possible without departing from the technical details of the present application. It will be clear to those who have knowledge of Therefore, the scope of the present application is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included in the scope of the present application.

100: display panel 200: display driving unit
300: gate driving unit
310, 320: first and second gate drivers
MST1 to MST (2n-1): odd main stage
AST1 to AST(2n-1): odd auxiliary stage
MST2~MST(2n): Even main stage
AST2~AST(2n): Even sub-stage

Claims (17)

a display panel having a display area including pixels connected to the gate line and a non-display area surrounding the display area;
a first gate driver including a main stage disposed on one side of the non-display area and driving the gate line; and
a second gate driver including an auxiliary stage disposed on an opposite side of the non-display area and driving the gate line;
The area of the auxiliary stage is smaller than the area of the main stage;
The main stage provides a first clock signal to a first output node connected to one end of the gate line based on a voltage of a first node charged and discharged by a gate start signal or a gate output signal of a previous stage,
The auxiliary stage provides the first clock signal to a second output node connected to the other end of the gate line based on a voltage of a third node that is synchronized with the voltage of the first node;
The auxiliary stage includes a fourth thin film transistor for charging and discharging the third node by providing the gate start signal or the gate output signal of the previous stage to the third node in response to a second clock signal;
A rising time point of the second clock signal is synchronized with a rising time point of the gate start signal;
The first clock signal and the second clock signal have sequentially shifted phases. According to claim 1,
The display device of claim 1 , wherein the auxiliary stage includes a smaller number of thin film transistors than the main stage. According to claim 1,
wherein the auxiliary stage provides a first clock signal as a gate output signal to an output node connected to the gate line based on the gate start signal and the second clock signal. According to claim 1,
wherein the auxiliary stage provides a first clock signal to an output node connected to the gate line as a gate output signal of a corresponding stage based on the gate output signal of the previous stage and the second clock signal. According to claim 1,
The main stage receives the gate start signal, the first clock signal, a gate high voltage, and a gate low voltage and provides a gate output signal to one end of the gate line;
wherein the auxiliary stage receives the gate start signal, the first clock signal, and the second clock signal and provides an output signal identical to the gate output signal to the other end of the gate line. According to claim 1,
The main stage receives a gate output signal of the previous stage, the first clock signal, a gate high voltage, and a gate low voltage, and provides a gate output signal of the corresponding stage to one end of the gate line;
The auxiliary stage receives the gate output signal, the first clock signal, and the second clock signal of the previous stage and provides an output signal identical to the gate output signal of the corresponding stage to the other end of the gate line. . According to claim 1,
The main stage includes a first gate driving circuit for driving the gate line;
The first gate driving circuit,
a first thin film transistor providing the first clock signal to a first output node connected to one end of the gate line based on the voltage of the first node;
a second thin film transistor for discharging the voltage of the first output node based on the voltage of the second node;
a first capacitor connected between the first node and the first output node; and
and a first node controller controlling a voltage of each of the first and second nodes. According to claim 7,
The first node controller controls the voltage of the first node to be opposite to the voltage of the second node by receiving the gate start signal or the gate output signal, gate high voltage, and gate low voltage of the previous stage, display device. According to claim 7,
The auxiliary stage includes a second gate driving circuit for driving the gate line;
The second gate driving circuit,
a third thin film transistor configured to provide the first clock signal to a second output node connected to the other end of the gate line based on the voltage of the third node synchronized with the voltage of the first node;
the fourth thin film transistor providing the gate start signal or the gate output signal of the previous stage to the third node based on the second clock signal; and
and a third capacitor connected between the third node and the second output node. According to claim 1,
and an emission line connected to the pixel and driven by the first and second gate drivers. According to claim 10,
wherein the auxiliary stage provides a gate high voltage as an emission signal to an output node connected to the emission line based on the emission start signal and the first clock signal. According to claim 10,
wherein the auxiliary stage provides a gate high voltage to an output node connected to the emission line as an emission signal of a corresponding stage based on an emission signal of a previous stage and the first clock signal. According to claim 10,
The main stage receives an emission start signal, the first clock signal, a gate high voltage, and a gate low voltage and provides an emission signal to one end of the emission line;
wherein the auxiliary stage receives an emission start signal, the first clock signal, and a gate high voltage and provides an output signal identical to the emission signal to the other end of the emission line. According to claim 10,
The main stage receives an emission signal of a previous stage, the first clock signal, a gate high voltage, and a gate low voltage, and provides an emission signal of the corresponding stage to one end of the emission line;
wherein the auxiliary stage receives an emission signal of a previous stage, the first clock signal, and a gate high voltage, and provides an output signal identical to the emission signal of the corresponding stage to the other end of the emission line. According to claim 10,
The main stage includes a first emission driving circuit for driving the emission line;
The first emission driving circuit,
a fifth thin film transistor providing a gate high voltage based on a voltage of a fourth node to a third output node connected to one end of the emission line;
a sixth thin film transistor discharging a voltage of the third output node based on a voltage of a fifth node;
a fourth capacitor connected between the fourth node and the third output node; and
and a second node controller controlling a voltage of each of the fourth and fifth nodes. According to claim 15,
The second node control unit controls the voltage of the fourth node to be opposite to the voltage of the fifth node by receiving an emission start signal or an emission signal of a previous stage, a first clock signal, and a gate low voltage, display device. According to claim 15,
The auxiliary stage includes a second emission driving circuit for driving the emission line;
The second emission driving circuit,
a seventh thin film transistor configured to provide the gate high voltage to a fourth output node connected to the other end of the emission line based on a voltage at a sixth node that is synchronized with a voltage at the fourth node;
an eighth thin film transistor providing an emission start signal or an emission signal of a previous stage to the sixth node based on a first clock signal; and
and a sixth capacitor connected between the sixth node and the fourth output node.

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