KR102487762B1 - Bicm reception device and method corresponding to 16-symbol mapping and low density parity check codeword with 16200 length, 2/15 rate - Google Patents

Abstract

A bit interleaver, a BICM device, and a bit interleaving method are disclosed. A bit interleaver according to an embodiment of the present invention includes a first memory for storing an LDPC codeword having a length of 16200 and a code rate of 2/15; a processor interleaving the LDPC codeword in units of bit groups having a size corresponding to a parallel factor of the LDPC codeword to generate an interleaved codeword; and a second memory providing the interleaved codeword to a modulator for 16-symbol mapping.

Description

Apparatus and method for receiving BICM corresponding to 16200 length and 2/15 code rate LDPC codeword and 16-symbol mapping 2/15 RATE}

The present invention relates to an interleaver, and more particularly, to a bit interleaver for distributing burst errors generated in a digital broadcasting channel.

BICM (Bit-Interleaved Coded Modulation) is a bandwidth-efficient transmission technology that includes an error-correction coder, a bit-by-bit interleaver, and a high-order modulator. It is a combined form.

BICM can provide excellent performance with a simple structure by using a low-density parity check (LDPC) coder or a turbo coder as an error correction coder. In addition, BICM provides a high level of flexibility because it can select a modulation order, error correction code length and code rate in various ways. Because of these advantages, BICM is not only used in broadcasting standards such as DVB-T2 or DVB-NGH, but is highly likely to be used in other next-generation broadcasting systems as well.

Despite these advantages, BICM's performance rapidly deteriorates if burst errors generated in a channel cannot be properly distributed through a bit-level interleaver. Therefore, the bitwise interleaver used in BICM must be designed to be optimized for modulation coefficients, error correction code lengths, and code rates.

An object of the present invention is to provide a bit interleaver inside BICM that can effectively disperse burst errors generated in a broadcasting system channel.

In addition, an object of the present invention is to provide a bit interleaver that can be applied to a next-generation broadcasting system such as ATSC 3.0 by being optimized for an LDPC encoder having a length of 16200 and a code rate of 2/15 and a modulator performing 16-symbol mapping. is to do

A bit interleaver according to the present invention for achieving the above objects includes a first memory for storing an LDPC codeword having a length of 16200 and a code rate of 2/15; a processor interleaving the LDPC codeword in units of bit groups having a size corresponding to a parallel factor of the LDPC codeword to generate an interleaved codeword; and a second memory providing the interleaved codeword to a modulator for 16-symbol mapping.

In this case, the 16-symbol mapping may be NUC (Non-Uniform Constellation) symbol mapping having 16 constellations.

In this case, the parallel factor is 360, and the bit group may include 360 bits.

(N _ldpc 는 16200)와 같이 표현되고, 하기 수학식 9와 같이 각각 360개의 비트들로 구성된 45개의 비트그룹들로 분할될 수 있다.At this time, the LDPC codeword is

( N _ldpc is 16200) and can be divided into 45 bit groups each consisting of 360 bits as shown in Equation 9 below.

[Equation 9]

( X _j is the jth bit group, N _ldpc is 16200, N _group is 45)

In this case, interleaving may be performed using Equation 10 below using a permutation order.

[Equation 10]

( X _j is the j-th bit group, Y _j is the interleaved j-th bit group, and π( j ) is the permutation order for interleaving bit group units)

In this case, the permutation order may correspond to an interleaving sequence expressed by Equation 11 below.

[Equation 11]

interleaved sequence

={5 33 18 8 29 10 21 14 30 26 11 23 27 4 7 6 24 44 38 31 34 43 13 0 15 42 17 2 20 12 40 39 35 32 1 3 41 37 9 25 19 22 16 28 36}

In addition, the bit interleaving method according to the present invention includes storing an LDPC codeword having a length of 16200 and a code rate of 2/15; generating an interleaved codeword by interleaving the LDPC codeword in units of bit groups having a size corresponding to a parallel factor of the LDPC codeword; and outputting the interleaved codeword to a modulator for 16-symbol mapping.

In addition, the BICM apparatus according to the present invention includes an error correction encoder for outputting an LDPC codeword having a length of 16200 and a code rate of 2/15; a bit interleaver interleaving the LDPC codeword in units of bit groups having a size corresponding to a parallel factor of the LDPC codeword and outputting an interleaved codeword; and a modulator for mapping the interleaved codeword to 16-symbols.

According to the present invention, a bit interleaver inside BICM capable of effectively distributing burst errors generated in a broadcasting system channel is provided.

In addition, the present invention provides a bit interleaver optimized for an LDPC encoder having a length of 16200 and a code rate of 2/15 and a modulator performing 16-symbol mapping and applicable to a next-generation broadcasting system such as ATSC 3.0.

1 is a block diagram showing a system for transmitting/receiving broadcast signals according to an embodiment of the present invention.
2 is an operational flowchart illustrating a broadcast signal transmission/reception method according to an embodiment of the present invention.
3 is a diagram showing the structure of a parity check matrix corresponding to an LDPC code according to an embodiment of the present invention.
4 is a diagram illustrating bit groups of an LDPC codeword having a length of 64800.
5 is a diagram illustrating bit groups of an LDPC codeword having a length of 16200.
6 is a diagram illustrating interleaving in units of bit groups according to an interleaving sequence.
7 is a block diagram illustrating a bit interleaver according to an embodiment of the present invention.
8 is an operational flowchart illustrating a bit interleaving method according to an embodiment of the present invention.

The present invention will be described in detail with reference to the accompanying drawings. Here, repeated descriptions, well-known functions that may unnecessarily obscure the subject matter of the present invention, and detailed descriptions of configurations are omitted. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clarity.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a system for transmitting/receiving broadcast signals according to an embodiment of the present invention.

Referring to FIG. 1 , it can be seen that the BICM device 10 and the BICM receiving device 30 communicate via a radio channel 20 .

The BICM device 10 encodes k-bit information bits 11 in the error correction encoder 13 to generate an n-bit codeword. In this case, the error correction coder 13 may be an LDPC coder or a turbo coder.

The codeword is interleaved by the bit interleaver 14 to generate an interleaved codeword.

In this case, interleaving may be performed in units of bit groups. At this time, the error correction coder 13 may be an LDPC encoder having a length of 16200 and a code rate of 2/15, and a codeword of length 16200 may be divided into a total of 45 bit groups, and each of the bit groups may be LDPC It may include 360 bits that are a parallel factor of the codeword.

In this case, interleaving may be performed in units of bit groups corresponding to an interleaving sequence to be described later.

At this time, the bit interleaver 14 effectively disperses the clustering errors generated in the channel to prevent performance deterioration of the error correction code. At this time, the bit interleaver 14 may be individually designed according to the length and code rate of the error correction code and the modulation coefficient.

The interleaved codeword is modulated by the modulator 15 and transmitted through the antenna 17.

At this time, the modulator 15 is a concept including a symbol mapping device. In this case, the modulator 15 may be a symbol mapping device that performs 16-symbol mapping to map codes to 16 constellations.

In this case, the modulator 15 may be a uniform modulator such as a quadrature amplitude modulation (QAM) modulator or a non-uniform modulator.

In particular, the modulator 15 may be a symbol mapping device that performs NUC (Non-Uniform Constellation) symbol mapping with 16 constellations.

The signal transmitted through the radio channel 20 is received through the antenna 31 of the BICM receiving device 30, and the BICM receiving device 30 undergoes the reverse process of the process that occurred in the BICM device 10. That is, the received data is demodulated by the demodulator 33, deinterleaved by the bit deinterleaver 34, and decoded by the error correction decoder 35 to finally restore information bits.

The transmission/reception process as described above has been described within the minimum range required to explain the characteristics of the present invention, and it is obvious to those skilled in the art that many processes necessary for data transmission may be added in addition to those described.

2 is an operational flowchart illustrating a broadcast signal transmission/reception method according to an embodiment of the present invention.

Referring to FIG. 2 , in the method for transmitting/receiving broadcast signals according to an embodiment of the present invention, first, input bits (information bits) are error-correction-encoded (S210).

That is, in step S210, an n-bit codeword is generated by encoding k-bit information bits in an error correction encoder.

At this time, step S210 may be performed in the same manner as the LDPC encoding method described later.

In addition, in the broadcast signal transmission/reception method, an interleaved codeword is generated by interleaving n-bit codewords in units of bit groups (S220).

In this case, the n-bit codeword may be an LDPC codeword having a length of 16200 and a code rate of 2/15, and a codeword having a length of 16200 may be divided into a total of 45 bit groups, and each of the bit groups may be an LDPC codeword It may include 360 bits corresponding to a parallel factor of .

In this case, interleaving may be performed in units of bit groups corresponding to an interleaving sequence to be described later.

In addition, the broadcast signal transmission/reception method modulates coded data (S230).

That is, in step S230, the interleaved codeword is modulated by a modulator.

At this time, the modulator is a concept including a symbol mapping device. In this case, the modulator may be a symbol mapping device that performs 16-symbol mapping for mapping codes to 16 constellations.

In this case, the modulator may be a uniform modulator such as a quadrature amplitude modulation (QAM) modulator or a non-uniform modulator.

In particular, the modulator may be a symbol mapping device that performs NUC (Non-Uniform Constellation) symbol mapping having 16 constellations.

Also, the broadcast signal transmission/reception method transmits modulated data (S240).

That is, in step S240, the modulated codeword is transmitted through an antenna through a radio channel.

In addition, the broadcast signal transmission/reception method demodulates received data (S250).

That is, in step S250, a signal transmitted through a radio channel is received through an antenna of the receiver, and the received data is demodulated by a demodulator.

Also, in the broadcast signal transmission/reception method, demodulated data is deinterleaved (S260). In this case, the deinterleaving of step S260 may correspond to the reverse process of step S220.

Also, in the broadcast signal transmission/reception method, error correction decoding is performed on the deinterleaved codeword (S270).

That is, in step S270, error correction decoding is performed through the error correction decoder of the receiver to finally restore information bits.

At this time, step S270 may correspond to a reverse process of the LDPC encoding method to be described later.

LDPC (Low Density Parity Check) codes are known as codes that approach the Shannon limit in an Additive White Gaussian Noise (AWGN) channel, and have asymptotically superior performance to turbo codes, parallelizable decoding, etc. has the advantage of

In general, an LDPC code is defined by a randomly generated low-density Parity Check Matrix (PCM). However, randomly generated LDPC codes not only require a lot of memory to store the PCM, but also take a lot of time to access the memory. To solve this problem, a quasi-cyclic LDPC (QC-LDPC) code has been proposed, and the QC-LDPC code composed of a zero matrix or a Circulant Permutation Matrix (CPM) is It is defined by PCM represented by 1.

[Equation 1]

Here, J is a CPM of size L x L and is given by Equation 2 below. Hereinafter, L may be 360.

[Equation 2]

In addition, J ⁱ is an L x L identity matrix I(=J ⁰ ) shifted to the right i (0=i<L) times, and J ^∞ is an L x L zero matrix. Therefore, in the QC-LDPC code, since only the exponent i needs to be stored to store J ⁱ , the memory required for storing the PCM is greatly reduced.

3 is a diagram showing the structure of a parity check matrix corresponding to an LDPC code according to an embodiment of the present invention.

Referring to FIG. 3, the sizes of matrices A and C are g x K and (N-K-g) x (K+g), respectively, and are composed of a zero matrix of L x L size and CPM. In addition, matrix z is a zero matrix of size g x (N-K-g), matrix D is an identity matrix of size (N-K-g) x (N-K-g), and matrix B is a dual diagonal matrix of size g x g. matrix). In this case, the matrix B may be a matrix in which all elements other than the elements on the diagonal and the elements adjacent to the bottom of the diagonal are all 0, or may be defined as in Equation 3 below.

[Equation 3]

Here, I _LxL is an identity matrix of size L x L.

That is, the matrix B may be a general (bit-wise) double-diagonal matrix, or a block-wise double-diagonal matrix having an identity matrix as a block as indicated in Equation 3 above. A bit-wise double-diagonal matrix is disclosed in detail in Korean Patent Publication No. 2007-0058438 and the like.

In particular, when matrix B is a general (bit-wise) double-diagonal matrix, row permutation or column permutation is applied to the PCM of the structure shown in FIG. It is obvious to those skilled in the art that it can be converted to quasi-cyclic.

At this time, N is the length of a codeword, and K represents the length of information.

In the present invention, as shown in Table 1 below, a newly designed QC-LDPC code with a code rate of 2/15 and a codeword length of 16200 is proposed. That is, an LDPC code generating an LDPC codeword having a length of 16200 by receiving information having a length of 2160 is proposed.

Table 1 shows the size of A, B, C, D, Z matrices of the QC-LDPC code of the present invention.

[Table 1]

A newly designed LDPC code can be displayed in the form of a sequence, an equivalent relationship is established between a sequence and a matrix (a parity bit check matrix), and the sequence can be expressed as shown in the following table.

[table]

Line 1: 2889 3122 3208 4324 5968 7241 13215

Line 2: 281 923 1077 5252 6099 10309 11114

Line 3: 727 2413 2676 6151 6796 8945 12528

Line 4: 2252 2322 3093 3329 8443 12170 13748

Line 5: 575 2489 2944 6577 8772 11253 11657

Line 6: 310 1461 2482 4643 4780 6936 11970

Line 7: 8691 9746 10794 13582

Line 8: 3717 6535 12470 12752

Line 9: 6011 6547 7020 11746

Line 10: 5309 6481 10244 13824

Line 11: 5327 8773 8824 13343

Line 12: 3506 3575 9915 13609

Line 13: 3393 7089 11048 12816

Line 14: 3651 4902 6118 12048

Line 15: 4210 10132 13375 13377

The LDPC code expressed in the form of a sequence is widely used in the DVB standard.

를 생성한다. 여기서, M₁=g, M₂=N-K-g이다. 또한, M₁은 이중 대각행렬(dual diagonal matrix) B에 대응하는 패러티(parity)의 크기이며, M₂는 항등행렬 D에 대응하는 패러티의 크기이다. 부호화 과정은 다음과 같다.According to one embodiment of the present invention, the LDPC code expressed in the form of a sequence is encoded as follows. Assume an information block S=(s ₀ , s ₁ , ..., s _K-1 ) with an information size K. The LDPC encoder uses an information block S of size K to generate a codeword of size N=K+M ₁ +M ₂

generate Here, M ₁ =g, M ₂ =NKg. In addition, M ₁ is the size of parity corresponding to the dual diagonal matrix B, and M ₂ is the size of parity corresponding to the identity matrix D. The encoding process is as follows.

-Initialization:

[Equation 4]

를 상기 테이블의 수열의 제1행에 명시된 패러티 비트 주소들(parity bit addresses)에서 누적(accumulate)한다. 예를 들어, 길이가 16200이며, 부호율이 2/15인 LDPC 부호에서의 누적 과정은 다음과 같다.-First

Accumulate at the parity bit addresses specified in the first row of the sequence of the table. For example, an accumulation process in an LDPC code having a length of 16200 and a code rate of 2/15 is as follows.

)은 GF(2)에서 일어난다.Add here (

) occurs in GF(2).

들에 대해서는, 하기 수학식 5에서 계산된 패러티 비트 주소들에서 누적한다.-the next L-1 information bits, i.e.

For , the parity bit addresses calculated in Equation 5 below are accumulated.

[Equation 5]

에 대응되는 패러티 비트 주소들, 즉 상기 테이블의 수열의 제1행에 표기된 패러티 비트 주소들을 나타내며, Q₁ = M₁/L, Q₂ = M₂/L, L = 360이다. 또한, Q₁과 Q₂는 하기 표 2에 정의된다. 예를 들어, 길이가 16200이며, 부호율이 2/15인 LDPC 부호는 M₁ = 3240, Q₁ = 9, M₂ = 10800, Q₂ = 30, L = 360이므로, 두 번째 비트

에 대해서는 상기 수학식 5를 이용하면 다음과 같은 연산이 수행된다.where x is the first bit

Indicates parity bit addresses corresponding to , that is, parity bit addresses indicated in the first row of the sequence of the table, Q ₁ = M ₁ /L, Q ₂ = M ₂ /L, L = 360. In addition, Q ₁ and Q ₂ are defined in Table 2 below. For example, an LDPC code with a length of 16200 and a code rate of 2/15 has M ₁ = 3240, Q ₁ = 9, M ₂ = 10800, Q ₂ = 30, and L = 360, so the second bit

For Equation 5, the following calculation is performed.

Table 2 shows the sizes of M ₁ , M ₂ , Q ₁ , and Q ₂ of the designed QC-LDPC code.

[Table 2]

부터

까지의 새로운 360개의 정보비트들은 상기 수열의 제2행을 이용하여, 상기 수학식 5로부터 패러티 비트 누적기들의 주소를 계산하고, 누적한다.-the next

from

For the new 360 information bits up to , the addresses of the parity bit accumulators are calculated and accumulated from Equation 5 using the second row of the sequence.

-Similarly, for all groups composed of L new information bits, addresses of parity bit accumulators are calculated and accumulated from Equation 5 using a new row of the sequence.

에서

까지의 모든 정보비트들이 사용된 후, i = 1부터 시작하여 하기 수학식 6의 연산을 순차적으로 수행한다.-

at

After all information bits up to are used, operations of Equation 6 below are sequentially performed, starting from i = 1.

[Equation 6]

-Next, if parity interleaving is performed as shown in Equation 7 below, parity generation corresponding to the double diagonal matrix B is completed.

[Equation 7]

)를 이용하여 이중 대각행렬 B에 대응하는 패러티 생성이 완료되면, M₁개의 생성된 패러티(

)을 이용하여, 항등행렬 D에 대응하는 패러티를 생성한다.K information bits (

), when parity generation corresponding to the double diagonal matrix B is completed, M ₁ generated parity (

) is used to generate a parity corresponding to the identity matrix D.

에서

까지의 L개의 비트들로 구성된 모든 그룹(group)들에 대해서, 상기 수열들의 새로운 행(이중 대각행렬 B에 대응하는 패러티를 생성할 때 이용한 마지막 행의 바로 다음 행부터 시작)과 상기 수학식 5를 이용하여 패러티 비트 누적기들의 주소를 계산하고, 관련 연산을 수행한다.-

at

For all groups consisting of up to L bits, a new row of the sequences (starting from the row immediately following the last row used when generating the parity corresponding to the double diagonal matrix B) and Equation 5 Calculate the addresses of the parity bit accumulators using , and perform related operations.

에서

까지의 모든 비트들이 사용된 후, 하기 수학식 8과 같은 패러티 인터리빙을 수행하면, 항등행렬 D에 대응하는 패러티 생성이 완료된다.-

at

After all bits up to are used, if parity interleaving is performed as shown in Equation 8 below, parity generation corresponding to the identity matrix D is completed.

[Equation 8]

4 is a diagram illustrating bit groups of an LDPC codeword having a length of 64800.

Referring to FIG. 4 , it can be seen that an LDPC codeword having a length of 64800 is divided into 180 bit groups (0 ^th group to 179 ^th group).

In this case, 360 may be a Parallel Factor (PF) of the LDPC codeword. That is, since PF is 360, an LDPC codeword with a length of 64800 is divided into 180 bit groups as shown in FIG. 4, and each bit group includes 360 bits.

5 is a diagram illustrating bit groups of an LDPC codeword having a length of 16200.

Referring to FIG. 5 , it can be seen that an LDPC codeword having a length of 16200 is divided into 45 bit groups (0 ^th group to 44 ^th group).

In this case, 360 may be a Parallel Factor (PF) of the LDPC codeword. That is, since PF is 360, an LDPC codeword with a length of 16200 is divided into 45 bit groups as shown in FIG. 5, and each bit group includes 360 bits.

6 is a diagram illustrating interleaving in units of bit groups according to an interleaving sequence.

Referring to FIG. 6, it can be seen that interleaving is performed by changing the order of bit groups according to the designed interleaving sequence.

For example, assume that an interleaving sequence for an LDPC codeword of length 16200 is as follows.

Interleaved sequence = {24 34 15 11 2 28 17 25 5 38 19 13 6 39 1 14 33 37 29 12 42 31 30 32 36 40 26 35 44 4 16 8 20 43 21 7 0 18 23 3 10 42 9 2}

Then, the order of bit groups of the LDPC codeword shown in FIG. 4 is changed as shown in FIG. 6 by an interleaving sequence.

That is, the LDPC codeword 610 and the interleaved codeword 620 each include 45 bit groups, and the 24th bit group of the LDPC codeword 610 is interleaved by an interleaving sequence. becomes the 0th bit group of , the 34th bit group of the LDPC codeword 610 becomes the 1st bit group of the interleaved LDPC codeword 620, and the 15th bit group of the LDPC codeword 610 interleaved The 2nd bit group of the LDPC codeword 620, the 11th bit group of the LDPC codeword 610 become the 3rd bit group of the interleaved LDPC codeword 620, and the 2nd bit group of the LDPC codeword 610 It can be seen that the th bit group becomes the 4 th bit group of the interleaved LDPC codeword 620.

는 N _group = N _ldpc / 360 개의 비트그룹들로 쪼개어진다. 이 때, N _ldpc 는 16200일 수 있다. _LDPC codeword of length N ldpc

is divided into N _group = N _ldpc / 360 bit groups. At this time, N _ldpc may be 16200.

[Equation 9]

Here, X _j represents the jth bit group, and each X _j is composed of 360 bits.

The LDPC codeword divided into bit groups is interleaved as shown in Equation 10 below.

[Equation 10]

Here, Y _j denotes an interleaved j-th bit group, and π( j ) is a permutation order for bit-group unit interleaving. The permutation order corresponds to the interleaving sequence of Equation 11 below.

[Equation 11]

interleaved sequence

={5 33 18 8 29 10 21 14 30 26 11 23 27 4 7 6 24 44 38 31 34 43 13 0 15 42 17 2 20 12 40 39 35 32 1 3 41 37 9 25 19 22 16 28 36}

That is, assuming that each of the codeword and the interleaved codeword includes 45 bit groups from the 0th bit group to the 44th bit group, the interleaving sequence of Equation 11 is a codeword in which the 5th bit group of the codeword is interleaved. becomes the 0th bit group of the codeword, the 33rd bit group of the codeword becomes the 1st bit group of the interleaved codeword, the 18th bit group of the codeword becomes the 2nd bit group of the interleaved codeword, and the codeword The 8th bit group of becomes the 3rd bit group of the interleaved codeword, ..., the 28th bit group of the codeword becomes the 43rd bit group of the interleaved codeword, and the 36th bit group of the codeword This means that it becomes the 44th bit group of the interleaved codeword.

In particular, the interleaving sequence shown in Equation 11 is optimized when 16-symbol mapping (in particular, NUC symbol mapping) is used and an LDPC encoder with a length of 16200 and a code rate of 2/15 is used.

7 is a block diagram illustrating a bit interleaver according to an embodiment of the present invention.

Referring to FIG. 7 , a bit interleaver according to an embodiment of the present invention includes memories 710 and 730 and a processor 720 .

The memory 710 stores an LDPC codeword having a length of 16200 and a code rate of 2/15.

The processor 720 generates an interleaved codeword by interleaving the LDPC codeword in units of bit groups corresponding to a parallel factor of the LDPC codeword.

In this case, the parallel factor may be 360. In this case, the bit group may include 360 bits.

At this time, the LDPC codeword may be divided into 45 bit groups as shown in Equation 9 above.

In this case, interleaving may be performed using Equation 10 using a permutation order.

In this case, the permutation order may correspond to the interleaving sequence expressed by Equation 11 above.

The memory 730 provides the interleaved codeword to a modulator for 16-symbol mapping.

In this case, the modulator may be a symbol mapping device that performs NUC (Non-Uniform Constellation) symbol mapping.

The memory 710 and the memory 730 may correspond to various hardware for storing a set of bits, and data structures such as an array, a list, a stack, and a queue ( data structure).

In this case, the memory 710 and the memory 730 may not be physically separate devices, but physically correspond to different addresses of one device. That is, the memory 710 and the memory 730 may not be physically separated but only logically separated.

The error correction encoder 13 shown in FIG. 1 may be implemented with a structure as shown in FIG. 7 .

That is, the error correction encoder may include memories and a processor. In this case, the first memory may be a memory for storing an LDPC codeword having a length of 16200 and a code rate of 2/15, and the second memory may be a memory initialized to 0.

The memories may correspond to λ _i (i=0, 1, ..., N-1) and P _j (j=0, 1, ..., M ₁ +M ₂ -1), respectively.

The processor may generate the LDPC codeword corresponding to information bits by performing accumulation on the memory using a sequence corresponding to a parity check matrix.

In this case, accumulation may be performed on parity bit addresses that are updated using the sequence of the table.

At this time, the LDPC codeword is a systematic part (λ ₀ , λ ₁ , ..., λ _K-1 ) corresponding to the information bits and having a length of 2160 (=K), included in the parity check matrix The first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) corresponding to the double diagonal matrix and having a length of 3240 (=M ₁ =g) and the identity included in the parity check matrix It may include a second parity part (λ _K+M1 , λ _K+M1+1 , ..., λ _K+M1+M2-1 ) corresponding to the matrix and having a length of 10800 (=M ₂ ).

At this time, the sequence is a value obtained by dividing 2160, which is the length of the systematic part, by 360, which is the CPM size (L) corresponding to the parity check matrix, and 3240, which is the length (M ₁ ) of the first parity part, by 360. It can have as many rows as the added number (2160/360+3240/360=15).

As described above, a sequence can be represented by the table above.

In this case, the second memory may have a size corresponding to the sum (M ₁ +M ₂ ) of the lengths of the first parity part (M ₁ ) and the lengths of the second parity part (M ₂ ).

In this case, the parity bit addresses may be updated based on a result of comparing each of the previous parity bit addresses (x) indicated in each row of the sequence with the length (M ₁ ) of the first parity part.

That is, parity bit addresses can be updated by Equation 5 above. At this time, x is the previous parity bit address, m is an information bit index, an integer greater than 0 and less than L, L is the CPM size of the parity check matrix, Q ₁ is M ₁ /L, M ₁ is the first parity part The size of Q ₂ may be M ₂ /L, and M ₂ may be the size of the second parity part.

At this time, as described above, the accumulation may be performed while changing rows of the sequence in units of CPM size L = 360 of the parity check matrix.

In this case, the first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) performs parity interleaving using the first memory and the second memory, as described through Equation 7 above. It can be created by performing parity interleaving.

In this case, the second parity part (λ _K+M1 , λ _K+M1+1 , ..., λ _K+M1+M2-1 ) is the first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ), the first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) and the sequence It may be generated by performing parity interleaving using the first memory and the second memory after the accumulation performed by using is completed.

8 is an operational flowchart illustrating a bit interleaving method according to an embodiment of the present invention.

Referring to FIG. 8, the bit interleaving method according to an embodiment of the present invention stores an LDPC codeword having a length of 16200 and a code rate of 2/15 (S810).

(N _ldpc 는 16200)와 같이 표현되고, 상기 수학식 9와 같이 각각 360개의 비트들로 구성된 45개의 비트그룹들로 분할될 수 있다.At this time, the LDPC codeword is

( N _ldpc is 16200) and can be divided into 45 bit groups each consisting of 360 bits as shown in Equation 9 above.

In addition, the bit interleaving method according to an embodiment of the present invention generates an interleaved codeword by interleaving the LDPC codeword in units of bit groups having a size corresponding to a parallel factor of the LDPC codeword (S820 ).

In this case, interleaving may be performed using Equation 10 using a permutation order.

In this case, the permutation order may correspond to the interleaving sequence expressed by Equation 11 above.

In this case, the parallel factor is 360, and the bit group may include 360 bits.

Also, in the bit interleaving method according to an embodiment of the present invention, the interleaved codeword is output to a modulator for 16-symbol mapping (S830).

As described above, the bit interleaver, the BICM device, and the bit interleaving method according to the present invention are not limited to the configuration and method of the above-described embodiments, but the above embodiments can be variously modified. All or part of the embodiments may be configured by selectively combining them.

710, 730: memory
720: processor

Claims (8)

delete a demodulator that performs demodulation corresponding to 16-symbol mapping;
a bit deinterleaver for generating deinterleaved values corresponding to an LDPC codeword having a length of 16200 and a code rate of 2/15 by performing group unit deinterleaving after the demodulation; and
An LDPC decoder for restoring information bits by performing LDPC decoding corresponding to the deinterleaved values;
The group-by-group deinterleaving is
A bit interleaved and coded modulation (BICM) receiver, which corresponds to a reverse process of interleaving using a permutation order, wherein the permutation order corresponds to the following interleaving sequence.
[interleaving sequence]
={5 33 18 8 29 10 21 14 30 26 11 23 27 4 7 6 24 44 38 31 34 43 13 0 15 42 17 2 20 12 40 39 35 32 1 3 41 37 9 25 19 22 16 28 36} The method of claim 2,
The LDPC codeword is generated using a sequence corresponding to a parity check matrix, and the sequence is represented by the following table.
[table]
Line 1: 2889 3122 3208 4324 5968 7241 13215
Line 2: 281 923 1077 5252 6099 10309 11114
Line 3: 727 2413 2676 6151 6796 8945 12528
Line 4: 2252 2322 3093 3329 8443 12170 13748
Line 5: 575 2489 2944 6577 8772 11253 11657
Line 6: 310 1461 2482 4643 4780 6936 11970
Line 7: 8691 9746 10794 13582
Line 8: 3717 6535 12470 12752
Line 9: 6011 6547 7020 11746
Line 10: 5309 6481 10244 13824
Line 11: 5327 8773 8824 13343
Line 12: 3506 3575 9915 13609
Line 13: 3393 7089 11048 12816
Line 14: 3651 4902 6118 12048
Line 15: 4210 10132 13375 13377 The method of claim 2,
The 16-symbol mapping is a BICM receiving device, characterized in that NUC (Non-Uniform Constellation) symbol mapping having 16 constellations. The method of claim 4,
The group-by-group deinterleaving is
A BICM receiving apparatus, characterized in that it is performed based on groups each containing 360 values. The method of claim 5,
The LDPC codeword is

( N _ldpc is 16200) and is divided into 45 bit groups each consisting of 360 bits as shown in the following equation.
[mathematical expression]

( X _j is the jth bit group, N _ldpc is 16200, N _group is 45) performing demodulation corresponding to 16-symbol mapping;
performing group-wise deinterleaving after the demodulation to generate deinterleaved values corresponding to an LDPC codeword having a length of 16200 and a code rate of 2/15; and
Restoring information bits by performing LDPC decoding corresponding to the deinterleaved values;
The group-by-group deinterleaving is
A bit interleaved and coded modulation (BICM) reception method, which corresponds to a reverse process of interleaving using a permutation order, wherein the permutation order corresponds to the following interleaving sequence.
[interleaving sequence]
={5 33 18 8 29 10 21 14 30 26 11 23 27 4 7 6 24 44 38 31 34 43 13 0 15 42 17 2 20 12 40 39 35 32 1 3 41 37 9 25 19 22 16 28 36} The method of claim 7,
The LDPC codeword is generated using a sequence corresponding to a parity check matrix, and the sequence is represented by the following table.
[table]
Line 1: 2889 3122 3208 4324 5968 7241 13215
Line 2: 281 923 1077 5252 6099 10309 11114
Line 3: 727 2413 2676 6151 6796 8945 12528
Line 4: 2252 2322 3093 3329 8443 12170 13748
Line 5: 575 2489 2944 6577 8772 11253 11657
Line 6: 310 1461 2482 4643 4780 6936 11970
Line 7: 8691 9746 10794 13582
Line 8: 3717 6535 12470 12752
Line 9: 6011 6547 7020 11746
Line 10: 5309 6481 10244 13824
Line 11: 5327 8773 8824 13343
Line 12: 3506 3575 9915 13609
Line 13: 3393 7089 11048 12816
Line 14: 3651 4902 6118 12048
Line 15: 4210 10132 13375 13377

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