KR102435057B1 - Pixel, image sensor having the pixel, and portable electronic device - Google Patents

Abstract

A pixel of a backside illuminated (BSI) image sensor is formed between a semiconductor substrate including a first surface and a second surface, and between the first surface and the second surface, in response to incident light received through the second surface. a photoelectric conversion region for generating electric charges, first trench-type isolation regions surrounding the photoelectric conversion region and extending vertically from the second surface, below the photoelectric conversion region in the semiconductor substrate a floating diffusion region formed thereon; and a transfer gate extending vertically from the first surface to the photoelectric conversion region and transferring the charges of the photoelectric conversion region to the floating diffusion region, the first trench-type isolation region comprising: They contain negatively charged materials.

Description

A pixel, an image sensor including the same, and a portable electronic device including the image sensor

An embodiment according to a concept of the present invention relates to an image sensor, and more particularly, includes a pixel including back deep trench isolation (DTI) and a vertical transfer gate, an image sensor including the same, and the image sensor It relates to a portable electronic device.

An image sensor (or image sensor chip) is a semiconductor device that converts optical images into electrical signals. The image sensor may be classified into a charge coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor.

The CMOS image sensor has a lower manufacturing cost compared to a CCD image sensor including a high voltage analog circuit, and consumes less power because the CMOS image sensor has a relatively small size.

Recently, as the performance of the CMOS image sensor is improved, the CMOS image sensor is widely used in various home appliances other than a smart phone or a digital camera. A CMOS image sensor includes a photoelectric conversion element that generates electric charges from incident light incident from the outside, and a processing circuit that processes electrical signals corresponding to the generated electric charges.

As the resolution of the CMOS image sensor increases, the number of pixels implemented in the pixel array of the CMOS image sensor increases, and as many pixels are implemented in the pixel array having a limited size, the size of each of the pixels decreases. Accordingly, an interference phenomenon, for example, crosstalk, may occur between pixels.

The technical problem to be achieved by the present invention is, in order to reduce crosstalk that may occur between pixels, a pixel including a back deep trench isolation (DTI) and a vertical transfer gate, and an image sensor including the same , and to provide a portable electronic device including the image sensor.

A pixel of a backside illuminated (BSI) image sensor according to an embodiment of the present invention is formed between a semiconductor substrate including a first surface and a second surface, the first surface and the second surface, and forming the second surface. a photoelectric conversion region that generates charges in response to incident light received through the photoelectric conversion region; first trench-type isolation regions surrounding the photoelectric conversion region and extending vertically from the second surface; a floating diffusion region formed below the region; and a transfer gate extending vertically from the first surface to the photoelectric conversion region and transferring the charges of the photoelectric conversion region to the floating diffusion region; The first trench-type isolation regions include negatively charged material.

In some embodiments, the first trench-type isolation regions extend from the second surface to the first surface.

According to embodiments, it further includes second trench-type isolation regions extending vertically from the first surface, wherein the first trench-type isolation regions and the second trench-type isolation regions are in contact with each other.

When the first trench-type isolation regions are deep trench isolation (DTI) regions, the second trench-type isolation regions are shallow trench isolation (STI) regions.

Each of the first trench-type isolation regions and the second trench-type isolation regions is DTI regions, and the second trench-type isolation regions are formed before the first trench-type isolation regions.

According to embodiments, further comprising second trench-type isolation regions extending vertically from the first surface to the first trench-type isolation regions, the first trench-type isolation regions and the second trench -type isolated regions do not contact each other.

The transfer gate may extend to the inside of the photoelectric conversion region.

The negatively charged material may be hafnium oxide (HfO) or hafnium dioxide (HfO2).

A BSI image sensor according to an embodiment of the present invention includes a pixel array including a plurality of pixels generating a plurality of pixel signals in response to incident light, and a signal processing circuit outputting image data based on the plurality of pixel signals. wherein each of the plurality of pixels is responsive to a semiconductor substrate including a first surface and a second surface, the first surface and the second surface, and the incident light received through the second surface a photoelectric conversion region to generate electric charges, first trench-type isolation regions surrounding the photoelectric conversion region and extending in a vertical direction from the second surface; and below the photoelectric conversion region in the semiconductor substrate ) and a transfer gate extending vertically from the first surface to the photoelectric conversion region and transferring the charges of the photoelectric conversion region to the floating diffusion region, the first trench-type The isolated regions contain negatively charged material.

A portable electronic device according to an embodiment of the present invention includes a backside illuminated (BSI) image sensor and a processor that controls the operation of the BSI image sensor. The BSI image sensor includes a pixel array including a plurality of pixels generating a plurality of pixel signals in response to incident light, and a signal processing circuit outputting image data based on the plurality of pixel signals. Each of the plurality of pixels has a semiconductor substrate including a first surface and a second surface, is formed between the first surface and the second surface, and generates electric charges in response to the incident light received through the second surface. a photoelectric conversion region generating a photoelectric conversion region, first trench-type isolation regions surrounding the photoelectric conversion region and extending in a vertical direction from the second surface, formed below the photoelectric conversion region in the semiconductor substrate a floating diffusion region and a transfer gate extending vertically from the first surface to the photoelectric conversion region and transferring the charges of the photoelectric conversion region to the floating diffusion region, the first trench-type isolation regions comprising: negatively charged material.

The portable electronic device further includes a camera serial interface for transmitting the image data to the processor.

A pixel including back deep trench isolation (DTI) and a vertical transfer gate according to an embodiment of the present invention has an effect of reducing crosstalk that may occur between pixels.

A pixel including a back DTI, a vertical transfer gate, and a negative charge material inside the back DTI according to an embodiment of the present invention can reduce dark current as well as crosstalk that may occur between pixels. It works.

A detailed description of each drawing is provided in order to more fully understand the drawings recited in the Detailed Description of the Invention.
1A to 1N are cross-sectional views illustrating methods of manufacturing pixels according to embodiments of the present invention.
1O is a cross-sectional view of pixels according to embodiments of the present invention.
2A to 2L are cross-sectional views for explaining methods of manufacturing pixels according to embodiments of the present invention.
2M is a cross-sectional view of pixels according to example embodiments.
3A through 3L are cross-sectional views for explaining methods of manufacturing pixels according to embodiments of the present invention.
3M is a cross-sectional view of pixels according to embodiments of the present invention.
4A and 4B are cross-sectional views illustrating pixels manufactured using manufacturing methods according to embodiments of the present invention.
5A and 5B are cross-sectional views illustrating pixels manufactured using manufacturing methods according to embodiments of the present invention.
6A and 6B are cross-sectional views illustrating pixels manufactured using manufacturing methods according to embodiments of the present invention.
7A and 7B are cross-sectional views illustrating pixels manufactured using manufacturing methods according to embodiments of the present invention.
8A and 8B are cross-sectional views illustrating pixels manufactured using manufacturing methods according to embodiments of the present invention.
9 is a block diagram illustrating an image processing apparatus including pixels manufactured according to an embodiment of the present invention.
10 is a block diagram illustrating an image processing apparatus including pixels manufactured according to an embodiment of the present invention.

The specific structural or functional description of the embodiments according to the concept of the present invention disclosed in this specification is only illustrated for the purpose of explaining the embodiments according to the concept of the present invention, and the embodiments according to the concept of the present invention are It may be implemented in various forms and is not limited to the embodiments described herein.

Since the embodiments according to the concept of the present invention may have various changes and may have various forms, the embodiments will be illustrated in the drawings and described in detail herein. However, this is not intended to limit the embodiments according to the concept of the present invention to specific disclosed forms, and includes all modifications, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first or second may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one element from another, for example, without departing from the scope of the inventive concept, a first element may be termed a second element and similarly a second element. A component may also be referred to as a first component.

When a component is referred to as being “connected” or “connected” to another component, it may be directly connected or connected to the other component, but it is understood that other components may exist in between. it should be On the other hand, when it is mentioned that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle. Other expressions describing the relationship between elements, such as "between" and "immediately between" or "neighboring to" and "directly adjacent to", etc., should be interpreted similarly.

The terms used herein are used only to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In this specification, terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described herein is present, but one or more other features It is to be understood that it does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present specification. does not

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

A front deep trench isolation (FDTI) region herein refers to a DTI region extending (or formed) vertically from a first surface (or upper portion) of a semiconductor substrate (eg, an epitaxial layer). mean, a back deep trench isolation (BDTI) region is a DTI region extending (or formed) vertically from a second surface (or lower portion) of the semiconductor substrate (eg, an epitaxial layer). means Here, the second surface means an opposite surface of the first surface. The FDTI region may simply be referred to as FDTI, and the BDTI region may simply be referred to as BDTI.

For example, FDTI may mean a DTI formed in a process of manufacturing a frontside illuminated (FSI) image sensor, and BDTI may mean a DTI formed in a process of manufacturing a backside illuminated (BSI) image sensor.

In addition, the manufacturing methods illustrated in FIGS. 1A to 8B are the pixels 10A, 10A-1, 10B, 10B-1, 10C, 10C-1, 10D, 10D-1, 10E, and 10E according to embodiments of the present invention. -1, 10F, 10F-1, 10G, 10G-1, 10F, or 10H-1) As illustratively shown to describe the respective manufacturing methods, each pixel 10A, 10A-1, 10B, 10B-1 , 10C, 10C-1, 10D, 10D-1, 10E, 10E-1, 10F, 10F-1, 10G, 10G-1, 10F or 10H-1) are each Pixel (10A, 10A-1, 10B, 10B-1, 10C, 10C-1, 10D, 10D-1, 10E, 10E-1, 10F, 10F-1, 10G, 10G-1, 10F or 10H-1) may vary depending on the manufacturer.

1A to 8B, pixel units 10A, 10A-1, 10B, 10B-1, 10C, 10C-1, 10D, 10D-1, 10E, 10E-1, 10F, 10F-1, 10G, 10G-1, 10F or 10H-1) are shown as examples, but the pixel array may include two or more pixels. Pixel unit (10A, 10A-1, 10B, 10B-1, 10C, 10C-1, 10D, 10D-1, 10E, 10E-1, 10F, 10F-1, 10G, 10G-1, 10F or 10H-1 ) may be simply described as a “pixel”, but as described above, a pixel may mean a pixel unit including two or more pixels.

Although it is described in this specification that the second step is performed after the first step and the third step is performed after the second step, the order of the first step to the third step may be changed according to embodiments In addition, at least two steps from the first step to the third step may be performed simultaneously. In addition, even if it is described that the second layer (or first element) is formed (or implemented) on or above the first layer (or second element), between the first layer and the second layer , one or more layers (or elements) may be formed (or implemented).

1A to 1N are cross-sectional views illustrating methods of manufacturing pixels 10A or 10A-1 according to embodiments of the present invention. 1A , an epitaxial layer (eg, p- epitaxial layer; 120 may be formed on the silicon substrate (eg, p+ silicon substrate) 110 .

For example, the p− epitaxial layer 120 may be grown using a silicon source gas to have the same crystal structure as that of the p+ silicon substrate 110 . In some embodiments, each epitaxial layer 120 , 220 , 320 , or 420 may be simply referred to as a semiconductor substrate. For example, the silicon source gas may include silane, dichlorosilane (DCS), trichlorosilane (TCS), hexachlorodisilane (HCS), or a combination thereof. The p-epitaxial layer 120 may include a first surface (or upper region; SUF1) and a second surface (or lower region; SUF2).

Referring to FIG. 1B , a plurality of first isolation regions (STI1 and STI2) are to be created in the p-epitaxial layer 120 by an etching process and/or a deposition process. can For example, the plurality of first isolation regions STI1 and STI2 are trench-type isolation regions and may be shallow trench isolation (STI) regions.

Referring to FIG. 1C , the photoelectric conversion regions PD1 and PD2 may be formed between the first surface SUF1 and the second surface SUF2 by an ion implantation process. The photoelectric conversion regions PD1 and PD2 may generate electric charges in response to incident light. A photodiode, a phototransistor, a photogate, or a pinned photodiode may be formed in each of the photoelectric conversion regions PD1 and PD2.

Referring to FIG. 1D , a plurality of openings may be formed at a predetermined depth from the first surface SUF1 of the p-epitaxial layer 120 . The plurality of openings may be formed by a wet etching process or a dry etching process. The depth and/or shape of each of the plurality of openings may be variously modified according to the depth and/or shape of each of the plurality of transfer gates (VTG1 and VTG2 in FIG. 1E ). After the plurality of openings are formed, an insulating layer may be formed on the first surface SUF1 to a predetermined thickness.

Referring to FIGS. 1D and 1E , each of the transfer gates VTG1 and VTG2 may be formed on or above each corresponding opening. For example, each of the transfer gates VTG1 and VTG2 may extend (or form) from the first surface SUF1 toward the respective photoelectric conversion regions PD1 and PD2.

Each of the transfer gates VTG1 and VTG2 and the other gates 131 and 133 may be formed simultaneously. For example, the other gates 131 and 133 may include a gate of a reset transistor and a gate of a source follower. For example, each of the transfer gates VTG1 , VTG2 , 131 , and 133 may be implemented with polysilicon, a metal, or a metal compound. As described above, an insulating layer may be formed between each of the transfer gates VTG1 , VTG2 , 131 , and 133 and the first surface SUF1 .

Referring to FIG. 1F , each of the floating diffusion regions FD1 and FD2 may be formed at a predetermined depth from the first surface SUF1 of the p-epitaxial layer 120 . In some embodiments, each of the floating diffusion regions FD1 and FD2 may be doped with n+ impurities.

Referring to FIG. 1G , the metal wiring region 130 may be formed on or above the p-epitaxial layer 120 . The metal wiring region 130 may include a plurality of metals and a plurality of contacts formed between the dielectric 135 . The plurality of metals may be connected to each of the transfer gates VTG1 , VTG2 , 131 , and 133 through the plurality of contacts. For example, the dielectric 135 may mean an inter-layer dielectric or inter level dielectric (ILD) or an inter-metal dielectric (IMD).

Referring to FIG. 1H , a sustaining wafer 140 is bonded on the metal wiring region 130 . For example, the holding wafer 140 may be used to hold (or support) the p-epitaxial layer 120 .

Fig. 1H is turned over to Fig. 1I. Referring to FIG. 1J , the p+ silicon substrate 110 is removed. In some embodiments, the p+ silicon substrate 110 may be ground according to a mechanical method and/or a chemical method.

Referring to FIG. 1K , to form second isolation regions, for example, trench-type isolation regions BDTI1 , BDTI2 , and BDTI3 , the corresponding regions on the second surface SUF2 of the p-epitaxial layer 120 are etched vertically. Accordingly, trenches OP1 , OP2 , and OP3 corresponding to the trench-type isolation regions BDTI1 , BDTI2 , and BDTI3 may be formed.

1K and 11 , the second surface SUF2 and the trenches OP1 , OP2 , and OP3 may be coded with a negative charge material NCM. For example, to code the second surface SUF2 and the trenches OP1 , OP2 , and OP3 , a negative charge material NCM is applied over the second surface SUF2 and of the trenches OP1 , OP2 , and OP3 . It may be deposited thereon. For example, the negative charge material NCM may be formed on the second surface SUF2 and on the trenches OP1 , OP2 , and OP3 to a predetermined thickness. Also, as shown in FIG. 11 , a dielectric material (DM) may be formed over the negative charge material (NCM). For example, empty spaces of the trenches OP1 , OP2 , and OP3 coded with the negative charge material NCM may be filled with the dielectric DM, and the dielectric DM may be formed on the second surface SUF2. . Accordingly, dark current is reduced and crosstalk is reduced.

The negative charge material (NCM) may be implemented as an oxide of a metal element. The metal element may be hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), yttrium (Y), or lanthanoid. . For example, the negative charge material NCM may be implemented with hafnium oxide (HfO) or hafnium dioxide (HfO2). Here, the negatively charged material (NCM) may refer to a material having a negative fixed charge.

The trench-type isolation regions BDTI1 , BDTI2 , and BDTI3 may fully extend (or form) from the second surface SUF2 to the first surface SUF1 . Each of the trench type isolation regions BDTI1 , BDTI2 , and BDTI3 may mean a back batch deep trench isolation (DTI) region.

Referring to FIG. 1M , color filters CF1 and CF2 may be formed on or above a dielectric material (DM). The first color filter CF1 may be any one of a red color filter, a green color filter, and a blue color filter, and the second color filter CF1 may include the red color filter and the It may be another one of a green color filter and the blue color filter. Referring to FIG. 1O , the color filters CF1 and CF2 may be formed on the negative charge material NCM. In some embodiments, the trenches OP1 , OP2 , and OP3 may be filled with a negative charge material NCM.

1N or 1O , each of the microlenses LEN1 and LEN2 may be formed on or above each of the color filters CF1 and CF2 . In some embodiments, a planarization layer such as an over-coating layer may be implemented (or formed) between the microlenses LEN1 and LEN2 and the color filters CF1 and CF2 . A pixel 10A or 10A-1 illustrated in FIG. 1N or 1O may mean a pixel (or pixels) manufactured according to a process for manufacturing a BSI image sensor.

The first photoelectric conversion region PD1 formed between the first surface SUF1 and the second surface SUF2 connects the first microlens LEN1, the first color filter CF1, and the second surface SUF2. Charges may be generated in response to incident light received through the . In addition, the second photoelectric conversion region PD2 formed between the first surface SUF1 and the second surface SUF2 includes the second microlens LEN2 , the second color filter CF2 , and the second surface SUF2 . ) may generate charges in response to the received incident light.

The corresponding two trench-type isolation regions BDTI1 and BDTI2 surround the first photoelectric conversion region PD1 and fully extend (or form) from the second surface SUF2 to the first surface SUF1 . can be In addition, the corresponding two trench-type isolation regions BDTI2 and BDTI3 surround the second photoelectric conversion region PD2 and are to be completely extended (or formed) from the second surface SUF2 to the first surface SUF1. can

When viewed with respect to the second surface SUF2 , each of the floating diffusion regions FD1 and FD2 is formed below each of the photoelectric conversion regions PD1 and PD2 .

The first transfer gate VTG1 vertically extends (or is formed) from the first surface SUF1 toward the first photoelectric conversion region PD1 and transfers charges of the first photoelectric conversion region PD1 in response to a corresponding voltage. It can transmit to the first floating diffusion area FD1. In addition, the second transfer gate VTG2 vertically extends (or is formed) from the first surface SUF1 toward the second photoelectric conversion region PD2, and in response to a corresponding voltage, the second photoelectric conversion region PD2 Charges may be transferred to the second floating diffusion region FD2 .

Each of the transfer gates VTG1 and VTG2 may mean a vertical transfer gate. As back DTIs BDTI1 , BDTI2 , and BDTI3 containing negative charge material (NCM) are formed between pixels (or photoelectric conversion regions PD1 and PD2), dark current and crosstalk are reduced or eliminated can be

2A to 2L are cross-sectional views for explaining methods of manufacturing pixels according to embodiments of the present invention. Referring to FIG. 2A , the p− epitaxial layer 220 may be formed on the p+ silicon substrate 210 . The p-epitaxial layer 220 may include a first surface SUF1 and a second surface SUF2 facing each other. The plurality of first isolation regions STI1 to STI5 may be formed in the p-epitaxial layer 220 by an etching process and/or a deposition process. For example, the plurality of first isolation regions STI1 to STI5 may be trench-type isolation regions and may be STI regions.

Referring to FIG. 2B , the photoelectric conversion regions PD1 and PD2 may be formed between the first surface SUF1 and the second surface SUF2 by an ion implantation process. Referring to FIG. 2C , the plurality of openings may be formed at a predetermined depth from the first surface SUF1 of the p-epitaxial layer 220 . The depth and/or shape of each of the plurality of openings may be variously modified according to the depth and/or shape of each of the plurality of transfer gates (VTG1 and VTG2 in FIG. 2D ). After the plurality of openings are formed, an insulating layer may be formed on the first surface SUF1 to a predetermined thickness.

Referring to FIG. 2D , each of the transfer gates VTG1 and VTG2 may be formed on each opening. For example, each of the transfer gates VTG1 and VTG2 may extend (or form) vertically from the first surface SUF1 toward the respective photoelectric conversion regions PD1 and PD2. In some embodiments, each of the transfer gates VTG1 and VTG2 and other gates 131 and 133 may be formed at the same time.

Referring to FIG. 2E , each of the floating diffusion regions FD1 and FD2 may be formed at a predetermined depth from the first surface SUF1 of the p-epitaxial layer 220 . Referring to FIG. 2F , a metal wiring region 230 may be formed on or above the p-epitaxial layer 220 .

Referring to FIG. 2G , the holding wafer 240 may be bonded on the metal wiring region 230 . For example, the holding wafer 240 may be used to hold (or support) the p-epitaxial layer 220 . Turning Fig. 2G upside down becomes Fig. 2H. Referring to FIG. 2I , the p+ silicon substrate 210 may be removed.

2J and 2K , corresponding to the second surface SUF2 of the p-epitaxial layer 220 to form second isolation regions, such as trench type isolation regions BDTI1 , BDTI2 , and BDTI3 . regions are etched vertically. Accordingly, trenches OP11 , OP12 , and OP13 corresponding to the trench-type isolation regions BDTI1 , BDTI2 , and BDTI3 may be formed. In this case, each of the trenches OP1 , OP2 , and OP3 may be vertically extended (or formed) until it contacts the corresponding respective STIs STI1 , STI3 , and STI5 .

The second surface SUF2 and the trenches OP11 , OP12 , and OP13 may be coded with a negative charge material NCM. For example, to code the surface of the second surface SUF2 and the trenches OP11, OP12, and OP13, a negative charge material NCM is applied to the second surface SUF2 and the trenches OP11, OP12, and OP13. can be deposited on the surface of For example, the negative charge material NCM may be formed to a predetermined thickness on the second surface SUF2 and the surfaces of the trenches OP11 , OP12 , and OP13 . Further, the dielectric DM may be formed over the negative charge material NCM. For example, empty spaces of the trenches OP11 , OP12 , and OP13 coded with the negative charge material NCM may be filled with the dielectric DM. For example, referring to FIGS. 2J and 2M , the trenches OP11 , OP12 , and OP13 may be filled with a negative charge material NCM and a negative charge material NCM may be formed on the second surface SUF2 . .

For example, the negative charge material (NCM) may be implemented with hafnium oxide (HfO) or hafnium dioxide (HfO2). Each of the trench type isolation regions BDTI1 , BDTI2 , and BDTI3 may be implemented as a back DTI.

Referring to FIG. 2L , the color filters CF1 and CF2 may be formed on or above the dielectric DM. Referring to FIG. 2M , the color filters CF1 and CF2 may be formed on or above the negative charge material NCM. Each of the microlenses LEN1 and LEN2 may be formed on or above each of the color filters CF1 and CF2 . According to an embodiment, a planarization layer such as an over-coating layer may be implemented between the microlenses LEN1 and LEN2 and the color filters CF1 and CF2 . In some embodiments, the height H1 of each of the STIs STI1 , STI3 , and STI5 may be smaller than the height H2 of each of the transfer gates VTG1 and VTG2 .

The pixels 10B or 10B-1 illustrated in FIG. 2L or 2M may be pixels manufactured according to processes for manufacturing the BSI image sensor.

The first photoelectric conversion region PD1 formed between the first surface SUF1 and the second surface SUF2 connects the first microlens LEN1, the first color filter CF1, and the second surface SUF2. Charges are generated in response to incident light received through the In addition, the second photoelectric conversion region PD2 formed between the first surface SUF1 and the second surface SUF2 includes the second microlens LEN2 , the second color filter CF2 , and the second surface SUF2 . ) to generate electric charges in response to incident light received through

Corresponding two trench-type isolation regions BDTI1 and BDTI2 surround the first photoelectric conversion region PD1 and are vertically aligned from the second surface SUF2 to the corresponding STIs STI1 and STI3 until contacted. is expanded (or formed). Corresponding two trench-type isolation regions BDTI2 and BDTI3 surround the second photoelectric conversion region PD2, and vertically from the second surface SUF2 until they contact the corresponding STIs STI3 and STI5. is expanded (or formed).

When viewed with respect to the second surface SUF2 , each of the floating diffusion regions FD1 and FD2 is formed below each of the photoelectric conversion regions PD1 and PD2 .

The first transfer gate VTG1 vertically extends (or is formed) from the first surface SUF1 toward the first photoelectric conversion region PD1 and transfers charges of the first photoelectric conversion region PD1 in response to a corresponding voltage. It is transmitted to the first floating diffusion area FD1. In addition, the second transfer gate VTG2 vertically extends (or is formed) from the first surface SUF1 toward the second photoelectric conversion region PD2, and in response to a corresponding voltage, the second photoelectric conversion region PD2 Charges are transferred to the second floating diffusion region FD2.

3A through 3L are cross-sectional views for explaining methods of manufacturing pixels according to embodiments of the present invention. Referring to FIG. 3A , a p− epitaxial layer 320 is formed on a p+ silicon substrate 310 . The plurality of third isolated regions FDTI1 , FDTI2 , and FDTI3 may be vertically extended (or formed) from the first surface SUF1 by an ion implantation process. The plurality of third isolated regions FDTI1 , FDTI2 , and FDTI3 may mean front DTI regions.

Referring to FIG. 3B , a plurality of first isolated regions, for example, the STI regions SDTI1 and STI2 may be vertically generated from the first surface SUF1 by an etching process. In some embodiments, the plurality of DTI regions FDTI1 , FDTI2 , and FDTI3 and the plurality of STI regions SDTI1 and STI2 may be simultaneously generated. In some embodiments, the plurality of STI regions SDTI1 and STI2 may be generated before the plurality of DTI regions FDTI1 , FDTI2 , and FDTI3 .

Referring to FIG. 3C , the photoelectric conversion regions PD1 and PD2 may be formed between the first surface SUF1 and the second surface SUF2 by an ion implantation process.

Referring to FIG. 3D , the plurality of openings may be formed at a predetermined depth from the first surface SUF1 of the p-epitaxial layer 320 . The depth and/or shape of each of the plurality of openings may be variously modified according to the depth and/or shape of each of the plurality of transfer gates VTG1 and VTG2. After the plurality of openings are formed, an insulating layer may be formed on the first surface SUF1 to a predetermined thickness.

Each of the transfer gates VTG1 and VTG2 may be formed on each opening. For example, each of the transfer gates VTG1 and VTG2 may extend (or form) vertically from the first surface SUF1 toward the respective photoelectric conversion regions PD1 and PD2. Each of the transfer gates VTG1 and VTG2 and the other gates 131 and 133 may be formed simultaneously.

Referring to FIG. 3E , each of the floating diffusion regions FD1 and FD2 may be formed at a predetermined depth from the first surface SUF1 of the p-epitaxial layer 320 . Referring to FIG. 3F , a metal wiring region 330 is formed on or above the p-epitaxial layer 320 . Referring to FIG. 3G , the holding wafer 340 is bonded on the metal wiring region 330 . For example, the holding wafer 340 may be used to hold (or support) the p-epitaxial layer 320 .

Fig. 3G is turned over to Fig. 3H. Referring to FIG. 3I , the p+ silicon substrate 310 is removed. 3J and 3K , corresponding to the second surface SUF2 of the p-epitaxial layer 320 to form second isolation regions, such as trench type isolation regions BDTI1 , BDTI2 , and BDTI3 . Areas to be etched may be vertically etched. Accordingly, trenches OP21 , OP22 , and OP23 corresponding to the trench-type isolation regions BDTI1 , BDTI2 , and BDTI3 may be formed. At this time, each of the trenches OP21, OP22, and OP23 is expanded (or formed) until it contacts the corresponding respective front DTIs FTI1, FTI2, and FTI3.

3J and 3K , the second surface SUF2 and the trenches OP21 , OP22 , and OP23 may be coded with a negative charge material NCM. For example, to code the surface of the second surface SUF2 and the trenches OP21, OP22, and OP23, a negative charge material NCM is applied to the second surface SUF2 and the trenches OP21, OP22, and OP23. It can be deposited on For example, the negative charge material NCM may be formed to a predetermined thickness on the second surface SUF2 and the trenches OP21 , OP22 , and OP23 . Further, the dielectric DM may be formed over the negative charge material NCM. Empty spaces of the trenches OP21 , OP22 , and OP23 coded with the negative charge material NCM may be filled with the dielectric DM. In some embodiments, referring to FIGS. 3J and 3M , the trenches OP21 , OP22 , and OP23 are filled with a negative charge material NCM, and the negative charge material NCM is formed on the second surface SUF2 . can be formed.

Each of the trench type isolation regions BDTI1 , BDTI2 , and BDTI3 may be implemented as a back DTI.

Referring to FIG. 3L , the color filters CF1 and CF2 may be formed on or above the dielectric DM. Referring to FIG. 3M , the color filters CF1 and CF2 may be formed on or above the negative charge material NCM. The microlenses LEN1 and LEN2 may be formed on or above the color filters CF1 and CF2. According to an embodiment, a planarization layer such as an over-coating layer may be implemented between the microlenses LEN1 and LEN2 and the color filters CF1 and CF2 . In some embodiments, the height H1 of the STI region SDTI1 or STI2 is smaller than the height H2 of the transfer gate VTG1 or VTG2, and the height H2 of the transfer gate VTG1 or VTG2 is the front DTI (FTI1). , FTI2, or FTI3) may be smaller than the height (H3).

The pixels 10C or 10C-1 illustrated in FIG. 3L or 3M may be pixels manufactured according to processes for manufacturing the BSI image sensor.

Each of the photoelectric conversion regions PD1 and PD2 generates electric charges in response to the incident light received through the second surface SUF2.

Corresponding two trench-type isolation regions BDTI1 and BDTI2 surround the first photoelectric conversion region PD1 and extend from the second surface SUF2 until they come into contact with the corresponding front DTIs FDTI1 and FDTI2. (or formed) The corresponding two trench-type isolation regions BDTI2 and BDTI3 surround the second photoelectric conversion region PD2 and extend from the second surface SUF2 to the corresponding front DTIs FDTI2 and FDTI3. (or formed)

When viewed with respect to the second surface SUF2 , each of the floating diffusion regions FD1 and FD2 is formed below each of the photoelectric conversion regions PD1 and PD2 .

The first transfer gate VTG1 vertically extends (or is formed) from the first surface SUF1 toward the first photoelectric conversion region PD1 and transfers charges of the first photoelectric conversion region PD1 in response to a corresponding voltage. It is transmitted to the first floating diffusion area FD1. The second transfer gate VTG2 vertically extends (or is formed) from the first surface SUF1 toward the second photoelectric conversion region PD2 and transfers charges of the second photoelectric conversion region PD2 in response to a corresponding voltage. It is transmitted to the second floating diffusion area FD2.

4A and 4B are cross-sectional views illustrating pixels manufactured using manufacturing methods according to embodiments of the present invention. Referring to FIGS. 2L and 4A , the STI STI1 vertically extended from the first surface SUF1 and the back DTI BDTI1 vertically extended from the second surface SUF2 do not contact each other. The STI extending vertically from the first surface SUF1 (STI3) and the back DTI extending vertically from the second surface SUF2 (BDTI2) do not contact each other, and the STI vertically extended from the first surface SUF1 (STI5) and the back DTI (BDTI3) extending vertically from the second surface (SUF2) do not contact each other.

Each configuration 220 , 230 , and 240 of FIG. 2L may correspond to each configuration 420 , 430 , and 440 of FIG. 4A . Each component 220 , 230 , and 240 of FIG. 2M may correspond to each component 420 , 430 , and 440 of FIG. 4B .

5A and 5B are cross-sectional views illustrating pixels manufactured using manufacturing methods according to embodiments of the present invention. of the pixel 10A shown in FIG. The manufacturing method and the manufacturing method of the pixel 10E shown in FIG. 5A are the same or similar. Pixel 10A-1 shown in Fig. 10, except that each transfer gate VTG1 and VTG2 extends (or is formed) vertically from the first surface SUF1 to the inside of each photoelectric conversion region PD1 and PD2. ) and the method of manufacturing the pixel 10E-1 shown in FIG. 5B are the same or similar.

6A and 6B are cross-sectional views illustrating pixels manufactured using manufacturing methods according to embodiments of the present invention. of the pixel 10B shown in FIG. The manufacturing method and the manufacturing method of the pixel 10F shown in Fig. 6A are the same or similar. Pixel 10B-1 shown in Fig. 2M, except that each of the transfer gates VTG1 and VTG2 extends (or is formed) vertically from the first surface SUF1 to the inside of each photoelectric conversion region PD1 and PD2. ) and the method of manufacturing the pixel 10F-1 shown in FIG. 6B are the same or similar.

7A and 7B are cross-sectional views illustrating pixels manufactured using manufacturing methods according to embodiments of the present invention. of the pixel 10C shown in Fig. 3L, except that each of the transfer gates VTG1 and VTG2 extends (or is formed) vertically from the first surface SUF1 to the inside of each photoelectric conversion region PD1 and PD2. The manufacturing methods and the manufacturing methods of the pixel 10G shown in FIG. 7A are the same or similar. Pixel 10C-1 shown in Fig. 3M, except that each transfer gate VTG1 and VTG2 extends (or is formed) vertically from the first surface SUF1 to the inside of each photoelectric conversion region PD1 and PD2. ) and manufacturing methods of the pixel 10G-1 shown in FIG. 7B are the same or similar.

8A and 8B are cross-sectional views illustrating pixels manufactured using manufacturing methods according to embodiments of the present invention. of the pixel 10D shown in FIG. 4A except that each of the transfer gates VTG1 and VTG2 extends (or is formed) vertically from the first surface SUF1 to the inside of each photoelectric conversion region PD1 and PD2. The manufacturing methods and the manufacturing methods of the pixel 10H shown in FIG. 8A are the same or similar. Pixel 10D-1 shown in FIG. 4B except that each of the transfer gates VTG1 and VTG2 extends (or is formed) vertically from the first surface SUF1 to the inside of each photoelectric conversion region PD1 and PD2. ) and manufacturing methods of the pixel 10H-1 shown in FIG. 8B are the same or similar.

9 is a block diagram illustrating an image processing apparatus including pixels manufactured according to embodiments of the present invention. 1A to 9 , the image processing apparatus 500 may be implemented as a digital camera, a camcorder, or a portable electronic device including a CMOS image sensor 505 . The portable electronic device may be implemented as a mobile phone, a smart phone, a tablet PC, a mobile internet device (MID), a wearable computer, an Internet of things (IoT) device, or an Internet of everything (IoE) device. .

The image processing apparatus 500 includes an optical lens 503 , a CMOS image sensor 505 , a digital signal processor (DSP) 600 , and a display 640 .

The CMOS image sensor 505 may generate image data IDATA of the subject 501 incident through the optical lens 503 . The CMOS image sensor 505 includes a pixel array 510 , a row driver 520 , a readout circuit 525 , a timing generator 530 , a control register block 550 , a reference signal generator 560 , and a buffer 570 . ) is included. The signal processing circuit may include a readout circuit 525 and a buffer 570 .

The pixel array 510 includes a plurality of pixels 10 that generate a plurality of pixel signals in response to incident light. Each of the plurality of pixels 10 includes corresponding pixels 10A, 10A-1, 10B, 10B-1, 10C, 10C-1, 10D, 10D-1, 10E, 10E-1, 10F, 10F-1, 10G, 10G-1, 10H, or 10H-1, collectively “10”). The pixel array 510 includes a plurality of pixels 10 arranged in a matrix form. Each of the plurality of pixels 10 transmits a corresponding output signal to a corresponding column line.

The row driver 520 drives control signals for controlling the operation of each of the plurality of pixels 10 to the pixel array 510 under the control of the timing generator 530 . For example, the row driver 520 may control the operation of pixels in a row unit. The row driver 520 may perform a function of a control signal generator capable of generating control signals.

The timing generator 530 controls operations of the row driver 520 , the readout circuit 525 , and the reference signal generator 560 according to the control of the control register block 550 . The readout circuit 525 includes an analog-to-digital converter 526 for each column and a memory 527 for each column. In some embodiments, the analog-to-digital converter 526 may perform a correlated double sampling function. The readout circuit 525 outputs a digital image signal corresponding to the pixel signal output from each pixel 10 of the pixel array 510 .

The control register block 550 controls operations of the timing generator 530 , the reference signal generator 560 , and the buffer 570 under the control of the DSP 600 . The buffer 570 transmits image data IDATA corresponding to the plurality of digital image signals output from the readout circuit 525 to the DSP 600 . The signal processing circuit processes a plurality of pixel signals output from the pixel array 510 (eg, including correlated double sampling and analog-to-digital conversion), and outputs image data IDATA corresponding to the result of the processing. can do.

The DSP 600 includes an image signal processor (ISP) 610 , a sensor controller 620 , and an interface 630 . The ISP 610 controls the sensor controller 620 that controls the control register block 550 , and the interface 630 .

According to embodiments, each of the CMOS image sensor 505 and the DSP 600 may be implemented as a chip, and may be implemented as a single package, for example, a multi-chip package. According to embodiments, each of the CMOS image sensor 505 and the ISP 610 may be implemented as a chip, and may be implemented as a single package, for example, a multi-chip package.

The ISP 610 processes the image data IDATA transmitted from the buffer 570 and transmits the processed image data to the interface 630 . The sensor controller 620 may generate various control signals for controlling the control register block 550 according to the control of the ISP 610 . The interface 630 may transmit image data processed by the ISP 610 to the display 640 . The display 640 may display image data output from the interface 630 .

10 is a block diagram illustrating an image processing apparatus including pixels manufactured according to an embodiment of the present invention. 1A to 10 , the image processing apparatus 700 may be implemented as a portable electronic device capable of using (or supporting) a mobile industry processor interface ( ^MIPI® ).

As described above, the portable electronic device includes a CMOS image sensor 505 and a processing circuit that may include image data IDATA output from the CMOS image sensor 505 .

The image processing apparatus 700 includes an application processor (AP) 710 , an image sensor 505 , and a display 730 . A camera serial interface (CSI) host 713 implemented in the AP 710 may serially communicate with the CSI device 506 of the image sensor 505 through CSI. According to an embodiment, the CSI host 713 may include a deserializer (DES), and the CSI device 506 may include a serializer (SER). The AP 710 may be implemented as an integrated circuit or a system on chip (SoC).

A display serial interface (DSI) host 711 implemented in the AP 710 may serially communicate with the DSI device 731 of the display 730 through the DSI. According to an embodiment, the DSI host 711 may include a serializer SER, and the DSI device 731 may include a deserializer DES. Each of the deserializer DES and the serializer SER may process an electrical signal or an optical signal.

The image processing apparatus 700 may further include a radio frequency (RF) chip 740 capable of communicating with the AP 710 . A physical layer (PHY) 715 of the AP 710 and the PHY 741 of the RF chip 740 may exchange data according to MIPI DigRF. The CPU 717 may control the operation of the DSI host 711 , the CSI host 713 , and the PHY 715 .

The image processing device 700 includes a GPS receiver 750 , a memory 751 such as dynamic random access memory (DRAM), a data storage device 753 implemented with a nonvolatile memory such as a NAND flash-based memory, and a microphone 755 . ), and/or a speaker 757 may be further included.

The image processing apparatus 700 includes at least one communication protocol (or communication standard), for example, WiMAX (worldwide interoperability for microwave access; 759), WLAN (Wireless LAN; 761), UWB (ultra-wideband; 763), or LTE It is possible to communicate with an external device using a long term evolution ( ^TM ) 765 or the like. The image processing device 700 may communicate with an external wireless communication device using Bluetooth or WiFi.

Although the present invention has been described with reference to the embodiment shown in the drawings, which is merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

10A to 10H, 10; pixel
110, 210, 310, and 410;
STI1~STI5; STI (shallow trench isolation) area
PD1, PD2; photoelectric conversion area
VTG1, VTG2; transfer gate, vertical transfer gate
FD1, FD2; floating diffusion area
SUF1; first surface, upper surface
SUF2; second surface, lower surface
BDTI1-BDTI3; Back deep trench isolation (DTI) region
FDTI1 to FDTI3; Front deep trench isolation (DTI) region
500, 600; image processing unit
505; image sensor
510; pixel array
610; application processor

Claims (20)

a semiconductor substrate comprising a first surface and a second surface;
a photoelectric conversion region formed between the first surface and the second surface and generating charges in response to incident light received through the second surface;
first trench-type isolation regions surrounding the photoelectric conversion region and extending vertically from the second surface;
a floating diffusion region formed below the photoelectric conversion region in the semiconductor substrate;
a transfer gate extending vertically from the first surface to the photoelectric conversion region and transferring the charges of the photoelectric conversion region to the floating diffusion region;
a metal wiring region comprising a dielectric layer disposed on the first surface of the substrate and metals penetrating the dielectric layer;
a second gate disposed in the metal wiring region adjacent to the first surface of the substrate and spaced apart from the transfer gate; and
a second isolation region of an insulating material within the substrate;
wherein the first trench-type isolation regions comprise negatively charged material;
a lower surface of the second isolation region is coplanar with the first surface of the substrate, and a lower surface of the second isolation region overlaps the transfer gate and the second gate along the first surface of the substrate;
The metal is a pixel of a backside illuminated (BSI) image sensor electrically connected to the transfer gate and the second gate. According to claim 1,
wherein the first trench-type isolation regions extend from the second surface to the first surface. According to claim 1,
and second trench-type isolation regions extending vertically from the first surface;
wherein the first trench-type isolation regions and the second trench-type isolation regions are in contact with each other. 4. The method of claim 3,
When the first trench-type isolation regions are deep trench isolation (DTI) regions, the second trench-type isolation regions are shallow trench isolation (STI) regions. 4. The method of claim 3,
each of the first trench-type isolation regions and the second trench-type isolation regions are DTI regions;
wherein the second trench-type isolation regions are formed before the first trench-type isolation regions. According to claim 1,
second trench-type isolation regions extending vertically from the first surface to the first trench-type isolation regions;
wherein the first trench-type isolation regions and the second trench-type isolation regions do not contact each other. According to claim 1,
The transmission gate is a pixel of the BSI image sensor extending to the inside of the photoelectric conversion region. According to claim 1,
wherein the negatively charged material is hafnium oxide (HfO) or hafnium dioxide (HfO2). a pixel array including a plurality of pixels generating a plurality of pixel signals in response to incident light; and
a signal processing circuit outputting image data based on the plurality of pixel signals;
Each of the plurality of pixels,
a semiconductor substrate comprising a first surface and a second surface;
a photoelectric conversion region formed between the first surface and the second surface and generating charges in response to the incident light received through the second surface;
first trench-type isolation regions surrounding the photoelectric conversion region and extending in a vertical direction from the second surface;
a floating diffusion region formed below the photoelectric conversion region in the semiconductor substrate;
a transfer gate extending vertically from the first surface to the photoelectric conversion region and transferring the charges of the photoelectric conversion region to the floating diffusion region;
a metal wiring region comprising a dielectric layer disposed on the first surface of the substrate and metals penetrating the dielectric layer;
a second gate disposed in the metal wiring region adjacent to the first surface of the substrate and spaced apart from the transfer gate; and
a second isolation region of an insulating material within the substrate;
wherein the first trench-type isolation regions comprise negatively charged material;
a lower surface of the second isolation region is coplanar with the first surface of the substrate, and a lower surface of the second isolation region overlaps the transfer gate and the second gate along the first surface of the substrate;
The metal is a backside illuminated (BSI) image sensor electrically connected to the transfer gate and the second gate. 10. The method of claim 9,
wherein the first trench-type isolation regions extend from the second surface to the first surface. 10. The method of claim 9,
and second trench-type isolation regions extending vertically from the first surface;
The first trench-type isolation regions and the second trench-type isolation regions are in contact with each other. 12. The method of claim 11,
When the first trench-type isolation regions are back deep trench isolation (DTI) regions,
wherein the second trench-type isolation regions are front DTI regions or shallow trench isolation (STI) regions. 12. The method of claim 11,
A length of each of the first trench-type isolation regions is longer than a length of each of the second trench-type isolation regions. 10. The method of claim 9,
second trench-type isolation regions extending vertically from the first surface to the first trench-type isolation regions;
The first trench-type isolation regions and the second trench-type isolation regions do not contact each other. a backside illuminated (BSI) image sensor; and
A processor for controlling the operation of the BSI image sensor,
The BSI image sensor is
a pixel array including a plurality of pixels generating a plurality of pixel signals in response to incident light; and
a signal processing circuit outputting image data based on the plurality of pixel signals;
Each of the plurality of pixels,
a semiconductor substrate comprising a first surface and a second surface;
a photoelectric conversion region formed between the first surface and the second surface and generating charges in response to the incident light received through the second surface;
first trench-type isolation regions surrounding the photoelectric conversion region and extending in a vertical direction from the second surface;
a floating diffusion region formed below the photoelectric conversion region in the semiconductor substrate;
a transfer gate extending vertically from the first surface to the photoelectric conversion region and transferring the charges of the photoelectric conversion region to the floating diffusion region;
a metal wiring region comprising a dielectric layer disposed on the first surface of the substrate and metals penetrating the dielectric layer;
a second gate disposed in the metal wiring region adjacent to the first surface of the substrate and spaced apart from the transfer gate; and
a second isolation region of an insulating material within the substrate;
the first trench-type isolation regions comprise negatively charged material;
a lower surface of the second isolation region is coplanar with the first surface of the substrate, and a lower surface of the second isolation region overlaps the transfer gate and the second gate along the first surface of the substrate;
wherein the metals are electrically connected to the transfer gate and the second gate. 16. The method of claim 15,
The portable electronic device further comprising a camera serial interface for transmitting the image data to the processor. 16. The method of claim 15,
wherein the first trench-type isolation regions extend from the second surface to the first surface. 16. The method of claim 15,
and second trench-type isolation regions extending vertically from the first surface;
wherein the first trench-type isolation regions and the second trench-type isolation regions are in contact with each other. 19. The method of claim 18,
When the first trench-type isolation regions are back deep trench isolation (DTI) regions,
wherein the second trench-type isolation regions are front DTI regions or shallow trench isolation (STI) regions. 16. The method of claim 15,
second trench-type isolation regions extending vertically from the first surface to the first trench-type isolation regions;
The first trench-type isolation regions and the second trench-type isolation regions do not contact each other.

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