KR102396928B1 - Three dimensional flash memory based on oxide semiconductor channel materials - Google Patents

Abstract

A three-dimensional flash memory based on an oxide semiconductor channel material is disclosed. According to an embodiment, in the 3D flash memory, a string extending in one direction on a substrate, the string extending in the one direction, and charge storage extending in the one direction to surround the channel layer and the channel layer extending in the one direction including layers; at least one selection line vertically connected to an upper end or lower end of the string; and a plurality of word lines vertically connected to the string while being positioned above or below the at least one selection line, wherein the channel layer is formed of an oxide semiconductor material.

Description

THREE DIMENSIONAL FLASH MEMORY BASED ON OXIDE SEMICONDUCTOR CHANNEL MATERIALS

The following embodiments relate to a three-dimensional flash memory, and more particularly, a technology for a three-dimensional flash memory in which a channel layer is formed of an oxide semiconductor material.

A flash memory device is an Electrically Erasable Programmable Read Only Memory (EEPROM), the memory being, for example, in a computer, digital camera, MP3 player, game system, memory stick. ) can be commonly used. Such a flash memory device electrically controls input/output of data by Fowler-Nordheimtunneling or hot electron injection.

Specifically, referring to FIG. 1 showing a conventional three-dimensional flash memory array, the three-dimensional flash memory array includes a common source line CSL, a bit line BL, and a common source line CSL and a bit line BL. ) may include a plurality of cell strings (CSTR) disposed between.

The bit lines are two-dimensionally arranged, and a plurality of cell strings CSTR are connected in parallel to each of the bit lines. The cell strings CSTR may be commonly connected to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the plurality of bit lines and one common source line CSL. In this case, there may be a plurality of common source lines CSL, and the plurality of common source lines CSL may be two-dimensionally arranged. Here, the same voltage may be applied to the plurality of common source lines CSL, or each of the plurality of common source lines CSL may be electrically controlled.

Each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit line BL, and ground and string select transistors GST and SST. ) may be formed of a plurality of memory cell transistors MCT disposed between. In addition, the ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be commonly connected to sources of the ground select transistors GST. In addition, the ground select line GSL, the plurality of word lines WL0 - WL3 and the plurality of string select lines SSL disposed between the common source line CSL and the bit line BL are ground selectable. It may be used as electrode layers of the transistor GST, the memory cell transistors MCT, and the string select transistors SST, respectively. In addition, each of the memory cell transistors MCT includes a memory element. Hereinafter, the string selection line SSL may be expressed as an upper selection line USL, and the ground selection line GSL may be expressed as a lower selection line LSL.

On the other hand, the conventional 3D flash memory increases the degree of integration by vertically stacking cells in order to meet the excellent performance and low price demanded by consumers.

For example, referring to FIG. 2 showing the structure of a conventional three-dimensional flash memory, in the conventional three-dimensional flash memory, interlayer insulating layers 211 and horizontal structures 250 are alternately formed on a substrate 200 . Repeatedly formed electrode structures 215 are disposed and manufactured. The interlayer insulating layers 211 and the horizontal structures 250 may extend in the first direction. The interlayer insulating layers 211 may be, for example, a silicon oxide layer, and the lowermost interlayer insulating layer 211a of the interlayer insulating layers 211 may have a thickness smaller than that of the other interlayer insulating layers 211 . Each of the horizontal structures 250 may include first and second blocking insulating layers 242 and 243 and an electrode layer 245 . A plurality of electrode structures 215 may be provided, and the plurality of electrode structures 215 may be disposed to face each other in a second direction crossing the first direction. The first and second directions may correspond to the x-axis and the y-axis of FIG. 2 , respectively. Trenches 240 separating the plurality of electrode structures 215 may extend in the first direction. Highly doped impurity regions may be formed in the substrate 200 exposed by the trenches 240 , so that a common source line CSL may be disposed. Although not shown, isolation insulating layers filling the trenches 240 may be further disposed.

Vertical structures 230 penetrating the electrode structure 215 may be disposed. For example, in a plan view, the vertical structures 230 may be arranged in a matrix form along the first and second directions. As another example, the vertical structures 230 may be arranged in the second direction, and may be arranged in a zigzag shape in the first direction. Each of the vertical structures 230 may include a passivation layer 224 , a charge storage layer 225 , a tunnel insulating layer 226 , and a channel layer 227 . For example, the channel layer 227 may be disposed in a hollow tube shape therein, and in this case, a buried film 228 filling the inside of the channel layer 227 may be further disposed. A drain region D may be disposed on the channel layer 227 , and a conductive pattern 229 may be formed on the drain region D to be connected to the bit line BL. The bit line BL may extend in a direction crossing the horizontal electrodes 250 , for example, in a second direction. For example, the vertical structures 230 aligned in the second direction may be connected to one bit line BL.

The first and second blocking insulating layers 242 and 243 included in the horizontal structures 250 and the charge storage layer 225 and the tunnel insulating layer 226 included in the vertical structures 230 are the 3D flash memory. It can be defined as an oxide-nitride-oxide (ONO) layer that is an information storage element. That is, some of the information storage elements may be included in the vertical structures 230 , and others may be included in the horizontal structures 250 . For example, among the information storage elements, the charge storage layer 225 and the tunnel insulating layer 226 are included in the vertical structures 230 , and the first and second blocking insulating layers 242 and 243 are the horizontal structures 250 . can be included in

Epitaxial patterns 222 may be disposed between the substrate 200 and the vertical structures 230 . The epitaxial patterns 222 connect the substrate 200 and the vertical structures 230 . The epitaxial patterns 222 may contact the horizontal structures 250 of at least one layer. That is, the epitaxial patterns 222 may be disposed to be in contact with the lowermost horizontal structure 250a. According to another embodiment, the epitaxial patterns 222 may be disposed to contact the horizontal structures 250 of a plurality of layers, for example, two layers. Meanwhile, when the epitaxial patterns 222 are disposed to be in contact with the lowermost horizontal structure 250a , the lowermost horizontal structure 250a may be disposed to be thicker than the remaining horizontal structures 250 . The lowermost horizontal structure 250a in contact with the epitaxial patterns 222 may correspond to the ground selection line GSL of the 3D flash memory array described with reference to FIG. 1 , and the vertical structures 230 . The remaining horizontal structures 250 in contact with may correspond to a plurality of word lines WL0-WL3.

Each of the epitaxial patterns 222 has a recessed sidewall 222a. Accordingly, the lowermost horizontal structure 250a in contact with the epitaxial patterns 222 is disposed along the profile of the recessed sidewall 222a. That is, the lowermost horizontal structure 250a may be disposed in a convex shape inward along the recessed sidewalls 222a of the epitaxial patterns 222 .

Conventional three-dimensional flash memory having such a structure has a problem in that leakage current is very large as the channel layer 227 is usually formed of polysilicon. Accordingly, in order to suppress the leakage current, a structure in which the number of string selection lines (SSL) is increased has been proposed.

However, the structure in which the number of SSLs is increased causes a disadvantage that adversely affects the density of memory.

Accordingly, the following embodiments are intended to propose a technique for improving the leakage current characteristics in a 3D flash memory and for achieving memory density and miniaturization.

SUMMARY One embodiment proposes a three-dimensional flash memory that improves leakage current characteristics and promotes memory density and miniaturization.

More specifically, embodiments include a channel layer formed of an oxide semiconductor material to have excellent leakage current characteristics of the oxide semiconductor material, and to improve the physical structure of at least one selection line thanks to the excellent leakage current characteristics of the oxide semiconductor material. By making changes, a three-dimensional flash memory that achieves memory density and miniaturization is proposed.

According to an embodiment, in the 3D flash memory, a string extending in one direction on a substrate, the string extending in the one direction, and charge storage extending in the one direction to surround the channel layer and the channel layer extending in the one direction including layers; at least one selection line vertically connected to an upper end or lower end of the string; and a plurality of word lines vertically connected to the string while being positioned above or below the at least one selection line, wherein the channel layer is formed of an oxide semiconductor material.

According to an aspect, the entire channel layer may be formed of the oxide semiconductor material.

According to another aspect, the physical structure of the at least one selection line may be determined based on a leakage current characteristic of the oxide semiconductor material forming the channel layer.

According to another aspect, the number or thickness of the at least one selection line may be adjusted based on leakage current characteristics of the oxide semiconductor material forming the channel layer.

According to another aspect, the at least one selection line may be formed to have a thickness smaller than a thickness of each of the plurality of word lines.

According to another aspect, the at least one selection line may be implemented as one.

According to another aspect, the oxide semiconductor material may include a material including at least one of In, Zn, and Ga, or a group 4 semiconductor material.

According to another aspect, the at least one selection line may be any one of a string selection line (SSL) and a ground selection line (GSL).

According to an embodiment, in a method of manufacturing a 3D flash memory, a semiconductor in which a plurality of word lines and a plurality of insulating layers are alternately stacked on a substrate, and at least one selection line is stacked on an upper portion or a lower portion thereof preparing the structure; etching holes in one direction on the semiconductor structure; forming a charge storage layer in the hole to extend in the one direction; and forming a channel layer made of an oxide semiconductor material in the inner space of the charge storage layer to extend in the one direction.

According to one aspect, the forming of the channel layer extending in the one direction may include forming the entire channel layer using the oxide semiconductor material.

According to another aspect, the preparing the semiconductor structure includes the semiconductor structure to include the at least one selection line having a physical structure determined based on the leakage current characteristic of the oxide semiconductor material forming the channel layer. It may be characterized in that the preparation step.

According to another aspect, the preparing the semiconductor structure includes the at least one selection line having a number or thickness adjusted based on leakage current characteristics of the oxide semiconductor material forming the channel layer. It may be characterized in that the step of preparing the semiconductor structure.

According to another aspect, the preparing of the semiconductor structure includes preparing the semiconductor structure to include the at least one selection line having a thickness smaller than a thickness of each of the plurality of word lines. can be characterized.

According to another aspect, preparing the semiconductor structure may include preparing the semiconductor structure to include the at least one selection line implemented as one.

According to another aspect, the forming of the channel layer extending in the one direction may include forming the channel layer with the oxide semiconductor material including a material including at least one of In, Zn, or Ga or a group 4 semiconductor material. It may be characterized in that the forming step.

According to another aspect, the at least one selection line may be any one of a string selection line (SSL) and a ground selection line (GSL).

One embodiment may propose a three-dimensional flash memory that improves the leakage current characteristics and promotes memory density and miniaturization.

More specifically, embodiments include a channel layer formed of an oxide semiconductor material to have excellent leakage current characteristics of the oxide semiconductor material, and to improve the physical structure of at least one selection line thanks to the excellent leakage current characteristics of the oxide semiconductor material. By changing it, it is possible to propose a three-dimensional flash memory that achieves memory density and miniaturization.

1 is a simplified circuit diagram illustrating an array of a conventional three-dimensional flash memory.
2 is a perspective view showing the structure of a conventional three-dimensional flash memory.
3 is a view for explaining the leakage current characteristic of the oxide semiconductor material.
4 is a YZ cross-sectional view illustrating a three-dimensional flash memory according to an exemplary embodiment.
5 is a YZ cross-sectional view illustrating a three-dimensional flash memory according to another exemplary embodiment.
6 is a flowchart illustrating a method of manufacturing a 3D flash memory according to an exemplary embodiment.
7A to 7D are YZ cross-sectional views illustrating a method of manufacturing a 3D flash memory according to an exemplary embodiment.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the examples. Also, like reference numerals in each figure denote like members.

In addition, the terms used in this specification are terms used to properly express the preferred embodiment of the present invention, which may vary depending on the intention of a user or operator or customs in the field to which the present invention belongs. Accordingly, definitions of these terms should be made based on the content throughout this specification.

FIG. 3 is a diagram for explaining leakage current characteristics of an oxide semiconductor material, and FIG. 4 is a Y-Z cross-sectional view illustrating a 3D flash memory according to an exemplary embodiment.

The oxide semiconductor material includes a material including at least one of In, Zn, or Ga (eg, a ZnO _x -based material including AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO) or a group 4 semiconductor material. As shown in the graph of FIG. 3 , the oxide semiconductor material has a property that the level of leakage current is significantly lower than that of polysilicon.

Accordingly, the 3D flash memory 400 according to the embodiment described with reference to FIG. 4 is characterized in that it includes a channel layer 410 based on an oxide semiconductor material having superior leakage current characteristics compared to polysilicon.

In more detail, the 3D flash memory 400 includes a string 420 including a channel layer 410 and a charge storage layer 411 , at least one selection line 430 , and a plurality of word lines. 440 may be included. Hereinafter, for convenience of description, the 3D flash memory 400 is illustrated as essentially including a string 420 , at least one selection line 330 , and a plurality of word lines 440 , and a plurality of It is illustrated that a plurality of insulating layers (not shown) interposed between the word lines 40 , a bit line disposed above the string 420 , and a source line disposed below the string 420 are omitted. In addition, the 3D flash memory 400 is illustrated and described as including one string 420 , but is not limited thereto and may include a plurality of strings. In this case, the structure of one string, which will be described later, may be applied to each of the plurality of strings as they are.

The string 420 includes a central channel layer 410 and a charge storage layer 411 extending in one direction (eg, z-direction) on the substrate, and thus each of the plurality of word lines 440 connected in the vertical direction. It is possible to configure memory cells corresponding to .

The charge storage layer 411 is formed to extend to surround the channel layer 410 , and is a component in which charges generated by a voltage applied through the plurality of word lines 440 are stored, and in the three-dimensional flash memory 400 . It serves as a data storage and may be formed of, for example, an oxide-nitride-oxide (ONO) structure or a ferroelectric film such as HfOx.

The channel layer 410 may be formed of an oxide semiconductor material, and may further include a buried layer (not shown) filling the inside. In particular, as the entire channel layer 410, not just a part of the channel layer 410, is formed of an oxide semiconductor material having excellent leakage current characteristics, it blocks and suppresses leakage current through the entire area of the channel layer 410. effect can be expected. Hereinafter, the excellent leakage current characteristic of the oxide semiconductor material means that the oxide semiconductor material has a small leakage current compared to the leakage current characteristic of polysilicon, which is a material constituting the conventional channel layer.

Here, the oxide semiconductor material is a material including at least one of In, Zn, and Ga having excellent leakage current characteristics (eg, a ZnO _x -based material including AZO, ZTO, IZO, ITO, IGZO or Ag-ZnO) or It may include a group 4 semiconductor material.

At least one selection line 430 is at least one string selection line (SSL) vertically connected to the top of the string 420 (at least one string selection line is located on the upper portion of the string 420) At least one ground selection line (GSL) (connected to a bit line (not shown)) or at least one ground selection line (GSL) vertically connected to the lower end of the string 420 (at least one ground selection line is located below the string 420 ) As any one of the source lines (not shown) connected to the above), it may be formed of a conductive material such as W (tungsten), Ti (titanium), Ta (tantalum), Au (copper), or Au (gold). Hereinafter, at least one selection line 430 is illustrated as one string selection line in the drawings, but as described above, it is not limited or limited thereto.

In particular, the physical structure of the at least one selection line 430 may be determined based on leakage current characteristics of the oxide semiconductor material forming the channel layer 410 . For example, the number of the at least one selection line 430 may be adjusted based on excellent leakage current characteristics of the oxide semiconductor material forming the channel layer 410 . As a more specific example, as the oxide semiconductor material forming the channel layer 410 has excellent leakage current characteristics, the 3D flash memory 400 includes one string selection line for each string 420 as shown in the drawing. and may include one ground selection line.

As another example, the thickness of the at least one selection line 430 may be adjusted based on leakage current characteristics of the oxide semiconductor material forming the channel layer 410 . A detailed description thereof will be described with reference to FIG. 5 .

The plurality of word lines 440 are positioned above or below the at least one selection line 430 and are vertically connected to the string 420 , and include W (tungsten), Ti (titanium), Ta (tantalum), and Au. It is formed of a conductive material such as (copper) or Au (gold), and a memory operation (such as a read operation, a program operation, and an erase operation) may be performed by applying a voltage to the corresponding memory cells.

5 is a Y-Z cross-sectional view illustrating a three-dimensional flash memory according to another exemplary embodiment.

Referring to FIG. 5 , the 3D flash memory 500 according to another exemplary embodiment differs from the 3D flash memory 400 described above with reference to FIG. 4 only in the structure of at least one selection line 510 . Since the structures of all other components are the same, only the at least one selection line 510 and the channel layer 520 vertically connected to the at least one selection line 510 will be described below.

In the 3D flash memory 500 according to another embodiment, the channel layer 520 is formed of an oxide semiconductor material having excellent leakage current characteristics. It is characterized in that the thickness of the physical structure of the at least one selection line 510 is adjusted. In more detail, the thickness of the at least one selection line 510 may be adjusted based on a leakage current characteristic of the oxide semiconductor material forming the channel layer 520 , for example, each of the plurality of word lines 530 . The thickness may be adjusted and determined to be thinner than the thickness. However, the present invention is not limited thereto, and the at least one selection line 510 may be formed to have a thinner thickness than the selection line of a conventional 3D flash memory having a polysilicon-based channel layer.

As such, the three-dimensional flash memories 400 and 500 may have excellent leakage current characteristics by forming the channel layers 410 and 520 of the oxide semiconductor material, and at least one selection line may be formed due to the excellent leakage current characteristics of the oxide semiconductor material. By changing the physical structure of 430 and 510, memory density and miniaturization can be achieved. In the above, it has been described that changing the physical structure of the at least one selection line 430 , 510 changes any one of the number or thickness, but it is not limited or limited to changing any one of the number or thickness, and the number and It is also possible to change both thicknesses.

In addition, the 3D flash memories 400 and 500 include the channel layers 410 and 520 formed of an oxide semiconductor material, and thus not only have excellent leakage current characteristics, but also have at least one selection line 430 and 510 . transistor characteristics (threshold voltage distribution of string cells and speed of program/read operations) may be improved.

6 is a flowchart illustrating a method of manufacturing a 3D flash memory according to an exemplary embodiment, and FIGS. 7A to 7D are Y-Z cross-sectional views illustrating a method of manufacturing a 3D flash memory according to an exemplary embodiment. The manufacturing method of the 3D flash memory described below is assuming that it is performed by an automated and mechanized manufacturing system, and refers to a method of manufacturing the 3D flash memory 400 and 500 described above with reference to FIGS. 4 to 5 . .

First, in the manufacturing system, in step S610, a plurality of word lines 711 and a plurality of insulating layers 712 are alternately stacked on a substrate as shown in FIG. 7A, and at least one selection line ( The semiconductor structure 710 in which the selection line 713 is stacked may be prepared.

Here, the at least one selection line 713 in the semiconductor structure 710 is one of at least one String Selection Line (SSL) or at least one Ground Selection Line (GSL), W It may be formed of a conductive material such as (tungsten), Ti (titanium), Ta (tantalum), Au (copper), or Au (gold), and the plurality of word lines 711 in the semiconductor structure 710 are also W It may be formed of a conductive material such as (tungsten), Ti (titanium), Ta (tantalum), Au (copper), or Au (gold). On the other hand, the plurality of insulating layers 712 in the semiconductor structure 710 may be formed of an insulating material.

Hereinafter, the drawings are shown as a case in which at least one selection line 713 is stacked on the top of the semiconductor structure 710 . A three-dimensional flash memory may be manufactured through ( S610 to S640 ).

Subsequently, in operation S620 , the manufacturing system may etch the hole 720 on the semiconductor structure 710 in one direction as shown in FIG. 7B . Here, the hole 720 means a circular trench.

Next, in step S630 , the manufacturing system may extend the charge storage layer 730 in one direction (eg, the z direction) in the hole 720 as shown in FIG. 7C . For example, the manufacturing system may form the charge storage layer 730 on the inner wall of the hole 720 so that the charge storage layer 730 has an internal space 731 .

Thereafter, the manufacturing system extends the channel layer 740 in one direction (eg, the z direction) with an oxide semiconductor material in the internal space 731 of the charge storage layer 730 in a step S640 as shown in FIG. 7D . can be formed In more detail, the manufacturing system fills all of the internal space 731 of the charge storage layer 730 with the oxide semiconductor material, so that the entire channel layer 740 may be formed of the oxide semiconductor material. Here, the oxide semiconductor material may be a material including at least one of In, Zn, or Ga or a material including a group 4 semiconductor material.

As such, since the channel layer 740 is formed of an oxide semiconductor material having excellent leakage current characteristics in step S640 , at least one selection line 713 in the semiconductor structure 710 prepared in step S610 is a channel layer It may have a physical structure determined based on a leakage current characteristic of the oxide semiconductor material from which 740 is to be formed. Specifically, in step S610, the manufacturing system is configured to include at least one selection line 713 having a number or thickness adjusted based on the leakage current characteristic of the oxide semiconductor material that will form the channel layer 740. 710) can be prepared. For example, the manufacturing system prepares the semiconductor structure 710 to include at least one selection line 713 having a thickness smaller than the thickness of each of the plurality of word lines 711 in step S610, or A semiconductor structure 710 including at least one selected line 713 implemented may be prepared.

As described above, although the embodiments have been described with reference to the limited embodiments and drawings, various modifications and variations are possible from the above description by those skilled in the art. For example, the described techniques are performed in an order different from the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (16)

a string extending in one direction on a substrate, the string including a channel layer extending in the one direction and a charge storage layer extending in the one direction to surround the channel layer;
at least one selection line vertically connected to an upper end or a lower end of the string; and
a plurality of word lines positioned above or below the at least one selection line and vertically connected to the string
including,
The channel layer is
Characterized in that it is formed of an oxide semiconductor material,
The at least one selection line is
Based on the leakage current characteristics of the oxide semiconductor material forming the channel layer, characterized in that it is formed to a thickness smaller than the thickness of each of the plurality of word lines,
The number of the at least one selection line is,
3D flash memory, characterized in that the control based on the leakage current characteristics of the oxide semiconductor material forming the channel layer. According to claim 1,
the entire channel layer,
A three-dimensional flash memory formed of the oxide semiconductor material. delete delete delete According to claim 1,
The at least one selection line is
A three-dimensional flash memory, characterized in that it is implemented as one. According to claim 1,
The oxide semiconductor material is
A 3D flash memory comprising a material including at least one of In, Zn, or Ga or a group 4 semiconductor material. According to claim 1,
The at least one selection line is
A three-dimensional flash memory, characterized in that it is either a string selection line (SSL) or a ground selection line (GSL). preparing a semiconductor structure in which a plurality of word lines and a plurality of insulating layers are alternately stacked on a substrate, and at least one selection line is stacked on an upper portion or a lower portion thereof;
etching holes in one direction on the semiconductor structure;
forming a charge storage layer in the hole to extend in the one direction; and
forming a channel layer made of an oxide semiconductor material in the inner space of the charge storage layer to extend in the one direction;
including,
The step of preparing the semiconductor structure,
Based on the leakage current characteristics of the oxide semiconductor material forming the channel layer, preparing the semiconductor structure to include the at least one selection line having a thickness smaller than the thickness of each of the plurality of word lines characterized by,
Preparing the semiconductor structure to include the at least one selection line having a number adjusted based on a leakage current characteristic of the oxide semiconductor material forming the channel layer . 10. The method of claim 9,
The step of extending the channel layer in the one direction comprises:
and forming the entire channel layer using the oxide semiconductor material. delete delete delete 10. The method of claim 9,
The step of preparing the semiconductor structure,
Preparing the semiconductor structure to include the at least one selection line implemented as one
A method of manufacturing a three-dimensional flash memory comprising a. 10. The method of claim 9,
The step of extending the channel layer in the one direction comprises:
and forming the channel layer using a material including at least one of In, Zn, or Ga or the oxide semiconductor material including a group 4 semiconductor material. 10. The method of claim 9,
The at least one selection line is
A method of manufacturing a three-dimensional flash memory, characterized in that it is any one of a string selection line (SSL) and a ground selection line (GSL).

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