KR102394881B1 - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a gate insulating film formed on a substrate, a first barrier film formed on the gate insulating film, an oxide film formed on the first barrier film, a second barrier film formed on the oxide film, and on the second barrier film a gate electrode formed therein, and a source/drain disposed on both sides of the gate electrode in the substrate, wherein the oxide layer includes an oxide formed by oxidizing a material included in the first barrier layer.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for manufacturing the same.

Recently, in order to improve the characteristics of a semiconductor device, a metal gate is often used instead of a polysilicon gate. The metal gate may be fabricated using a replacement metal gate process.

Meanwhile, in order to increase the density of the semiconductor device, the scale of the semiconductor device is gradually decreasing. In a scaled-down semiconductor device, this replacement metal gate process requires multiple etching, deposition, and polishing steps.

The technical problem to be solved by the present invention is to provide a semiconductor device having a structure in which an oxide film is formed between the barrier films to block the physical diffusion path in order to prevent diffusion of impurities through the physical diffusion path of the barrier film.

Another technical problem to be solved by the present invention is to provide a method of manufacturing a semiconductor device having a structure in which an oxide film is formed between the barrier films to block the physical diffusion path in order to prevent diffusion of impurities through the physical diffusion path of the barrier film. will be.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor device according to an embodiment of the present invention for solving the above technical problem includes a gate insulating film formed on a substrate, a first barrier film formed on the gate insulating film, an oxide film formed on the first barrier film, and an oxide film on the oxide film a second barrier layer formed on a second barrier layer, a gate electrode formed on the second barrier layer, and a source/drain disposed on both sides of the gate electrode in the substrate, wherein the oxide layer is a material included in the first barrier layer This includes oxides formed by oxidation.

In some embodiments of the present invention, the first barrier layer may include a conductive material.

In some embodiments of the present invention, the first barrier layer and the second barrier layer may include the same material.

In some embodiments of the present invention, the first barrier layer may include Ti.

In some embodiments of the present invention, the oxide layer may be amorphous.

In some embodiments of the present invention, the thickness of the oxide layer may be 20 Å or less.

In some embodiments of the present invention, the oxide layer may include TiO ₂ .

In some embodiments of the present invention, an interface layer disposed between the substrate and the gate insulating layer may be further included.

A semiconductor device according to another embodiment of the present invention for solving the above technical problem includes a substrate in which a first region and a second region are defined, a first gate insulating layer formed in the first region, and an on the first gate insulating layer A first transistor including a first barrier film formed on the substrate, a first source/drain in the substrate, a second gate insulating film formed in the second region, and a second barrier film formed on the second gate insulating film; a second transistor including an oxide film formed on the second barrier film, a third barrier film formed on the oxide film, a gate electrode formed on the third barrier film, and a second source/drain in the substrate However, the first transistor does not include the gate electrode, the oxide layer includes an oxide formed by oxidizing a material included in the second barrier layer, the first transistor has a first channel length, and the second The transistor has a second channel length different from the first channel length.

In some embodiments of the present invention, the second channel length may be greater than the first channel length.

In some embodiments of the present invention, the first to third barrier layers may include a conductive material.

In some embodiments of the present invention, the first to third barrier layers may include the same material.

In some embodiments of the present invention, the first to third barrier layers may include Ti.

In some embodiments of the present invention, the oxide layer may be amorphous.

In some embodiments of the present invention, the thickness of the oxide layer may be 20 Å or less.

In some embodiments of the present invention, the oxide layer may include TiO ₂ .

In some embodiments of the present invention, a first interface layer disposed between the substrate and the first gate insulating layer and a second interface layer disposed between the substrate and the second gate insulating layer may be further included.

A semiconductor device according to another embodiment of the present invention for solving the above technical problem includes an active fin that extends on a substrate in a first direction and protrudes from the substrate, and crosses the first direction on the active fin a gate insulating film extending in a second direction, a first barrier film formed on the gate insulating film, an oxide film formed on the first barrier film, a second barrier film formed on the oxide film, and a second barrier film formed on the second barrier film a gate electrode and a source/drain disposed on both sides of the gate electrode in the active fin, wherein the oxide layer includes an oxide formed by oxidizing a material included in the first barrier layer.

In some embodiments of the present invention, the first and second barrier layers may include a conductive material.

In some embodiments of the present invention, the first barrier layer and the second barrier layer may include the same material.

In some embodiments of the present invention, the first and second barrier layers may include Ti.

In some embodiments of the present invention, the oxide layer may be amorphous.

In some embodiments of the present invention, the thickness of the oxide layer may be 20 Å or less.

In some embodiments of the present invention, the oxide layer may include TiO ₂ .

In a method for manufacturing a semiconductor device according to an embodiment of the present invention for solving the above technical problem, an interlayer insulating film including a trench is formed on a substrate, a gate insulating film is formed on an inner surface of the trench, and the A first barrier film is formed on the gate insulating film, and the first barrier film is exposed to an oxygen environment to form an oxide film on the first barrier film, and a first barrier film containing the same material as the first barrier film on the oxide film and forming a second barrier layer and forming a gate electrode on the second barrier layer.

In some embodiments of the present invention, an in-situ process may be used to form the first barrier layer, the oxide layer, and the second barrier layer.

In some embodiments of the present invention, the thickness of the oxide layer may be 20 Å or less.

In some embodiments of the present invention, the first and second barrier layers may include a conductive material.

In some embodiments of the present invention, the first and second barrier layers may include Ti.

In some embodiments of the present invention, before forming the gate insulating layer, the method may further include forming an interface layer on the bottom surface of the trench.

The details of other embodiments are included in the detailed description and drawings.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
2 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention.
3 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention.
4 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.
5 is a perspective view of a semiconductor device according to a fifth embodiment of the present invention.
6 is a cross-sectional view taken along line AA of FIG. 5 .
7 is a cross-sectional view taken along line BB of FIG. 5 .
8 is a perspective view of a semiconductor device according to a sixth embodiment of the present invention.
9 is a cross-sectional view taken along lines C1-C1 and C2-C2 of FIG. 8 .
10 is a cross-sectional view taken along lines D1-D1 and D2-D2 of FIG. 8 .
11 to 13 are circuit diagrams and layout diagrams for explaining a semiconductor device according to a seventh embodiment of the present invention.
14 is a flowchart sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
15 to 20 are intermediate steps for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
21 is a flowchart sequentially illustrating a method of manufacturing a semiconductor device according to another exemplary embodiment of the present invention.
22 is an intermediate step view for explaining a method of manufacturing a semiconductor device according to another embodiment of the present invention.
23 is a schematic block diagram illustrating an electronic system including a semiconductor device according to some embodiments of the present invention.
24 is a schematic block diagram for explaining an application example of an electronic system including a semiconductor device according to some embodiments of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

When one component is referred to as “connected to” or “coupled to” with another component, it means that it is directly connected or coupled to another component or intervening another component. including all cases. On the other hand, when one component is referred to as “directly connected to” or “directly coupled to” with another component, it indicates that another component is not interposed therebetween. “and/or” includes each and every combination of one or more of the recited items.

When a component is referred to as “on” or “on” another component, it includes all cases in which other components are interposed in the middle as well as directly above the other components. On the other hand, when a component is referred to as “directly on” or “directly above” another component, it indicates that other components are not interposed therebetween.

Spatially relative terms "below", "beneath", "lower", "above", "upper", etc. It can be used to easily describe the correlation between components and other components. The spatially relative terms should be understood as terms including different orientations of the device during use or operation in addition to the orientation shown in the drawings. For example, when an element shown in the drawings is turned over, a component described as "beneath" or "beneath" of another element may be placed "above" the other element. . Accordingly, the exemplary term “below” may include both directions below and above. Components may also be oriented in other orientations, and thus spatially relative terms may be interpreted according to orientation.

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, "comprises" and/or "comprising" refers to the presence of one or more other components, steps, operations and/or elements mentioned. or addition is not excluded.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms, of course. These terms are only used to distinguish one component from another. Accordingly, it goes without saying that the first component mentioned below may be the second component within the spirit of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used with the meaning commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in a commonly used dictionary are not to be interpreted ideally or excessively unless clearly defined in particular.

Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 1 , a semiconductor device 1 according to a first embodiment of the present invention includes a substrate 100 , a first gate insulating layer 130 , a first barrier layer 141 , a first oxide layer 143 , It may include a second barrier layer 142 , a first gate electrode 150 , a first gate spacer 160 , a first source/drain region 170 , and the like.

The substrate 100 is a rigid substrate such as a silicon substrate, a silicon on insulator (SOI) substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, or a glass substrate for display, or polyimide, polyester ) may be a flexible plastic substrate such as polycarbonate, polyethersulfone, polymethylmethacrylate, polyethylene naphthalate, or polyethyleneterephthalate. In addition, the substrate 100 may be, for example, a first conductivity type (P type), but is not limited thereto.

The first gate insulating layer 130 may be formed on the substrate 100 and include a material having a high dielectric constant (high-k). The first gate insulating layer 130 may include, for example, any one selected from the group consisting of HfSiON, HfO ₂ , ZrO ₂ , Ta ₂ O ₅ , TiO ₂ , SrTiO ₃ , BaTiO ₃ , and SrTiO ₃ . can The first gate insulating layer 130 may be conformally formed along sidewalls of the first gate spacer 160 .

Meanwhile, the first gate insulating layer 130 may be formed to have an appropriate thickness according to the type of device to be formed. For example, when the first gate insulating layer 130 is made of HfO ₂ , the gate insulating layer 130 may be formed to a thickness of about 50 Å or less (about 5 Å to 50 Å), but is not limited thereto.

The first barrier layer 141 is formed on the first gate insulating layer 130 . The first barrier layer 141 may include a conductive material, for example, a TiN layer. The first barrier layer 141 may be formed to have an appropriate thickness according to the type of device to be formed. The first barrier layer 141 may be formed to a thickness of, for example, about 5 to 25 Å.

The first barrier layer 141 and the second barrier layer 142 to be described later may serve as an adhesion layer between the first gate electrode 150 and the first gate insulating layer 130 . The first barrier layer 141 may be conformally formed along sidewalls of the first gate spacer 160 using, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD).

The first oxide layer 143 may be formed on the first barrier layer 141 . In particular, the first oxide layer 143 is formed between the first barrier layer 141 and the second barrier layer 142 , and fluorine (F) generated from tungsten hexafluoride (WF6) included in the first gate electrode 150 . ) may serve to prevent ions from penetrating toward the first gate insulating layer 130 .

In some embodiments of the present invention, the first oxide layer 143 may be formed using a natural oxidation phenomenon by exposing the first barrier layer 141 to an oxygen environment. The first barrier layer 141 and the second barrier layer 142 to be described later may be formed in a crystalline state, and accordingly, the first barrier layer 141 and the second barrier layer 142 are protected against fluorine (F) ions. It can provide a physical path for movement. A first oxide layer 143 is formed to block diffusion of such fluorine (F) ions. In order to block the path through which fluorine (F) ions diffuse, the entire first barrier layer 141 and the second barrier layer 142 may be converted into an amorphous state. 2 A heterogeneous material having a high crystallization temperature must be doped into the barrier layer 142 . This causes an increase in the resistivity of the entire first barrier layer 141 and the second barrier layer 142 , thereby reducing reliability of the semiconductor device.

In addition, in order to block a path through which fluorine (F) ions are diffused, the first barrier film 141 and the second barrier film 142 are formed between the first barrier film 141 and the second barrier film 142 . A dissimilar material may be deposited, but this may cause an increase in wiring resistance. Therefore, in the present invention, the first oxide film 143, which is a natural oxide film, between the first barrier film 141 and the second barrier film 142 so as to block the path through which fluorine (F) ions are diffused without an additional process and increase in specific resistance. to form

Here, the first oxide layer 143 may include an oxide (eg, TiO ₂ ) of a material (eg, Ti) included in the first barrier layer 141 , and the first oxide layer 143 . The thickness of may be formed to be, for example, 20 Å or less. The first oxide layer 143 may be formed in an amorphous state so as to block a path through which fluorine (F) ions are diffused.

The second barrier layer 142 is formed on the first oxide layer 143 . The second barrier layer 142 may include the same material as the first barrier layer 141 . The second barrier layer 142 may include a conductive material, for example, a TiN layer. The second barrier layer 142 may be formed to have an appropriate thickness according to the type of device to be formed. The second barrier layer 142 may be formed to a thickness of, for example, about 5 to about 25 Å.

The first barrier layer 141 and the second barrier layer 142 may serve as an adhesion layer between the first gate electrode 150 and the first gate insulating layer 130 . The second barrier layer 142 may be conformally formed along the sidewall of the first gate spacer 160 using, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD).

The first barrier layer 141 , the first oxide layer 143 , and the second barrier layer 142 may be formed using an ex-situ process. That is, in the process of forming the first barrier film 141 and the second barrier film 142 , the first barrier film 141 is exposed to an oxygen environment, and the first oxide film ( 143 ), and then the second barrier layer 142 may be formed. That is, the first oxide layer 143 may be formed using a natural oxidation phenomenon.

Also, the first barrier layer 141 , the first oxide layer 143 , and the second barrier layer 142 may be formed using an in-situ process. In the process of forming the first barrier layer 141 and the second barrier layer 142 , oxygen atoms may be injected to deposit the first oxide layer 143 on the first barrier layer 141 .

The first gate electrode 150 is formed on the second barrier layer 142 . The first gate electrode 150 may include a conductive material, for example, tungsten (W) or aluminum (Al), but is not limited thereto.

The first gate spacer 160 may be formed on side surfaces of the first gate insulating layer 130 and the first barrier layer 141 . The first gate spacer 160 may include, for example, any one of SiN and SiON.

The first source/drain regions 170 may be disposed on both sides of the first gate electrode 150 in the substrate 100 . The first source/drain region 170 may be an n-type source/drain doped with an n-type impurity. The first source/drain region 170 may have a low doped drain (LDD) shape, but is not limited thereto. The shape of the first source/drain region 170 may vary depending on the type of device to be formed.

Hereinafter, semiconductor devices according to other embodiments of the present invention will be described.

2 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. For convenience of description, descriptions of parts substantially identical to those of the semiconductor device according to the first embodiment of the present invention will be omitted.

Referring to FIG. 2 , the semiconductor device 2 according to the second embodiment of the present invention includes substrates 100 and 200 , a first gate insulating layer 130 , a first barrier layer 141 , and a first gate spacer ( 160 ), first source/drain region 170 , second gate insulating layer 230 , third barrier layer 241 , second oxide layer 243 , fourth barrier layer 242 , and second gate electrode 250 . ), a second gate spacer 260 , a second source/drain region 270 , and the like.

The substrates 100 and 200 may include a first region (I) and a second region (II). The first region (I) and the second region (II) may be divided by, for example, a field insulating layer such as shallow trench isolation (STI). Here, the first region I is a region in which the channel length of the first transistor TR1 is a first length W1, and the second region II is a region in which the channel length of the second transistor TR2 is a second length. (W2) may be a region. Here, the first length W1 and the second length W2 are different from each other, and for example, the second length W2 may be greater than the first length W1 . Here, the channel length is defined as a distance between adjacent sources/drains of the first transistor TR1 and the second transistor TR2 .

The substrate 100 is defined as a first region (I), and the substrate 200 is defined as a second region (II). In general, a semiconductor device may be manufactured to have a short channel and a long channel according to characteristics of the semiconductor device, wherein the first region (I) is a short channel region, and the second region (II) ) denotes a long channel region. In this case, a gate electrode may not be formed in the first transistor TR1 formed in the first region I, unlike the second transistor TR2 formed in the second region II. Since the first barrier layer 141 includes a conductive material, the first transistor TR1 formed in the first region I may operate as a transistor even without a gate electrode. The oxide film, which is a characteristic of the present invention, may be formed in the second transistor TR2 formed in the second region II. That is, the second oxide layer 243 prevents fluorine (F) ions generated from tungsten hexafluoride (WF6) included in the second gate electrode 250 from penetrating toward the second gate insulating layer 230 . there is.

The first transistor TR1 may include a substrate 100 , a first gate insulating layer 130 , a first barrier layer 141 , a first gate spacer 160 , a first source/drain region 170 , and the like. and is substantially the same as described above. However, the thickness of the first barrier layer 141 may be thicker than the thickness of the third barrier layer 241 . The first barrier layer 141 may fill a space defined by the first gate insulating layer 130 . In some embodiments of the present invention, the first barrier layer 141 may have an overall flat top surface.

The second transistor TR2 includes the substrate 200 , the second gate insulating layer 230 , the third barrier layer 241 , the second oxide layer 243 , the fourth barrier layer 242 , and the second gate electrode 250 . , a second gate spacer 260 , and a second source/drain region 270 . The third barrier layer 241 , the second oxide layer 243 , and the fourth barrier layer 242 may each have a concave shape.

The substrate 200 , the second gate insulating layer 230 , the third barrier layer 241 , the second oxide layer 243 , the fourth barrier layer 242 , the second gate electrode 250 , and the second gate spacer 260 . ) and the second source/drain regions 270 are the above-described substrate 100 , the first gate insulating layer 130 , the first barrier layer 141 , the first oxide layer 143 , and the second barrier layer 142 , respectively. ), the first gate electrode 150 , the first gate spacer 160 , and the first source/drain region 170 are substantially the same.

3 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention. For convenience of description, descriptions of parts substantially identical to those of the semiconductor device according to the first embodiment of the present invention will be omitted.

Referring to FIG. 3 , the semiconductor device 3 according to the third embodiment of the present invention includes a substrate 100 , a first interface layer 120 , a first gate insulating layer 130 , and a first barrier layer 141 . , a first oxide layer 143 , a second barrier layer 142 , a first gate electrode 150 , a first gate spacer 160 , a first source/drain region 170 , and the like.

Substrate 100 , first gate insulating layer 130 , first barrier layer 141 , first oxide layer 143 , second barrier layer 142 , first gate electrode 150 , first gate spacer 160 . ), the first source/drain region 170 is substantially the same as described above.

The first interface layer 120 is formed on the substrate 100 , and may be formed between the substrate 100 and the first gate insulating layer 130 .

The first interface layer 120 may serve to prevent a defective interface between the substrate 100 and the first gate insulating layer 130 . The first interface layer 120 is a low-k material layer having a dielectric constant k of 9 or less, for example, a silicon oxide layer (k is about 4) or a silicon oxynitride layer (k is about 4-8 depending on the content of oxygen atoms and nitrogen atoms). ) may be included. Alternatively, the first interface layer 120 may be formed of silicate or a combination of the above-described layers.

4 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention. For convenience of description, descriptions of parts substantially the same as those of the semiconductor devices according to the first to third embodiments of the present invention will be omitted.

Referring to FIG. 4 , a semiconductor device 4 according to a fourth embodiment of the present invention includes substrates 100 and 200 , a first interface layer 120 , a first gate insulating layer 130 , and a first barrier layer ( 141 ), the first gate spacer 160 , the first source/drain regions 170 , the second interface layer 220 , the second gate insulating layer 230 , the third barrier layer 241 , and the second oxide layer 243 . ), a fourth barrier layer 242 , a second gate electrode 250 , a second gate spacer 260 , and a second source/drain region 270 .

The second interface layer 220 is substantially the same as the first interface layer 120 described above, and the remaining components of the semiconductor device 4 are also substantially the same as those described above, respectively.

Hereinafter, as a semiconductor device according to other embodiments of the present invention, a fin-type semiconductor device will be described.

5 is a perspective view of a semiconductor device according to a fifth embodiment of the present invention. 6 is a cross-sectional view taken along line A-A of FIG. 5 . 7 is a cross-sectional view taken along line B-B of FIG. 5 .

5 to 7 , the semiconductor device 5 according to the fifth embodiment of the present invention includes a substrate 300 , a first field insulating layer 310 , an active fin F, and a third gate insulating layer 330 . ), a fifth barrier film 341 , a third oxide film 343 , a sixth barrier film 342 , a third gate electrode 350 , a third gate spacer 360 , and a third source/drain region 410 . , the first interlayer insulating film 500 , and the like.

The substrate 300 may be a rigid substrate such as a silicon substrate, a silicon on insulator (SOI) substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, or a glass substrate for display, or polyimide, polyester. ) may be a flexible plastic substrate such as polycarbonate, polyethersulfone, polymethylmethacrylate, polyethylene naphthalate, or polyethyleneterephthalate.

The first field insulating layer 310 is formed on the substrate 300 and is used for device isolation. The first field insulating layer 310 is an insulating layer, and may be an HDP oxide layer, an SOG oxide layer, a CVD oxide layer, or the like, but is not limited thereto.

The active fin F is formed on the substrate 300 . In particular, the active fin F may be formed to protrude from the substrate 300 . In particular, the active fin F may be formed to protrude from the substrate 300 in the third direction Z. The active fin F may be a part of the substrate 300 or may include an epitaxial layer grown from the substrate 300 . The active fin F may extend long in the first direction X. The field insulating layer 310 may cover an upper surface of the substrate 300 and a portion of a side surface of the active fin F.

The first gate structure GS1 may be formed on the active fin F in a direction crossing the active fin F. The first gate structure GS1 may extend long in the second direction Y.

The first gate structure GS1 includes a third gate insulating layer 330 , a fifth barrier layer 341 , a third oxide layer 343 , a sixth barrier layer 342 , and a third gate insulating layer 330 sequentially formed on the active fin F . It may include a third gate electrode 350 , a third gate insulating layer 330 , and a third gate spacer 360 formed on side surfaces of the fifth barrier layer 341 , and the like. Due to this structure, channels may be formed on both sides and top surfaces of the active fin F.

The third gate insulating layer 330 may be formed on the active fin F. However, an interface layer may be further formed between the third gate insulating layer 330 and the active fin F. The third gate insulating layer 330 may be conformally formed along sidewalls of the third gate spacer 360 . For example, the third gate insulating layer 330 may be disposed between the fifth barrier layer 341 and the third gate spacer 360 .

The third gate insulating layer 330 may include a material having a high dielectric constant (high-k). Specifically, the third gate insulating layer 330 may be, for example, any one selected from the group consisting of HfSiON, HfO ₂ , ZrO ₂ , Ta ₂ O ₅ , TiO ₂ , SrTiO ₃ , BaTiO ₃ , and SrTiO ₃ . may include.

Meanwhile, the third gate insulating layer 330 may be formed to have an appropriate thickness according to the type of device to be formed. For example, when the third gate insulating layer 330 is made of HfO ₂ , the third gate insulating layer 330 may be formed to a thickness of about 50 Å or less (about 5 Å to 50 Å), but is not limited thereto.

The fifth barrier layer 341 may be formed on the third gate insulating layer 330 . The fifth barrier layer 341 may be formed in contact with the third gate insulating layer 330 . According to some embodiments of the present disclosure, as shown in FIG. 5 , the fifth barrier layer 341 may extend upward along the sidewall of the third gate spacer 360 , which will be described later.

The fifth barrier layer 341 may include a conductive material, for example, a TiN layer. The fifth barrier layer 341 may be formed to have an appropriate thickness according to the type of device to be formed. The fifth barrier layer 341 may be formed to a thickness of, for example, about 5 to about 25 Å.

The fifth barrier layer 341 and the sixth barrier layer 342 to be described later may serve as an adhesion layer between the third gate electrode 350 and the third gate insulating layer 330 . The fifth barrier layer 341 may be conformally formed along the sidewall of the third gate spacer 360 using, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD).

The third oxide layer 343 may be formed on the fifth barrier layer 341 . In particular, the third oxide film 343 is formed between the fifth barrier film 341 and the sixth barrier film 342 , and fluorine (F) generated from tungsten hexafluoride (WF6) included in the third gate electrode 350 . ) may serve to prevent ions from penetrating toward the third gate insulating layer 130 .

In some embodiments of the present invention, the third oxide layer 343 may be formed using a natural oxidation phenomenon by exposing the fifth barrier layer 341 to an oxygen environment. The fifth barrier film 341 and the sixth barrier film 342 to be described later may be formed in a crystalline state, and accordingly, the fifth barrier film 341 and the sixth barrier film 342 are protected against fluorine (F) ions. It can provide a physical path for movement. A third oxide layer 343 is formed to block diffusion of such fluorine (F) ions.

Here, the third oxide layer 343 may include an oxide (eg, TiO ₂ ) of a material (eg, Ti) included in the fifth barrier layer 341 , and the third oxide layer 343 . The thickness of may be formed to be, for example, 20 Å or less. The third oxide layer 343 may be formed in an amorphous state to block a path through which fluorine (F) ions are diffused.

The sixth barrier layer 342 is formed on the third oxide layer 343 . The sixth barrier layer 342 may include the same material as the fifth barrier layer 341 . The sixth barrier layer 342 may include a conductive material, for example, a TiN layer. The sixth barrier layer 342 may be formed to have an appropriate thickness according to the type of device to be formed. The sixth barrier layer 342 may be formed to a thickness of, for example, about 5 to 25 Å.

The fifth barrier layer 341 and the sixth barrier layer 342 may serve as an adhesion layer between the third gate electrode 350 and the third gate insulating layer 330 . The sixth barrier layer 342 may be conformally formed along the sidewall of the third gate spacer 360 using, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD).

The third gate electrode 350 is formed on the sixth barrier layer 342 . The third gate electrode 350 may include a conductive material, for example, tungsten (W) or aluminum (Al), but is not limited thereto.

The third gate spacer 360 may be formed on at least one side of the side surfaces of the first gate structure GS1 . The third gate spacer 360 may include at least one of a nitride layer, an oxynitride layer, and a low-k material.

In addition, although one side of the third gate spacer 360 is shown as a curved line, the present invention is not limited thereto, and the shape of the third gate spacer 360 may be different from this. For example, the third gate spacer 360 may have an I-shape or an L-shape, different from that illustrated.

In addition, although it is illustrated that the third gate spacer 360 is formed of a single layer in the drawings, the present invention is not limited thereto, and may be formed of a plurality of layers.

Meanwhile, the third source/drain region 410 may be formed on at least one side of both sides of the first gate structure GS1 and may be formed in the active fin F. The third source/drain region 410 and the first gate structure GS1 may be insulated by the third gate spacer 360 .

When the semiconductor device 5 is an NMOS transistor, the third source/drain region 410 may include the same material as the substrate 300 or a tensile stress material. For example, when the substrate 300 is made of Si, the source/drain regions may be Si or a material having a lattice constant smaller than that of Si (eg, SiC or SiP). The tensile stress material may apply tensile stress to the active fin F under the first gate structure GS1 , that is, the channel region to improve carrier mobility in the channel region.

Meanwhile, when the semiconductor device 5 is a PMOS transistor, the third source/drain region 410 may include a compressive stress material. For example, the compressive stress material may be a material having a lattice constant greater than that of Si, for example, SiGe. The compressive stress material may improve carrier mobility in the channel region by applying compressive stress to the active fin F under the first gate structure GS1 , that is, the channel region.

In some embodiments of the present invention, the third source/drain region 410 may be formed through epitaxial growth, but the present invention is not limited thereto.

The first interlayer insulating layer 500 may include, for example, at least one of a low-k material, an oxide layer, a nitride layer, and an oxynitride layer. The low dielectric constant material is, for example, Flowable Oxide (FOX), Tonen SilaZen (TOSZ), Undoped Silica Glass (USG), Borosilica Glass (BSG), PhosphoSilaca Glass (PSG), BoroPhosphoSilica Glass (BPSG), Plasma Enhanced Tetra (PRTEOS). Ethyl Ortho Silicate), Fluoride Silicate Glass (FSG), High Density Plasma (HDP), Plasma Enhanced Oxide (PEOX), Flowable CVD (FCVD), or a combination thereof, but is not limited thereto.

8 is a perspective view of a semiconductor device according to a sixth embodiment of the present invention. 9 is a cross-sectional view taken along lines C1-C1 and C2-C2 of FIG. 8 . FIG. 10 is a cross-sectional view taken along lines D1-D1 and D2-D2 of FIG. 8 . For convenience of description, descriptions of parts substantially the same as those of the semiconductor device according to the fifth embodiment of the present invention will be omitted.

8 to 10 , a semiconductor device 6 according to a sixth embodiment of the present invention includes substrates 300 and 300 ′, a first field insulating layer 310 , a first active fin F1 , and a first 3 gate insulating layer 330 , fifth barrier layer 341 , third gate spacer 360 , third source/drain region 410 , first interlayer insulating layer 500 , second field insulating layer 310 ′; The second active fin F2, the fourth gate insulating film 330', the seventh barrier film 341', the fourth oxide film 343', the eighth barrier film 342', the fourth gate electrode 350' ), a fourth gate spacer 360 ′, a fourth source/drain region 410 ′, a second interlayer insulating layer 500 ′, and the like.

In the semiconductor device 6 , the substrates 300 and 300 ′ may include a first region (I) and a second region (II). The first region (I) and the second region (II) may be divided by, for example, a field insulating layer such as shallow trench isolation (STI). Here, the first region (I) is a region in which the channel length of the first transistor TR1 including the first gate structure GS1 is the third length W3, and the second region (II) is the second gate The channel length of the second transistor TR2 including the structure GS2 may be the fourth length W4 . Here, the third length W3 and the fourth length W4 are different from each other, and for example, the fourth length W4 may be greater than the third length W3 . Here, the channel length is defined as a distance between adjacent sources/drains of the first transistor TR1 and the second transistor TR2 .

Substrate 300 , first field insulating layer 310 , first active fin F1 , third gate insulating layer 330 , fifth barrier layer 341 , third gate spacer 360 , third source/drain Each of the region 410 and the first interlayer insulating layer 500 is substantially the same as the above-described components. However, the thickness of the fifth barrier layer 341 may be thicker than the thickness of the seventh barrier layer 341 ′. The fifth barrier layer 341 may fill a space defined by the third gate insulating layer 330 . The fifth barrier layer 341 may have a flat top surface.

In addition, the substrate 300', the second field insulating layer 310', the second active fin F2, the fourth gate insulating layer 330', the seventh barrier layer 341', and the fourth oxide layer 343'. , the eighth barrier film 342', the fourth gate electrode 350', the fourth gate spacer 360', the fourth source/drain region 410', and the second interlayer insulating film 500' are each, The above-described substrate 300 , the first field insulating layer 310 , the active fin F, the third gate insulating layer 330 , the fifth barrier layer 341 , the third oxide layer 343 , and the sixth barrier layer 342 . ), the third gate electrode 350 , the third gate spacer 360 , the third source/drain region 410 , and the first interlayer insulating layer 500 are substantially the same. In some embodiments of the present invention, each of the seventh barrier layer 341 ′, the fourth oxide layer 343 ′, and the eighth barrier layer 342 ′ may have a concave shape.

11 to 13 are circuit diagrams and layout diagrams for explaining a semiconductor device according to a seventh embodiment of the present invention.

13 illustrates only a plurality of fins and a plurality of gate structures in the layout diagram of FIG. 12 . Although the above-described semiconductor device according to some embodiments of the present invention is applicable to all devices including general logic devices using pin-type transistors, FIGS. 11 to 13 show SRAMs by way of example.

First, referring to FIG. 11 , a semiconductor device according to a seventh embodiment of the present invention includes a pair of inverters INV1 and INV2 connected in parallel between a power node Vcc and a ground node Vss, respectively. may include a first pass transistor PS1 and a second pass transistor PS2 connected to output nodes of the inverters INV1 and INV2.

The first pass transistor PS1 and the second pass transistor PS2 may be respectively connected to the bit line BL and the complementary bit line /BL. Gates of the first pass transistor PS1 and the second pass transistor PS2 may be connected to the word line WL.

The first inverter INV1 includes a first pull-up transistor PU1 and a first pull-down transistor PD1 connected in series, and the second inverter INV2 includes a second pull-up transistor PU2 and a second pull-down transistor connected in series. and a transistor PD2.

The first pull-up transistor PU1 and the second pull-up transistor PU2 may be PMOS transistors, and the first pull-down transistor PD1 and the second pull-down transistor PD2 may be NMOS transistors.

In addition, the input node of the first inverter INV1 is connected to the output node of the second inverter INV2 so that the first inverter INV1 and the second inverter INV2 constitute one latch circuit. and an input node of the second inverter INV2 may be connected to an output node of the first inverter INV1 .

Here, referring to FIGS. 11 to 13 , the first active fin F1 , the second active fin F2 , the third active fin F3 , and the fourth active fin F4 spaced apart from each other in one direction (eg, For example, it is formed to extend long in the vertical direction of FIG. 12 ).

In addition, the first gate structure 351 , the second gate structure 352 , the third gate structure 353 , and the fourth gate structure 354 extend long in the other direction (eg, the left-right direction in FIG. 12 ). and is formed in a direction crossing the first active fins F1 to F4.

Specifically, the first gate structure 351 may be formed to completely cross the first active fin F1 and the second active fin F2 and overlap a portion of an end of the third active fin F3 . The third gate structure 353 may be formed to completely cross the fourth active fin F4 and the third active fin F3 and overlap a portion of an end of the second active fin F2 . The second gate structure 352 and the fourth gate structure 354 may be formed to cross the first active fin F1 and the fourth active fin F4, respectively.

12 , the first pull-up transistor PU1 is defined around a region where the first gate structure 351 and the second active fin F2 intersect, and the first pull-down transistor PD1 is the first It is defined around a region where the gate structure 351 and the first active fin F1 intersect, and the first pass transistor PS1 is formed around a region where the second gate structure 352 and the first active fin F1 intersect. is defined in

The second pull-up transistor PU2 is defined around a region where the third gate structure 353 and the third active fin F3 intersect, and the second pull-down transistor PD2 includes the third gate structure 353 and the fourth gate structure 353 . The active fin F4 is defined around the intersecting region, and the second pass transistor PS2 is defined around the intersecting region of the fourth gate structure 354 and the fourth active fin F4 .

Although not clearly shown, recesses are formed on both sides of a region where the first to fourth gate structures 351 to 354 and the first to fourth active fins F1 to F4 intersect, and the source/ A drain region may be formed, and a plurality of contacts 361 may be formed.

In addition, the shared contact 362 simultaneously connects the second active fin F2 , the third gate structure 353 and the wiring 371 . The shared contact 363 simultaneously connects the third active fin F3 , the first gate structure 351 , and the wiring 372 .

Examples of the first pull-up transistor PU1 , the first pull-down transistor PD1 , the first pass transistor PS1 , the second pull-up transistor PU2 , the second pull-down transistor PD2 , and the second pass transistor PS2 include For example, the semiconductor device according to the embodiments of the present invention described above may be employed.

Hereinafter, a method of manufacturing a semiconductor device according to some embodiments of the present invention will be described.

14 is a flowchart sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. 15 to 20 are intermediate steps for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

14 to 20 , in the method of manufacturing a semiconductor device according to an embodiment of the present invention, first, an interlayer insulating layer pattern IL including a trench is formed on a substrate 100 ( S100 ).

Specifically, after forming the dummy gate pattern DG, the dummy spacer pattern DS, and the interlayer insulating layer pattern IL on the substrate 100 , the dummy gate pattern DG is removed to form a trench. Before forming the interlayer insulating layer pattern IL, the first source/drain regions 170 may be formed in the substrate 100 using the dummy gate pattern DG and the dummy spacer pattern DS as masks.

Next, a first gate insulating layer 130 is formed on the bottom surface of the trench ( S110 ). Then, a first barrier layer 141 is formed on the first gate insulating layer 130 ( S120 ). The first barrier layer 141 may be conformally formed along the sidewall of the dummy spacer pattern DS. The first barrier layer 141 may include a conductive material, for example, a TiN layer. The first barrier layer 141 may be formed to have an appropriate thickness according to the type of device to be formed. The first barrier layer 141 may be formed to a thickness of, for example, about 5 to 25 Å.

Next, the first barrier layer 141 is exposed to an oxygen environment to form a first oxide layer 143 on the first barrier layer 141 ( S130 ). Here, the first oxide layer 143 may include an oxide (eg, TiO ₂ ) of a material (eg, Ti) included in the first barrier layer 141 , and the first oxide layer 143 . The thickness of may be formed to be, for example, 20 Å or less. The first oxide layer 143 may be formed in an amorphous state so as to block a path through which fluorine (F) ions are diffused.

Next, a second barrier layer 142 is formed on the first oxide layer 143 ( S140 ). Here, the second barrier layer 142 may include the same material as the first barrier layer 141 . The second barrier layer 142 may include a conductive material, for example, a TiN layer. The second barrier layer 142 may be formed to have an appropriate thickness according to the type of device to be formed. The second barrier layer 142 may be formed to a thickness of, for example, about 5 to about 25 Å.

Next, the first gate electrode 150 is formed on the second barrier layer 142 ( S150 ). The first gate electrode 150 may include a conductive material, for example, tungsten (W) or aluminum (Al).

Next, the semiconductor device of FIG. 17 is manufactured using a planarization process and an etching process.

21 is a flowchart sequentially illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention. 22 is an intermediate step view for explaining a method of manufacturing a semiconductor device according to another embodiment of the present invention. For convenience of description, descriptions of parts substantially the same as those described in the method of manufacturing a semiconductor device according to an exemplary embodiment will be omitted.

21 and 22 , in the method of manufacturing a semiconductor device according to another embodiment of the present invention, before forming the first gate insulating layer 130 , the first interface layer 120 may be further formed ( S105).

The first interface layer 120 is formed on the substrate 100 , and may be formed between the substrate 100 and the first gate insulating layer 130 .

The first interface layer 120 may serve to prevent a defective interface between the substrate 100 and the first gate insulating layer 130 . The first interface layer 120 is a low-k material layer having a dielectric constant k of 9 or less, for example, a silicon oxide layer (k is about 4) or a silicon oxynitride layer (k is about 4-8 depending on the content of oxygen atoms and nitrogen atoms). ) may be included. Alternatively, the first interface layer 120 may be formed of silicate or a combination of the above-described layers.

Hereinafter, an electronic system including a semiconductor device according to some embodiments of the present invention will be described. 23 is a schematic block diagram illustrating an electronic system including a semiconductor device according to some embodiments of the present invention.

Referring to FIG. 23 , the electronic system includes a control device 510 (CONTROLLER), an interface 520 (INTERFACE), an input/output device 530 (I/O), a memory device 540 MEMORY, and a power supply device 550 POWER SUPPLY. ), and a bus 560 (BUS).

The control device 510 , the interface 520 , the input/output device 530 , the memory device 540 , and the power supply device 550 may be coupled to each other through the bus 560 . The bus 560 corresponds to a path through which data is moved.

The control device 510 may process data by including at least one of a microprocessor, a microcontroller, and logic elements capable of performing functions similar thereto.

The interface 520 may perform a function of transmitting data to or receiving data from a communication network. The interface 520 may be in a wired or wireless form. For example, the interface 520 may include an antenna or a wired/wireless transceiver.

The input/output device 530 may input/output data including a keypad and a display device.

The storage device 540 may store data and/or instructions. The semiconductor device according to some embodiments of the present invention may be provided as some components of the memory device 540 .

The power supply 550 may convert externally input power and provide it to each of the components 510 to 540 .

24 is a schematic block diagram for explaining an application example of an electronic system including a semiconductor device according to some embodiments of the present invention.

Referring to FIG. 24 , the electronic system includes a central processing unit 610 (CPU), an interface 620; INTERFACE, a peripheral device 630; PERIPHERAL DEVICE), a main memory device 640; SECONDARY MEMORY) and a bus 660 (BUS).

The central processing unit 610 , the interface 620 , the peripheral unit 630 , the main memory unit 640 , and the auxiliary memory unit 650 may be coupled to each other through the bus 660 . The bus 660 corresponds to a path through which data is moved.

The central processing unit 610 may include a control unit, an arithmetic unit, and the like to execute a program and process data.

The interface 620 may perform a function of transmitting data to or receiving data from a communication network. The interface 520 may be in a wired or wireless form. For example, the interface 520 may include an antenna or a wired/wireless transceiver.

The peripheral device 630 may input/output data including a mouse, a keyboard, a display device, and a printer device.

The main memory device 640 may transmit/receive data to/from the central processing unit 610 and may store data and/or instructions required for program execution. The semiconductor device according to some embodiments of the present invention may be provided as some components of the main memory device 640 .

The auxiliary storage device 650 may include a non-volatile storage device such as a magnetic tape, a magnetic disk, a floppy disk, a hard disk, or an optical disk to store data and/or instructions. The auxiliary storage device 650 may store data even when the power of the electronic system is cut off.

In addition, the semiconductor device according to some embodiments of the present invention includes a computer, an Ultra Mobile PC (UMPC), a workstation, a net-book, a Personal Digital Assistants (PDA), a portable computer, and a web tablet. ), wireless phone, mobile phone, smart phone, e-book, PMP (portable multimedia player), portable game console, navigation device, black box (black box), digital camera, 3-dimensional television, digital audio recorder, digital audio player, digital picture recorder, digital A digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, a computer Provided as one of various components of an electronic device, such as one of various electronic devices constituting a network, one of various electronic devices constituting a telematics network, an RFID device, or one of various components constituting a computing system can be

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those of ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: substrate 120: first interface layer
130: first gate insulating layer 141: first barrier layer
142: second barrier film 143: first oxide film
150: first gate electrode 160: first gate spacer
170: first source/drain region

Claims (20)

a gate insulating film formed on the substrate;
a first barrier film formed on the gate insulating film;
an oxide film formed on the first barrier film;
a second barrier film formed on the oxide film;
a gate electrode formed on the second barrier layer; and
In the substrate, including a source/drain disposed on both sides of the gate electrode,
The oxide layer includes an oxide formed by oxidizing a material included in the first barrier layer,
The oxide film is an amorphous semiconductor device. The method of claim 1,
The first barrier layer includes a conductive material. 3. The method of claim 2,
The first barrier layer and the second barrier layer include the same material. 3. The method of claim 2,
The first barrier layer includes Ti. delete The method of claim 1,
The thickness of the oxide film is 20 angstroms or less. a substrate having a first region and a second region defined thereon;
a first transistor formed in the first region, the first transistor including a first gate insulating layer, a first barrier layer formed on the first gate insulating layer, and first sources/drains in the substrate; and
A second transistor formed in the second region, comprising a second gate insulating film, a second barrier film formed on the second gate insulating film, an oxide film formed on the second barrier film, and a third barrier formed on the oxide film a second transistor including a film, a gate electrode formed on the third barrier film, and a second source/drain in the substrate;
the first transistor does not include the gate electrode;
The oxide layer includes an oxide formed by oxidizing a material included in the second barrier layer,
The first transistor has a first channel length, and the second transistor has a second channel length different from the first channel length. 8. The method of claim 7,
The second channel length is greater than the first channel length. 8. The method of claim 7,
The first to third barrier layers include a conductive material. 10. The method of claim 9,
The first to third barrier layers may include the same material. 10. The method of claim 9,
The first to third barrier layers include Ti. 8. The method of claim 7,
The oxide film is an amorphous semiconductor device. 13. The method of claim 12,
The thickness of the oxide film is 20 angstroms or less. an active fin extending on a substrate in a first direction and protruding from the substrate;
a gate insulating layer formed on the active fin to extend in a second direction crossing the first direction;
a first barrier film formed on the gate insulating film;
an oxide film formed on the first barrier film;
a second barrier film formed on the oxide film;
a gate electrode formed on the second barrier layer; and
In the active fin, including a source/drain disposed on both sides of the gate electrode,
The oxide layer includes an oxide formed by oxidizing a material included in the first barrier layer,
The oxide film is an amorphous semiconductor device. forming an interlayer insulating film including a trench on the substrate;
forming a gate insulating film on the inner surface of the trench;
forming a first barrier film on the gate insulating film;
exposing the first barrier film to an oxygen environment to form an oxide film on the first barrier film;
forming a second barrier film including the same material as that of the first barrier film on the oxide film;
forming a gate electrode on the second barrier layer;
The method of manufacturing a semiconductor device wherein the oxide film is amorphous. 16. The method of claim 15,
A method of manufacturing a semiconductor device using an in-situ process to form the first barrier film, the oxide film, and the second barrier film. 16. The method of claim 15,
The thickness of the oxide film is 20 Å or less. 16. The method of claim 15,
The first and second barrier layers include a conductive material. 19. The method of claim 18,
The first and second barrier layers include Ti. 16. The method of claim 15,
The method of manufacturing a semiconductor device further comprising forming an interface layer on a bottom surface of the trench before forming the gate insulating layer.

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