KR102383564B1 - Display panel and electroluminescence display using the same - Google Patents

Abstract

The present invention relates to a display panel and an electroluminescent display using the same. The display panel supplies the first data signal to the first data line in response to first and second switch control signals synchronized with the first gate signal and supplies the second data signal to the second data line, and a demultiplexer configured to supply a third data signal to the third data line and a fourth data signal to the fourth data line in response to third and fourth switch control signals synchronized with the gate signal.

Description

DISPLAY PANEL AND ELECTROLUMINESCENCE DISPLAY USING THE SAME

The present invention relates to a display panel in which a demultiplexer (DEMUX) is disposed between a data driving circuit and data lines, and an electroluminescent display using the same.

The flat panel display includes a liquid crystal display (LCD), an electroluminescence display, a field emission display (FED), and a plasma display panel (PDP).

The electroluminescent display device is roughly classified into an inorganic light emitting display device and an organic light emitting display device according to the material of the light emitting layer. The active matrix type organic light emitting diode display includes an organic light emitting diode (hereinafter, referred to as "OLED") that emits light by itself, and has a fast response speed and high luminous efficiency, luminance and viewing angle. There are advantages.

An OLED of an organic light emitting display device includes an anode electrode and a cathode electrode, and an organic compound layer formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL). When a power supply voltage is applied to the anode and the cathode, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the light emitting layer (EML) to form excitons, and as a result, the light emitting layer (EML) emits visible light will occur

Each of the pixels of the organic light emitting diode display includes a driving element for controlling a current flowing through the OLED. The driving device may be implemented as a transistor. Electrical characteristics of the driving device, such as threshold voltage and mobility, should be the same in all pixels, but the electrical characteristics of the driving device are not uniform due to process conditions and driving environment. The driving element receives a lot of stress as the driving time increases. In addition, the stress of the driving element varies according to the data of the input image. The electrical characteristics of the driving element are affected by stress. Accordingly, electrical characteristics of the driving elements change as the driving time elapses.

In order to improve the image quality and lifespan of the organic light emitting diode display, a compensation circuit for compensating for a difference in driving characteristics of pixels has been applied to the organic light emitting display device. A compensation circuit for compensating for a difference in driving characteristics of pixels in an organic light emitting diode display may be divided into an internal compensation circuit and an external compensation circuit. The internal compensation circuit samples the threshold voltage of the driving device by using the internal compensation circuit disposed in each of the sub-pixels. The internal compensation circuit automatically compensates the threshold voltage deviation of the driving device in the pixel circuit by compensating the voltage of the data signal by the threshold voltage of the driving device. The external compensation circuit senses electrical characteristics of driving elements through a sensing path connected to the pixels, and modulates pixel data of an input image based on the sensing result to compensate for changes in driving characteristics of each of the pixels.

The internal compensation circuit must ensure sufficient sampling time. As the resolution of the display panel increases and the driving frequency of the display panel increases, one horizontal period during which data is written in pixels of one line in the display panel decreases. Therefore, the threshold voltage sampling period of the driving element allocated within one horizontal period this can only be reduced. If the time required for sampling the threshold voltage of the driving element is insufficient, the threshold voltage of the driving voltage may not be accurately sampled.

Meanwhile, in the electroluminescent display device, the number of channels of the data driver may be reduced by disposing a demultiplexer (DEMUX) between the data driver and the data lines. However, since the demultiplexer time-divisions and distributes the data voltage continuously output from the data driver to the data lines, a sampling time may be insufficient in the case of a pixel circuit to which an internal compensation circuit is applied. For example, in the case of a 1:2 demultiplexer, the data voltage is divided by time division into two data lines within one horizontal period. Since each of the two sub-pixels connected to the two data lines is driven by passing through the initialization step and the sampling step to the light emitting step within a 1/2 horizontal period, the sampling time is insufficient.

In the case of a pixel circuit having a specific structure, when a data voltage is supplied to two sub-pixels through the demultiplexer, the data voltage is supplied to one of the sub-pixels, whereas the initialization voltage is changed in the other sub-pixels due to the influence of the previous data voltage. There is a problem in that the driving element is not driven normally. Accordingly, there is a limitation in the structure of the pixel circuit connected to the demultiplexer.

In order to solve this problem, a method of supplying an initialization voltage to the other sub-pixel when a data voltage is applied to any one of the data of the two sub-pixels that receive the data voltage time division distribution through the demultiplexer may be considered. However, in this method, since the initialization voltage is supplied to the sub-pixels every 1/2 horizontal period, the swing width and the application time of the data voltage increase, which causes heat generation and power consumption of the data driver to increase.

The present invention provides a display panel capable of reducing the number of channels of a data driver by connecting a demultiplexer to data lines of a display panel, lengthening the sampling time of sub-pixels, and preventing malfunction, and an electroluminescence display using the same .

A display panel of the present invention includes: a data driver sequentially outputting first to fourth data signals through one channel; A first gate signal synchronized with the first and second data signals is supplied to a first gate line group connected to a pixel of an N-th (N is a positive integer) display line, and then applied to the third and fourth data signals. a gate driver supplying a synchronized second gate signal to a second gate line group connected to a pixel of an N+1th display line; After supplying the first data signal to a first data line and supplying the second data signal to a second data line in response to first and second switch control signals synchronized with the first gate signal, the second and a demultiplexer configured to supply the third data signal to a third data line and supply the fourth data signal to a fourth data line in response to third and fourth switch control signals synchronized with the gate signal.

The pixel of the N-th display line includes a first sub-pixel connected to the first data line and a second sub-pixel connected to the second data line.

The pixel of the N+1th display line includes a third sub-pixel connected to the third data line and a fourth sub-pixel connected to the fourth data line.

According to the present invention, the number of channels of the data driver can be reduced by connecting a demultiplexer to the data lines of the display panel, and a sampling error can be prevented by simultaneously performing initialization of sub-pixels, charging of data lines, and threshold voltage sampling of the driving device. and ensure sufficient sampling time.

1 is a block diagram showing an electroluminescent display device according to an embodiment of the present invention.
2 is a diagram schematically illustrating a connection structure between a demultiplexer and sub-pixels.
3 is a waveform diagram illustrating a pixel driving signal illustrated in FIG. 2 .
4 is a circuit diagram illustrating an example of a pixel circuit according to an embodiment of the present invention.
5 is a circuit diagram schematically illustrating an operation of an electroluminescent display device according to an embodiment of the present invention.
6 to 13 are diagrams showing the operation of the electroluminescent display device according to an embodiment of the present invention in stages.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only the embodiments allow the disclosure of the present invention to be complete, and those of ordinary skill in the art to which the present invention pertains It is provided to fully understand the scope of the invention, and the present invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiment of the present invention are exemplary, and therefore the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially identical elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When "includes", "includes", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, it may be interpreted as the plural unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship between two components is described as 'on One or more other elements may be interposed between those elements in which 'directly' or 'directly' are not used.

1st, 2nd, etc. may be used to distinguish the components, but the functions or structures of these components are not limited to the ordinal number or component name attached to the front of the component. For example, in the pixel circuit of FIG. 4 , ordinal numbers such as first, second, third, and fourth placed in front of the elements are sequentially charged to the data lines through the switch elements S1 to S4 based on the order in which they are sequentially charged. it will be pasted

The following embodiments can be partially or wholly combined or combined with each other, and technically various interlocking and driving are possible. Each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship.

In the electroluminescent display device of the present invention, pixel circuits, signal lines connected to the pixel circuits, a demultiplexer, and a gate driver may include a plurality of transistors. The transistors may include an n-channel MOSFET (NMOS) or a p-channel MOSFET (PMOS), and may be implemented as a thin film transistor (TFT) on a substrate of the display panel. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the transistor, carriers begin to flow from the source. The drain is an electrode through which carriers exit the TFT. In a transistor, the flow of carriers flows from source to drain. In the case of an n-channel MOSFET (NMOS), the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an n-channel MOSFET (NMOS), the direction of current flows from drain to source. In the case of a p-channel MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel MOSFET (PMOS), current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain are not fixed. For example, the source and drain may be changed according to an applied voltage. Accordingly, the invention is not limited by the names of the source and the drain. In the following description, the source and the drain will be referred to as first and second electrodes.

The gate signal supplied to the gate lines and the switch control signal applied to the switch elements of the demultiplexer swing between a gate on voltage and a gate off voltage. The gate-on voltage is set to a voltage at which the transistor is turned on, and the gate-off voltage is an off voltage of the transistor. The transistor is turned on in response to the gate-on voltage, while turned-off in response to the gate-off voltage. In the case of an n-channel MOSFET (NMOS), the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In the case of a p-channel MOSFET (PMOS), the gate-on voltage may be a gate low voltage VGL, and the gate-off voltage may be a gate high voltage VGH.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, the electroluminescent display device will be mainly described with respect to the organic light emitting display device including the organic light emitting material. The technical spirit of the present invention is not limited to an organic light emitting display device, and may be applied to an inorganic light emitting display device including an inorganic light emitting material.

The present invention distributes the data voltage output from the data driver through one channel to N (N is an even number of 2 or more) data lines in a time division method using a demultiplexer (DEMUX).

Referring to FIG. 1 , an electroluminescent display device according to an embodiment of the present invention includes a display panel 100 and a display panel driving circuit.

The display panel 100 includes an active area AA for displaying an input image on the screen. A pixel array is disposed in the active area AA. The pixel array includes a plurality of data lines 102 , a plurality of gate lines 103 intersecting the data lines 102 , and pixels arranged in a matrix form.

Each of the pixels may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to implement color. Each of the pixels may further include a white sub-pixel. Each of the sub-pixels 101 includes a pixel circuit. The pixel circuit may include an internal compensation circuit. As an example, the pixel circuit may be implemented as a circuit as in the example of FIG. 4 , but is not limited thereto.

Touch sensors may be disposed on the display panel 100 . The touch input may be sensed using separate touch sensors or may be sensed through pixels. The touch sensors may be implemented as on-cell type or add-on type touch sensors disposed on the screen of the display panel or embedded in a pixel array. can

The display panel driving circuit includes a data driver 110 and a gate driver 120 . The display panel driving circuit further includes a demultiplexer 112 disposed between the data driver 110 and the data lines 102 .

The display panel driving circuit writes input image data into pixels of the display panel 100 under the control of a timing controller (TCON) 130 . The display panel driving circuit may further include a touch sensor driver for driving the touch sensors. The touch sensor driver is omitted from FIG. 1 . In the mobile device, the display panel driving circuit, the timing controller 130 , and the power circuit may be integrated into one integrated circuit.

The display panel driving circuit may operate in a low-speed driving mode. The low-speed driving mode may be set to reduce power consumption of the display device when the input image does not change by a preset number of frames by analyzing the input image. In the low-speed driving mode, when a still image is input for a predetermined time or longer, power consumption may be reduced by controlling the data update period of the pixels by lowering the refresh rate of the pixels. The low-speed driving mode is not limited when a still image is input. For example, when the display device operates in the standby mode or when a user command or an input image is not input to the display panel driving circuit for a predetermined time or more, the display panel driving circuit may operate in the low speed driving mode.

The data driver 110 generates a data signal by converting digital data of an input image received from the timing controller 130 into a gamma compensation voltage every frame period. The data driver 110 outputs a voltage of a data signal (hereinafter referred to as a “data voltage”) through an output buffer in each of the channels.

The demultiplexer 112 is disposed between the data driver 110 and the data lines 102 using a plurality of switch elements to distribute the data voltage output from the data driver 110 to the data lines 102 in a time division manner. do. In FIG. 2 , “S1 to S4” indicate switch elements of the demultiplexer 112 .

The gate driver 120 may be implemented as a gate in panel (GIP) circuit that is directly formed on the bezel region BZ of the display panel 100 together with the TFT array of the active region AA. The gate driver 120 outputs a gate signal to the gate lines 103 under the control of the timing controller 130 . The gate driver 120 may sequentially supply the gate signals to the gate lines 103 by shifting the gate signals using a shift register. The gate signal may include, but is not limited to, a scan signal for selecting pixels of a line in which data is to be written, and a light emission signal (hereinafter, referred to as “EM signal”) defining an emission time of pixels charged with data voltage. does not

As shown in FIG. 2 , the gate lines 103 include a first gate line group connected to sub-pixels of an N-th display line L(N), and an N+1-th display line L(N+1). )) and a second gate line group connected to the sub-pixels. The first gate line group includes first to third gate lines 31 to 33 . The second gate line group includes fourth to sixth gate lines 34 to 36 . The first gate signal is supplied to the first to third gate lines 31 to 33 . The second gate signal is supplied to the fourth to sixth gate lines 34 to 36 . The first and second gate signals include a scan signal and an EM signal as shown in FIG. 3 . The first and second gate signals share one scan signal.

The gate driver 120 may include a first gate driver 121 and a second gate driver 122 . The first gate driver 121 outputs a scan signal and sequentially shifts the scan signal according to a shift clock. The second gate driver 122 outputs the EM signal and sequentially shifts the EM signal according to the shift clock. In the case of the model without the bezel BZ, the switch elements constituting the first and second gate drivers 121 and 122 may be dispersedly disposed in the active area AA.

The timing controller 130 receives digital video data DATA of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The host system may be any one of a television (Television) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, and a system of a mobile device.

The timing controller 130 multiplies the input frame frequency by i (i is a positive integer greater than 0) to control the operation timing of the display panel drivers 110, 112, and 120 with a frame frequency of the input frame frequency × i Hz. can The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase-Alternating Line) scheme. The timing controller 130 may lower the frame frequency to a frequency between 1 Hz and 30 Hz in order to lower the refresh rate of pixels in the low-speed driving mode.

The timing controller 130 controls the operation timing of the demultiplexer 112 and a data timing control signal for controlling the operation timing of the data driver 110 based on the timing signals Vsync, Hsync, DE received from the host system. A switch control signal for controlling the operation timing of the gate driver 120 and a gate timing control signal for controlling the operation timing of the gate driver 120 are generated. The voltage level of the gate timing control signal output from the timing controller 130 may be converted into a gate-on voltage and a gate-off voltage through a level shifter (not shown) and supplied to the gate driver 120 . The level shifter converts a low level voltage of the gate timing control signal into a gate low voltage VGL and converts a high level voltage of the gate timing control signal into a gate high voltage VGH. .

2 is a diagram schematically illustrating a connection structure between a demultiplexer and sub-pixels. 3 is a waveform diagram illustrating a pixel driving signal illustrated in FIG. 2 .

2 and 3 , the display panel 100 includes a plurality of display lines L(N) and L(N+1). The display lines L(N) and L(N+1) include a plurality of sub-pixels 1011 to 1014 that are simultaneously selected by a gate signal. The N-th (N is a positive integer) display line L(N) is the first and second sub-pixels 1011 and 1012 connected to the gate lines 31 to 33 and the data lines 211 and 212 . includes The N+1-th display line L(N+1) includes third and fourth sub-pixels 1013 and 1014 connected to gate lines 34 to 36 and data lines 213 and 214 . .

The data driver 110 outputs the data voltage Vdata through the output buffer AMP. A voltage (hereinafter, referred to as a “data voltage”) Vdata of a data signal output through an arbitrary channel from the data driver 110 is a first data signal and a second sub-pixel to be supplied to the first sub-pixel 1011 . The data voltage is output in order of the second data signal to be supplied to the 1012 , the third data signal to be supplied to the third sub-pixel 1013 , and the fourth data signal to be supplied to the fourth sub-pixel 1014 . In the data driver 110 , one channel is connected to the demultiplexer 112 through the output buffer AMP.

The demultiplexer 112 may sequentially connect one channel of the data driver 110 to the four data lines 211 to 214 in response to the switch control signals MUX1 to MUX4 as shown in FIG. 2 . Accordingly, the demultiplexer 112 may reduce the number of channels of the data driver 110 by 1/4 compared to the data lines 211 to 214 .

The demultiplexer 112 includes first to fourth switch elements S1 to S4. The first switch element S1 connects the output buffer AMP to the first data line 211 in response to the first switch control signal MUX1 . The second switch element S2 connects the output buffer AMP to the second data line 212 in response to the second switch control signal MUX2 generated following the first switch control signal MUX1 . The third switch element S3 connects the output buffer AMP to the third data line 213 in response to the third switch control signal MUX3 generated following the second switch control signal MUX2 . The fourth switch element S4 connects the output buffer AMP to the fourth data line 214 in response to the fourth switch control signal MUX4 generated following the third switch control signal MUX3 . The first to fourth switch control signals MUX1 to DMUX4 may be sequentially generated so that a data voltage may be supplied to the data lines 211 to 214 in a time division manner. After the first switch element S1 is turned on by the first switch control signal MUX1 and the data voltage Vdata is applied to the first data line 211, the second switch element ( S2 is turned on by the second switch control signal MUX2 to apply the data voltage Vdata to the second data line 212 . Subsequently, after the third switch element S3 is turned on by the third switch control signal MUX3 and the data voltage Vdata is applied to the third data line 213 , the fourth switch element S4 is turned on. It is turned on by the fourth switch control signal MUX4 to apply the data voltage Vdata to the fourth data line 214 .

The demultiplexer 112 may be disposed at an edge of the display panel 100 to which the IC of the data driver 110 is to be attached, or may be built into the IC of the data driver 110 . When the demultiplexer 112 is formed on the display panel 100 , the size of the IC of the data driver 110 is reduced, thereby reducing the IC cost. When the demultiplexer 112 is built into the IC of the data driver 110 , the driving performance of the display panel may be improved.

Capacitors C1 to C4 are connected to each of the data lines 211 to 214 . The capacitors C1 to C4 may be parasitic capacitances connected to the data lines 211 to 214 . If the parasitic capacitance is small, a separate capacitor may be connected to the data lines 211 and 214 . The first and third data lines 211 and 213 are adjacent to each other without a sub-pixel therebetween. The second and fourth data lines 212 and 214 are adjacent with no sub-pixels therebetween. Accordingly, two data lines are adjacent between left and right adjacent sub-pixels. It should be designed so that the parasitic capacitance between these data lines is minimized. For example, an insulating layer between adjacent data lines may be thickly formed of an insulating material having a low dielectric constant.

The switch elements S1 to S4 and the capacitors C1 to C4 of the demultiplexer 112 sample the data voltage. The switch elements S1 and S2 and the capacitors C1 and C2 connected to the first and second data lines 211 and 214 are connected to the sub-pixels 1011 and 1012 of the N-th display line L(N). The data voltage Vdata to be supplied is sampled and maintained. The switch elements S3 and S4 and the capacitors C3 and C4 connected to the third and fourth data lines 213 and 214 are the sub-pixels 1013 of the N+1-th display line L(N+1). , 1014) to sample and hold the data voltage Vdata.

Power voltages such as the pixel driving voltage VDD, the low potential power voltage VSS, and the initialization voltage VINI are supplied to the pixel circuit formed in each of the sub-pixels. The power supply voltage may be VDD=5V, VSS=-5V, VINI=1V~-1V, but is not limited thereto. The gate signal and the switch control signal swing between the gate high voltage VGH and the gate low voltage VGL. VGH and VGL may be VGH=10V, VGL=-5V, but is not limited thereto. The data voltage Vdata may be a voltage between 5V and 1V, but is not limited thereto. These voltages may vary depending on the driving characteristics of the display panel or the product model.

The first sub-pixel 1011 is connected to the first switch element S1 , the first capacitor C1 , the first data line 211 , and the first to third gate lines 31 to 33 . The second sub-pixel 1012 is connected to the second switch element S2 , the second capacitor C2 , the second data line 212 , and the first to third gate lines 31 to 33 . The third sub-pixel 1013 is connected to the third switch element S3 , the third capacitor C3 , the third data line 213 , and the fourth to sixth gate lines 34 to 36 . The fourth sub-pixel 1014 is connected to the fourth switch element S4 , the fourth capacitor C4 , the fourth data line 214 , and the fourth to sixth gate lines 34 to 36 .

The gate signal includes a scan signal and an EM signal. An N-1 th scan signal SCAN(N-1) is applied to the first gate line 31 . The N-1th scan signal SCAN(N-1) is a pulse of a gate-on voltage synchronized with the first and second data signals D1 and D2 to be written in the first and second sub-pixels 1011 and 1012 . The N-th scan signal SCAN(N-1) is followed by the N-th scan signal SCAN(N) is generated. The N-th scan signal SCAN(N) includes the third and fourth It is generated as a pulse of a gate-on voltage synchronized with the third and fourth data signals D3 and D4 to be written in the sub-pixels 1013 and 1014. Following the N-th scan signal SCAN(N), the N+th A first scan signal SCAN(N) is generated, and the (N+1)th scan signal SCAN(N+1) is to be written in fifth and sixth sub-pixels of an N+1th display line (not shown). It is generated as a pulse of the gate-on voltage synchronized with the fifth and sixth data signals D5 and D6. Each of the scan signals SCAN(N-1) to SCAN(N+1) is a pulse of one horizontal period 1H. have a width

The N-th scan signal SCAN(N-1) is synchronized with the switch control signals MUX1 and MUX2 so as to overlap the first and second switch control signals MUX1 and MUX2. The N-th scan signal SCAN( N) is synchronized with the switch control signals MUX3 and MUX4 so as to overlap the third and fourth switch control signals MUX3 and MUX4 The pulse width of each of the switch control signals MUX1 to MUX4 is approximately 1/2 horizontal is the period

The N-th EM signal EM(N) defines an emission time of the N-th display line L(N). The N-th EM signal EM(N) blocks light emission of the sub-pixels 1011 and 1012 of the N-th display line L(N) during a period in which the sub-pixels 1011 and 1012 are initialized and sampled. After this, the emission time of the N-th display line L(N) for emitting the sub-pixels 1011 and 1012 is defined. The Nth EM signal EM(N) is generated as a pulse of a gate-off voltage. The N-th EM signal EM(N) has a pulse width of approximately 4 horizontal periods overlapping the N-2 th and N+1 th scan signals SCAN(N-2) and SCAN(N). The N+1-th EM signal EM(N+1) is applied to the sub-pixels 1013 and 1014 of the N+1-th display line L(N+1) during a period in which the sub-pixels 1013 and 1014 are initialized and sampled. After blocking the light emission of 1013 and 1014 , the emission time of the N+1th display line L(N+1) for emitting the sub-pixels 1013 and 1014 is defined. The N+1th EM signal EM(N+1) is generated as a pulse of a gate-off voltage. The N+1th EM signal EM(N+1) is a pulse of approximately 4 horizontal periods overlapping the N-1th and N+2th scan signals SCAN(N-1) to SCAN(N+2)) have a width The N+2th scan signal SCAN(N+2) omitted from the drawing is generated with a pulse width of one horizontal period 1H following the N+1th scan signal SCAN(N+1).

4 is a circuit diagram illustrating an example of a pixel circuit according to an embodiment of the present invention. The pixel circuit of FIG. 4 is a pixel circuit applied to the sub-pixels 1011 and 1012 of the N-th display line L(N). In the case of the sub-pixels 1011 and 1012 of the N+1-th display line L(N+1), the gate signal is the second gate signal SCAN(N) and SCAN(N+1) shown in FIG. 3 . ), EM(N+1) is applied to the pixel circuit shown in FIG.

Referring to FIG. 4 , an example of a pixel circuit includes a light emitting element EL, a plurality of thin film transistors (TFTs) T1 to T6 , DT, and a storage capacitor Cst. The TFTs T1 to T6 and DT may be implemented as p-type TFTs (PMOS), but are not limited thereto.

The switch TFTs T1 , T2 , T5 , and T6 are turned on/off according to the gate signal to initialize the pixel circuit, and then form a threshold voltage sampling path of the driving element DT in the sampling step, and the data voltage (Vdata) is supplied to the storage capacitor (Cst). The switch TFTs T3 and T4 switch a current path between the driving element DT and the light emitting element DT. When the gate and drain of the driving device DT are connected, the driving device DT operates in a diode form so that the source-gate voltage of the driving device DT rises to the threshold voltage of the driving device DT, so that the storage capacitor ( Cst) is sampled.

The light emitting element EL may be implemented as an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the OLED is connected to the fourth and sixth switch TFTs T4 and T6 through the sixth node n6. The cathode of the OLED is connected to the VSS electrode to which the low potential power voltage VSS is applied. The OLED emits light with a current supplied through the driving TFT (DT). The current path of the OLED is switched by the third and fourth switch TFTs T3 and T4.

The storage capacitor Cst is connected between the first node n1 and the second node n2 . The data voltage Vdata compensated by the threshold voltage Vth of the driving TFT DT is charged in the storage capacitor Cst. Since the data voltage Vdata in each of the sub-pixels 101 is compensated by the threshold voltage Vth of the driving TFT DT, the characteristic deviation of the driving TFT DT in the sub-pixels 101 is compensated for uniformity. It can be driven by driving characteristics.

The first switch TFT T1 connects the first node n1 and the fourth node n4 in response to the N-th scan signal SCAN(N). The first node n1 is connected to the gate of the driving TFT DT, the first electrode of the storage capacitor Cst, and the first electrode of the first switch TFT T1. The fourth node n4 is connected to the second electrode of the driving TFT DT, the second electrode of the first switch TFT T1, and the first electrode of the fourth switch TFT T4. The gate of the first switch TFT T1 receives the N-th scan signal SCAN(N). A first electrode of the first switch TFT (T) is connected to a first node (n1), and a second electrode of the first switch TFT (T1) is connected to a fourth node (n4).

The second switch TFT T2 supplies the data voltage Vdata to the third node n3 in response to the N-th scan signal SCAN1 . The gate of the second switch TFT T2 is supplied with the N-th scan signal SCAN(N). The first electrode of the second switch TFT T2 is connected to the third node n3. The second electrode of the second switch TFT T2 is supplied with the data voltage Vdata through the data line. The third node n3 is connected to the first electrode of the second switch TFT T20, the second electrode of the third TFT T3, and the second electrode of the driving TFT DT.

The third switch TFT T3 connects the second node n2 to the third node n3 in response to the EM signal EM(N). The gate of the third switch TFT T3 receives the EM signal EM(N). The first electrode of the third switch TFT T3 is connected to the second node n2. The second electrode of the third switch TFT T3 is connected to the third node n3. The second node n2 is connected to the VDD line to which the pixel driving voltage VDD is supplied and the second electrode of the storage capacitor Cst.

The fourth switch TFT T4 connects the fourth node n4 to the sixth node n6 in response to the EM signal EM(N). The fifth node n5 is connected to the second electrode of the fourth switch TFT T4 , the second electrode of the sixth switch TFT T6 , and the anode of the light emitting element EL. The gate of the fourth switch TFT T4 receives the EM signal EM(N). The first electrode of the fourth switch TFT T4 is connected to the fourth node n4 , and the second electrode is connected to the sixth node n6 . The sixth node n6 is connected to the second electrode of the fourth switch TFT T4 , the second electrode of the sixth switch TFT T6 , and the anode of the light emitting element EL.

The fifth switch TFT T5 connects the first node n1 to the fifth node n1 in response to the N-1 th scan signal SCAN(N-1). The fifth node n5 is connected to the Vini line to which the initialization voltage Vini is supplied, the second electrode of the fifth switch TFT T5, and the first electrode of the sixth switch TFT T6. The gate of the fifth switch TFT T5 receives the N-1 th scan signal SCAN(N-1). The first electrode of the fifth switch TFT T5 is connected to the first node n1 , and the second electrode is connected to the fifth node n5 .

The sixth switch TFT T6 connects the fifth node n5 to the sixth node n6 in response to the N-th scan signal SCAN(N). The gate of the sixth switch TFT T6 receives the N-th scan signal SCAN(N). The first electrode of the sixth switch TFT T6 is connected to the fifth node n5 , and the second electrode is connected to the sixth node n6 .

The driving TFT DT is a driving element that controls a current flowing through the light emitting element EL according to the source-gate voltage Vsg. The driving TFT DT includes a gate connected to the first node n1 , a first electrode connected to the third node n3 , and a third electrode connected to the second node n2 .

5 is a circuit diagram schematically illustrating an operation of an electroluminescent display device according to an embodiment of the present invention. FIG. 5 is an example in which the pixel circuit shown in FIG. 4 is applied to the four sub-pixels 1011 to 1014 as shown in FIG. 2 .

Referring to FIG. 5 , in the present invention, the sampling error is performed by simultaneously initializing the sub-pixels 1011 to 1014 , charging the data lines 211 to 214 , and sampling the threshold voltage of the driving TFTs DT1 to DT4 . It is possible to prevent a malfunction of the sub-pixels due to , and secure a sufficient sampling time. A sampling time of sub-pixels can be secured twice as compared to a conventional display device to which a demultiplexer is applied.

According to the present invention, the sub-pixels 1011 and 1012 of the N-th display line L(N) are initialized and the data lines 211 and 212 as shown by a thick solid line for one horizontal period (1H). The data voltage Vdata is charged to the capacitors C1 and C2 of The present invention supplies the data voltage Vdata charged in the capacitors C1 and C2 to the sub-pixels 1011 and 1012 and the driving TFTs DT1 for the next one horizontal period (1H), as shown by a thick dotted line. , DT2 ), the sub-pixels 1013 and 1014 of the N+1-th display line L(N+1) are initialized, and the capacitor C1 of the data lines 213 and 214 is sampled. , C2) is charged.

6 to 13 are diagrams showing the operation of the electroluminescent display device according to an embodiment of the present invention in stages.

6 and 7 , an N−1th scan signal SCAN(N−1) is applied to the subpixels 1011 and 1012 of the Nth display line L(N) during the first period t01. is authorized During the first period t01 , the data driver 110 displays the N-th display during the first period t01 through one channel connected to the first to fourth data lines 211 to 214 through the demultiplexer 112 . The data voltage Vdata to be supplied to the sub-pixels 1011 and 1012 of the line L(N) is sequentially output in synchronization with the N-1 th scan signal SCAN(N-1). In FIG. 7 , “D1” denotes a first data voltage D1 to be supplied to the first sub-pixel 1011 , and “D2” denotes a second data voltage D2 to be supplied to the second sub-pixel 1012 . The N-1 th scan signal SCAN(N-1) overlaps the first and second switch control signals MUX1 and MUX2.

During the first period t01, the fifth switch TFT T5 is turned on and the first switch element S1 is turned on in the sub-pixels 1011 and 1012 of the N-th display line L(N). After being turned on, the second switch element S2 is turned on. Accordingly, the first and second sub-pixels 1011 and 1012 are initialized and at the same time the data voltage D1 is applied to the capacitors C1 and C2 of the data lines 211 and 212 connected to the sub-pixels 1011 and 1012. , D2) is charged. In the sub-pixels 1011 and 1012 , the initialization voltage VINI is supplied to the first node n1 to turn on the driving TFTs DT1 and DT2 and the storage capacitor Cst is initialized to the initialization voltage VINI. do.

8 and 9 , the second sub-pixels 1011 and 1012 of the N-th and N+1-th display lines L(N) and L(N+1) are applied during the second period t02. An N scan signal SCAN(N) is applied. Accordingly, the first and second switch TFTs T1 and T2 are turned on in the sub-pixels 1011 and 1012 of the N-th display line L(N) to charge the data lines 211 and 212 . The data voltages D1 and D2 are applied to the first node n1. As a result, the data voltage Vdata+Vth compensated by the threshold voltage Vth of the driving TFTs DT1 and DT2 in the sub-pixels 1011 and 1012 is stored in the storage capacitor Cst. This data voltage Vdata+Vth is a voltage representing the luminance of the sub-pixels 1011 and 1012 . At the same time, the sub-pixels 1013 and 1014 of the N+1-th display line L(N+1) are initialized, and the data lines 213 and 214 connected to the sub-pixels 1013 and 1014 are initialized. is charged with the data voltage Vdata.

During the second period t02, the data driver 110 operates one channel through the sub-pixels 1013 and 1014 of the N+1-th display line L(N+1) during the second period t02) The data voltage Vdata to be supplied to is sequentially output in synchronization with the N-th scan signal SCAN(N). In FIG. 9 , “D3” denotes a third data voltage D3 to be supplied to the third sub-pixel 1013 , and “D4” denotes a fourth data voltage D4 to be supplied to the fourth sub-pixel 1014 . The N-th scan signal SCAN(N) overlaps the third and fourth switch control signals MUX3 and MUX4.

During the second period t02, the fifth switch TFT T5 is turned on in the sub-pixels 1013 and 1014 of the N+1-th display line L(N+1), and at the same time, the third switch element ( After S3 is turned on, the fourth switch element S4 is turned on. Accordingly, while the third and fourth sub-pixels 1013 and 1014 are initialized, the data voltage D3 is applied to the capacitors C3 and C4 of the data lines 213 and 214 connected to the sub-pixels 1013 and 1014. , D4) is charged. In the sub-pixels 1013 and 1014 , the initialization voltage VINI is supplied to the first node n1 to turn on the driving TFTs DT3 and DT4 and the storage capacitor Cst is initialized to the initialization voltage VINI. do.

10 and 11 , the N+1th scan signal SCAN(N) is transmitted to the subpixels 1013 and 1014 of the N+1th display line L(N+1) during the third period t03. +1)) is applied. Accordingly, the first and second switch TFTs T1 and T2 are turned on in the sub-pixels 1013 and 1014 of the N+1-th display line L(N+1), so that the data lines 213 and 213 are turned on. Data voltages D3 and D4 charged in 214 are applied to the first node n1. As a result, the data voltage Vdata+Vth compensated by the threshold voltage Vth of the driving TFTs DT3 and DT4 in the sub-pixels 1013 and 1014 is stored in the storage capacitor Cst. This data voltage Vdata+Vth is a voltage representing the luminance of the sub-pixels 1013 and 1014 .

12 and 13 , the EM signal EM(N) is gated on to the sub-pixels 1013 and 1014 of the N-th display line L(N) after sampling has been completed during the third period t03. A voltage VGL is applied. In this case, the light emitting elements EL in the sub-pixels 1011 and 1012 of the N-th display line L(N) emit light with current flowing through the driving TFTs DT1 and DT2.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 101, 1011 to 1014: sub-pixel
102, 211 to 214: data lines 103, 31 to 36: gate lines
110: data driver 120: gate driver
130: timing controller

Claims (18)

a data driver sequentially outputting first to fourth data signals through one channel;
A first gate signal synchronized with the first and second data signals is supplied to a first gate line group connected to a pixel of an N-th (N is a positive integer) display line, and then applied to the third and fourth data signals. a gate driver supplying a synchronized second gate signal to a second gate line group connected to a pixel of an N+1th display line;
After supplying the first data signal to a first data line and supplying the second data signal to a second data line in response to first and second switch control signals synchronized with the first gate signal, the second a demultiplexer configured to supply the third data signal to a third data line and supply the fourth data signal to a fourth data line in response to third and fourth switch control signals synchronized with the gate signal;
the pixel of the N-th display line includes a first sub-pixel connected to the first data line and a second sub-pixel connected to the second data line;
the pixel of the N+1th display line includes a third sub-pixel connected to the third data line and a fourth sub-pixel connected to the fourth data line;
Each of the first to fourth sub-pixels is
light emitting element;
a driving transistor for driving the light emitting device;
a plurality of switch transistors turned on/off according to the first and second gate signals; and
a capacitor formed between the gate of the driving transistor and a power line to which a predetermined pixel driving voltage is supplied;
the capacitor is connected to the gate of the driving transistor through a first node and is connected to the power line through a second node,
wherein the driving transistor includes the gate connected to the first node, a first electrode connected to a third node, and a second electrode connected to a fourth node connected to the light emitting device. The method of claim 1,
Each of the first to fourth data lines is
A display panel comprising a capacitor to which a voltage of a data signal is charged. The method of claim 1,
The demultiplexer is
a first switch element turned on according to the first switch control signal to supply the first data signal to the first data line;
a second switch element turned on according to the second switch control signal to supply the second data signal to the second data line;
a third switch element that is turned on according to the generated third switch control signal and supplies the third data signal to the third data line; and
and a fourth switch element turned on according to the fourth switch control signal to supply the fourth data signal to the fourth data line. 4. The method of claim 3,
The first gate signal is
an N-1 th scan signal generated as a pulse of a gate-on voltage synchronized with the first and second switch control signals;
an N-th scan signal generated as a pulse of a gate-on voltage synchronized with the third and fourth switch control signals; and
and an Nth light emission signal generated by a pulse of a gate-off voltage overlapping the N-1th scan signal and the Nth scan signal,
The second gate signal is
the Nth scan signal;
an N+1th scan signal generated subsequent to the Nth scan signal; and
and an N+1th emission signal generated by a pulse of a gate-off voltage overlapping the Nth scan signal and the N+1th scan signal. 5. The method of claim 4,
Each of the scan signals is
It is generated as a pulse of 1 horizontal period,
Each of the first to fourth switch control signals is generated as a pulse of 1/2 horizontal period. 5. The method of claim 4,
The first gate line group comprises:
a first gate line to which the N-1th scan signal is supplied;
a second gate line to which the Nth scan signal is supplied; and
and a third gate line to which the N-th light emitting signal is supplied,
The second gate line group,
a fourth gate line to which the Nth scan signal is supplied;
a fifth gate line to which the N+1th scan signal is supplied; and
and a sixth gate line to which the N+1th emission signal is supplied. The method of claim 1,
After the first and second sub-pixels are initialized and the first data signal is supplied to the first data line and the second data signal is supplied to a second data line,
A display panel in which the voltage of the first data signal charged in the first data line is supplied to the first sub-pixel and the voltage of the second data signal charged in the second data line is supplied to the second sub-pixel. 8. The method of claim 7,
The third and fourth sub-pixels are initialized while the voltage of the data signal is supplied to the first and second sub-pixels;
The third data signal is supplied to the third data line and the fourth data signal is supplied to a fourth data line when the third and fourth sub-pixels are initialized. delete 5. The method of claim 4,
The first and second sub-pixels are
a first switch transistor connecting the first node and the fourth node in response to the Nth scan signal;
a second switch transistor for supplying a voltage of a data signal to the third node in response to the Nth scan signal;
a third switch transistor for connecting the second node to the third node in response to the Nth light emitting signal;
a fourth switch transistor connecting the fourth node to a sixth node in response to the Nth light emitting signal;
a fifth switch transistor connecting the first node to a fifth node in response to the N-1th scan signal; and
A sixth switch transistor for connecting the fifth node to a sixth node in response to the Nth scan signal,
A predetermined initialization voltage is supplied to the fifth node,
A display panel in which an anode of the light emitting device is connected to the sixth node. 5. The method of claim 4,
The third and fourth sub-pixels are
a first switch transistor connecting the first node and the fourth node in response to the N+1th scan signal;
a second switch transistor for supplying a voltage of a data signal to the third node in response to the N+1th scan signal;
a third switch transistor connecting the second node to the third node in response to the N+1th light emission signal;
a fourth switch transistor connecting the fourth node to a sixth node in response to the N+1th light emission signal;
a fifth switch transistor connecting the first node to a fifth node in response to the Nth scan signal; and
A sixth switch transistor for connecting the fifth node to a sixth node in response to the N+1th scan signal,
A predetermined initialization voltage is supplied to the fifth node,
A display panel in which an anode of the light emitting device is connected to the sixth node. a data driver sequentially outputting first to fourth data signals through one channel;
A first gate signal synchronized with the first and second data signals is supplied to a first gate line group connected to a pixel of an N-th (N is a positive integer) display line, and then applied to the third and fourth data signals. a gate driver supplying a synchronized second gate signal to a second gate line group connected to a pixel of an N+1th display line;
After supplying the first data signal to a first data line and supplying the second data signal to a second data line in response to first and second switch control signals synchronized with the first gate signal, the second a demultiplexer configured to supply the third data signal to a third data line and supply the fourth data signal to a fourth data line in response to third and fourth switch control signals synchronized with the gate signal;
The pixel of the N-th display line is
a first sub-pixel connected to the first data line and a second sub-pixel connected to the second data line;
the pixel of the N+1th display line includes a third sub-pixel connected to the third data line and a fourth sub-pixel connected to the fourth data line;
Each of the first to fourth sub-pixels,
light emitting element;
a driving transistor for driving the light emitting device;
a plurality of switch transistors turned on/off according to the first and second gate signals; and
a capacitor formed between the gate of the driving transistor and a power line to which a predetermined pixel driving voltage is supplied;
the capacitor is
connected to the gate of the driving transistor through a first node and connected to the power line through a second node,
and the driving transistor includes the gate connected to the first node, a first electrode connected to a third node, and a second electrode connected to a fourth node connected to the light emitting device. 13. The method of claim 12,
The demultiplexer is embedded in an integrated circuit together with the data driver or is formed on a display panel in which the sub-pixels and the gate driver are formed. 14. The method of claim 13,
The first gate signal is
an N-1 th scan signal generated as a pulse of a gate-on voltage synchronized with the first and second switch control signals;
an N-th scan signal generated as a pulse of a gate-on voltage synchronized with the third and fourth switch control signals; and
and an Nth light emission signal generated by a pulse of a gate-off voltage overlapping the N-1th scan signal and the Nth scan signal,
The second gate signal is
the Nth scan signal;
an N+1th scan signal generated subsequent to the Nth scan signal; and
and an N+1th emission signal generated by a pulse of a gate-off voltage overlapping the Nth scan signal and the N+1th scan signal. 13. The method of claim 12,
After the first and second sub-pixels are initialized and the first data signal is supplied to the first data line and the second data signal is supplied to a second data line,
An electroluminescent display in which the voltage of the first data signal charged in the first data line is supplied to the first sub-pixel and the voltage of the second data signal charged in the second data line is supplied to the second sub-pixel Device. 16. The method of claim 15,
The third and fourth sub-pixels are initialized while the voltage of the data signal is supplied to the first and second sub-pixels;
The third data signal is supplied to the third data line and the fourth data signal is supplied to the fourth data line at the same time that the third and fourth sub-pixels are initialized. 15. The method of claim 14,
The first and second sub-pixels are
a first switch transistor connecting the first node and the fourth node in response to the Nth scan signal;
a second switch transistor for supplying a voltage of a data signal to the third node in response to the Nth scan signal;
a third switch transistor for connecting the second node to the third node in response to the Nth light emitting signal;
a fourth switch transistor connecting the fourth node to a sixth node in response to the Nth light emitting signal;
a fifth switch transistor connecting the first node to a fifth node in response to the N-1th scan signal; and
A sixth switch transistor for connecting the fifth node to a sixth node in response to the Nth scan signal,
A predetermined initialization voltage is supplied to the fifth node,
An electroluminescent display device in which the anode of the light emitting device is connected to the sixth node. 15. The method of claim 14,
The third and fourth sub-pixels are
a first switch transistor connecting the first node and the fourth node in response to the N+1th scan signal;
a second switch transistor for supplying a voltage of a data signal to the third node in response to the N+1th scan signal;
a third switch transistor connecting the second node to the third node in response to the N+1th light emission signal;
a fourth switch transistor connecting the fourth node to a sixth node in response to the N+1th light emission signal;
a fifth switch transistor connecting the first node to a fifth node in response to the Nth scan signal; and
A sixth switch transistor for connecting the fifth node to a sixth node in response to the N+1th scan signal,
A predetermined initialization voltage is supplied to the fifth node,
An electroluminescent display device in which the anode of the light emitting device is connected to the sixth node.

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