KR102372869B1 - Matrix operator and matrix operation method for artificial neural network - Google Patents

Abstract

The present invention provides a first buffer for receiving and storing a first matrix that is a multiplicand matrix, a second buffer for receiving and storing a second matrix that is a multiplier matrix multiplied by the first matrix, and a plurality of sequentially selected columns from the first matrix Elements are applied, a plurality of elements sequentially selected row by row in a second matrix corresponding to a column selected in the first matrix are applied, and each element of a column selected in the first matrix is multiplied by all elements of a row selected in the second matrix Comprising an operation unit for obtaining a result matrix that is a matrix multiplication operation result of the first matrix and the second matrix by accumulating and adding the multiplication operation results between the sequentially selected columns of the first matrix and the rows of the second matrix, the operation efficiency It is possible to provide a matrix operator and a matrix operation method for an artificial neural network capable of increasing computation speed and reducing power consumption.

Description

MATRIX OPERATOR AND MATRIX OPERATION METHOD FOR ARTIFICIAL NEURAL NETWORK

The present invention relates to an artificial neural network module and a scheduling method thereof, and to an artificial neural network module for high-efficiency computational processing and a scheduling method thereof.

Recently, an artificial neural network that mimics how the human brain recognizes patterns and processes various information in a manner similar to that of the brain has been applied and used in various fields.

Such an artificial neural network requires learning based on massive data, and in this process, a large amount of addition and multiplication operations must be performed. The same number of arithmetic circuits must be provided.

Therefore, recently, a new kind of hardware accelerator specialized in deep learning of artificial neural networks is receiving great attention. Deep learning accelerators have been presented in different forms depending on the usage environment and purpose. For example, a graphics processing unit (GPU) is mainly used in servers or workstations that value performance, and an FPGA (Field Programmable Gate Array) or ASIC (application specific integrated circuit) is used in edge devices such as smartphones that prioritize low power. Dedicated hardware designed for this purpose, that is, a Neural Processing Unit (NPU), is mainly used.

However, many accelerators that have been released so far lack the flexibility to respond to various types of layers or tensors used in various artificial neural networks due to the nature of dedicated hardware. This disadvantage has a problem in that it is difficult to cope with the deep learning applications and models that are currently widely used.

On the other hand, in order to variably use a plurality of computing devices, the control circuit becomes complicated, and thus some computing devices are not used and remain in an idle state in the process of performing calculations of the artificial neural network, resulting in inefficiency and unnecessary Additional power may be consumed.

Korean Patent Publication No. 10-2019-0055447 (published on May 23, 2019)

SUMMARY OF THE INVENTION It is an object of the present invention to provide a matrix operator and a matrix operation method capable of increasing computational efficiency and reducing power consumption by simultaneously performing multiplication and addition operations in parallel according to a pipeline technique.

In order to achieve the above object, a matrix operator for an artificial neural network according to an embodiment of the present invention includes: a first buffer for receiving and storing a first matrix that is a multiplicand matrix; a second buffer for receiving and storing a second matrix that is a multiplier matrix multiplied by the first matrix; and receiving a plurality of elements sequentially selected in units of columns from the first matrix, and receiving a plurality of elements sequentially selected in units of rows from the second matrix in correspondence to columns selected in the first matrix, in the first matrix Each element of the selected column is multiplied by all elements of the selected row in the second matrix, and the result of the multiplication operation between the sequentially selected first matrix column and the second matrix row is accumulated and added to form the first matrix and the second matrix. and an operator for obtaining a result matrix that is a result of a matrix multiplication operation of a matrix.

The operation unit receives and multiplies a corresponding one element among the elements of the column selected in the first matrix and all elements in the row selected in the second matrix, respectively, and adds the result of inter-element multiplication to the accumulated value of the previous multiplication result. It may include a plurality of arithmetic processing lanes for adding to obtain an element of a row of the partial accumulation matrix.

Each of the plurality of arithmetic processing lanes adds an element of a column in the first matrix and a row in the second matrix that are next selected according to a predetermined sequence while adding an inter-element multiplication result to a cumulative sum of a previous multiplication result. Multiplication operation can be performed by accepting all elements.

each of the plurality of arithmetic processing lanes includes a plurality of process elements, each of the plurality of process elements having a corresponding one of a corresponding one element in a selected column of the first matrix and a corresponding one of a plurality of elements in a selected row of the second matrix a multiplier that multiplies and multiplies a single element; an adder for updating the accumulated value by adding the multiplication result output from the multiplier to the accumulated value obtained by adding the multiplication result of the previously applied element; and an accumulation register configured to store the accumulated value updated by the adder.

The second buffer may select the i-th row of the second matrix when the i-th column (where i is a natural number) of the first matrix is selected from the first buffer.

The matrix operator is implemented as an artificial neural network module for performing an operation specified for at least one layer among a plurality of layers of the artificial neural network, wherein the first matrix is a feature map applied to the at least one layer, and the second matrix may be a kernel predetermined in the at least one layer.

A matrix operation method for an artificial neural network according to another embodiment of the present invention for achieving the above object includes receiving and storing a first matrix that is a multiplicand matrix and a second matrix that is a multiplier matrix multiplied by the first matrix; receiving a plurality of elements sequentially selected in units of columns in the first matrix and a plurality of elements sequentially selected in units of rows in the second matrix corresponding to columns selected in the first matrix; multiplying each element of a column selected in the first matrix by all elements of a row selected in the second matrix; and acquiring a result matrix that is a result of the matrix multiplication operation of the first matrix and the second matrix by cumulatively adding the multiplication operation results between the sequentially selected columns of the first matrix and the rows of the second matrix.

Therefore, the matrix operator and the matrix operation method for an artificial neural network according to an embodiment of the present invention allow the matrix multiplication operation and the addition operation performed in a plurality of layers of the artificial neural network to be simultaneously performed in parallel, thereby increasing computational efficiency and power consumption can be reduced. In particular, according to the pipeline method, it is possible to maximize the operation efficiency by allowing the addition operation to be accumulated while the multiplication operation is being performed.

1 shows a general structure of an example of an artificial neural network.
2 is a diagram illustrating a general matrix multiplication operation algorithm.
FIG. 3 shows the number of multiplication operations and addition operations required in the matrix multiplication operation algorithm of FIG. 2 .
4 shows a schematic structure of a matrix operator according to an embodiment of the present invention.
FIG. 5 shows a detailed configuration of an arithmetic processing lane of FIG. 4 .
FIG. 6 shows a detailed configuration of the process element of FIG. 5 .
7 illustrates a matrix multiplication operation algorithm according to an embodiment of the present invention.
8 shows a matrix operation method according to an embodiment of the present invention.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings. However, the present invention may be embodied in various different forms, and is not limited to the described embodiments. In addition, in order to clearly explain the present invention, parts irrelevant to the description are omitted, and the same reference numerals in the drawings indicate the same members.

Throughout the specification, when a part "includes" a certain component, it does not exclude other components unless otherwise stated, meaning that other components may be further included. In addition, terms such as "...unit", "...group", "module", and "block" described in the specification mean a unit that processes at least one function or operation, which is hardware, software, or hardware. and a combination of software.

1 shows a general structure of an example of an artificial neural network.

1 illustrates a convolutional neural network (CNN) as a representative example of an artificial neural network. In particular, as an artificial neural network used for optical character recognition in convolutional neural networks, it shows the general structure of LeNet-5, a representative convolutional neural network developed for postal zip code recognition and number recognition.

For example, LeNet-5 receives a 32 X 32 input image, repeatedly performs convolution and subsampling operations, extracts a feature map (f.map), and extracts from the feature map. It is configured to select a value corresponding to the most probable class among the predetermined classes based on the specified feature value.

Since LeNet-5 is a neural network developed to recognize numbers, LeNet-5 can classify feature values as numbers between 0 and 9, for example, and select one of numbers between 0 and 9 as a result value.

Hereinafter, LeNet-5 will be described as an example, but other convolutional neural networks and artificial neural networks also have basically similarities, and the concept of the present invention is not limited to LeNet-5 and can be applied to various artificial neural networks.

In FIG. 1, C denotes a convolution layer, S denotes a sub-sampling layer, and FC denotes a fully-connected layer, and the numbers after C, S, and FC denote layers indicates the index. That is, LeNet-5 includes three convolutional layers (C1, C2, C3), two subsampling layers (S1, S2), and two fully connected layers (FC1, FC2).

In the case of CNN as shown in Figure 1, each of a plurality of convolutional layers (C1, C2, C3) receives a feature map (f.map) (or an input image (Input)), and the applied feature map (f .map) (or an input image (Input)) is performed with a kernel predetermined in each of the corresponding convolutional layers (C1, C2, C3) and a convolution operation. And the convolution operation consists of a number of multiplication and addition operations. In addition, multiplication operations are performed in multiple fully connected layers (FC1 and FC2).

That is, in the case of the CNN shown in FIG. 1, a plurality of multiplication operations and addition operations must be performed. And in the case of artificial neural networks other than CNN, it is basically configured to perform multiplication and addition operations.

In general, artificial neural networks perform matrix multiplication and matrix addition operations by transforming a feature map (or input image) and a kernel into a matrix according to a predefined algorithm such as im2col (image blocks into columns). This improves the calculation speed.

As is well known, the inter-matrix multiplication operation multiplies specified elements in each matrix and then adds all the multiplied results to obtain an operation result. In this case, in the case of inter-element multiplication, one multiplication operation is performed in parallel, whereas the process of adding the inter-element multiplication result must be repeated a plurality of times according to the number of values to be added.

FIG. 2 is a diagram illustrating a general matrix multiplication operation method, and FIG. 3 illustrates the number of multiplication operations and addition operations required in the matrix multiplication operation method of FIG. 2 .

As shown in FIG. 2 , the matrix multiplication operation is performed with the elements of each row (#1, #2, #3, ..., #m) of A matrix of m × k size and B of size k × n. One element (# , &) are obtained.

Here, matrix A is called a multiplicand matrix, and matrix B is called a multiplier matrix.

Referring to the operation for obtaining the elements (#1, &1) of row 1, column 1 of the C matrix with reference to FIG. 3 , the matrix A, which is the multiplicand matrix, is read row by row according to the general matrix operation rules, and the matrix B, which is the multiplier matrix, is read. is read column-by-column, the read rows of the A matrix and the columns of the B matrix are multiplied by each other, and all the multiplied results are added.

For example, the elements of the first row (#1) of the A matrix are multiplied by each element of the first column (&1) of the B matrix. Here, as an example, it is assumed that k is 16, and if the matrix operator is provided with 16 processing elements (hereinafter referred to as PE), the 16 elements of the first row (#1) of the A matrix and the B matrix are A multiplication operation may be simultaneously performed on 16 elements of the first column &1 in parallel. That is, only one parallel operation is performed for multiplication of the elements of the first row (#1) of the A matrix and the elements of the first column (&1) of the B matrix.

However, the sum of 16 multiplication values obtained by subsequent inter-element multiplication is not calculated by one operation. In general, an arithmetic element such as the process element PE is configured to receive two inputs and perform a multiplication or addition operation. Accordingly, as shown in FIG. 3 , the addition operation is first performed by selecting 16 multiplication values by two, and the addition operation must be repeatedly performed by selecting two additional values for the addition operation. This means that four addition operations have to be repeatedly performed for 16 multiplication values, and as a result, the operation time of the addition operation on the multiplication result is very long compared to the inter-element multiplication operation.

In addition, since the result of multiplication between elements must be added, multiplication and addition between elements are sequentially performed. That is, the multiplication operation and the addition operation must be performed separately. Accordingly, as shown in FIG. 3 , a total of 5 operations are required for multiplication between 16 elements.

And this is an operation for obtaining a value for one element (eg, c _0,0 ) of the C matrix. Assuming that the number of operation processing lanes including 16 process elements PE is m, , and C for the entire matrix, since the number of times proportional to the size of the A matrix and the B matrix is to be performed, as a result, n × 5 operations are required.

Therefore, it is very important to reduce the time required for the addition operation in order to accelerate the operation speed of the matrix.

4 shows a schematic structure of a matrix operator according to an embodiment of the present invention, FIG. 5 shows a detailed configuration of an arithmetic processing lane of FIG. 4 , and FIG. 6 shows a detailed configuration of the process element of FIG. 5 .

4 to 6 , the matrix operator 100 according to the present embodiment will be described. The matrix operator 100 includes an operation control unit 110 , a first buffer unit 120 , and a second buffer unit 130 . and a calculator 140 , and as described above, may be used as a module of an artificial neural network.

The operation control unit 110 receives a plurality of matrices on which operations are to be performed in each layer of the artificial neural network. Here, the plurality of matrices to be calculated may be at least one feature map (or input image) applied to a layer and at least one kernel assigned to each layer.

The operation control unit 110 selects two matrices on which an operation is to be performed from among a plurality of applied matrices, and transmits the selected two matrices to the first buffer unit 120 and the second buffer unit 130 together with an operation command. do. At this time, the first buffer unit 120 applies the matrix A, which is a multiplicand matrix for at least one feature map applied to the layer of the artificial neural network, to the second buffer unit 130 , and the second buffer unit 130 applies the multiplier to the kernel specified in the layer of the artificial neural network. Apply the matrix B, which is a matrix.

In addition, the operation control unit 110 may receive a matrix operation result from the operation unit 140 and transmit it to a memory (not shown) and store it.

The reason that the operation control unit 110 applies the selected matrix together with the operation command is to select an element of each matrix and perform a matrix multiplication operation based on the matrix multiplication algorithm according to the present embodiment to be described later.

The first buffer unit 120 selects an element in units of columns from the matrix A applied from the operation control unit 110 according to an operation command and transmits it to the operation unit 140 . In addition, the second buffer unit 130 selects an element in units of rows from the B matrix applied according to the operation command and transmits it to the operation unit 140 .

The calculation unit 140 may include a plurality of calculation processing lanes SIMDL. In addition, each of the plurality of arithmetic processing lanes SIMDL may include a plurality of process elements PE and a SIMD unit SIMDU, as shown in FIG. 5 .

Recently, in order to increase computational efficiency, it is common for matrix operators to use a SIMD (Single Instruction Multiple Data) technique so that complex operations can be batch-processed with a single instruction. The SIMD technique is a method in which a plurality of process elements (PEs) apply the same (or similar) operation to a plurality of data and simultaneously process it, and is a technology mainly used in a vector processor.

In the SIMD technique, in order to maximize instruction efficiency, multiple instruction sets that can process multiple data with a single instruction are stored. In addition, each of the stored instruction sets uses data level parallelism (DLP) for a plurality of process elements (PE) to simultaneously perform operations in parallel. That is, the SIMD unit SIMDU causes the first and second buffer units 120 and 130 to perform the same operation in which a plurality of process elements PE are assigned to elements applied in units of rows or columns in parallel.

Here, the SIMD unit (SIMDU) may be implemented as hardware in the operation unit 140 or may be implemented as software specifying an operation performed by the operation unit 140 . Also, in some cases, it may be implemented in the operation control unit 110 .

Each of the plurality of process elements PE receives from the first and second buffer units 120 and 130, elements to be calculated among the elements a and b of the A matrix and the B matrix, and performs a multiplication or addition operation. do. In addition, each of the plurality of process elements PE may be implemented as a multiply-accumulate operator (MAC).

Referring to FIG. 6 , each of the plurality of process elements PE may include a multiplier MUL, an adder ADD, and an accumulation register ACC.

The multiplier MUL multiplies the element (a) of the A matrix applied from the first buffer unit 120 and the element (b) of the B matrix applied from the second buffer unit 130 and outputs it to the adder ADD. . The adder ADD receives and adds the output value of the multiplier MUL and the previously calculated accumulated subtotal stored in the accumulation register ACC to update the accumulated subtotal. The accumulation register ACC stores the updated accumulated subtotal output from the adder ADD.

7 illustrates a matrix multiplication operation algorithm according to an embodiment of the present invention.

Hereinafter, an algorithm for multiplying the matrix of FIG. 7 will be described with reference to FIGS. 4 to 6 .

In a general matrix multiplication operation, as shown in FIG. 2 , elements are selected in units of columns (&1, &2, ..., &k) from matrix A, which is a multiplicand matrix, and column units (&1, &2, ..., &n) was selected, the corresponding elements among the selected elements were multiplied with each other, and then the multiplication operation was performed by adding them all together.

On the other hand, in the matrix multiplication operation method according to the present embodiment shown in FIG. 7, the first buffer 120 selects an element in a column unit (&1, &2, ..., &k) from the matrix A, which is a multiplicand matrix, The second buffer 130 selects an element in row units (#1, #2, ..., #k) from the matrix B, which is a multiplier matrix, and transmits it to the operation unit 140 .

Each of the plurality of operation processing lanes SIMDL of the operation unit 140 receives and multiplies corresponding elements from the A matrix and the B matrix, and accumulates and adds the multiplied results.

In particular, in this embodiment, each of the plurality of arithmetic processing lanes SIMDL includes one element among the elements selected by column units (&1, &2, ..., &k) in matrix A and row units (#1, #) in matrix B. Multiple elements selected by 2, ..., #k) are multiplied by each other.

For example, when the first column (&1) of the A matrix and the first row (#1) of the B matrix are selected, the first operation processing lane among the plurality of operation processing lanes SIMDL is the first column (&1) of the A matrix Apply the a element (a _0,0 ) of the first row of , and the b elements (b _0,0 , b _0,1 , ..., b _0,n ) of the first row (#1) of the B matrix and multiply each of the b elements (b _0,0 , b _0,1 , ..., b _0,n ) by the element a (a _0,0 ).

At this time, in each of the plurality of process elements PE of the first arithmetic processing lane, the multiplier MUL operates the a element (a _0,0 ) and the b elements (b _0,0 , b _0,1 , ..., b _{0, n} ), receives the corresponding one b element, multiplies it, and transfers it to the adder (ADD). Since there is no previously calculated multiplication result, that is, there is no accumulated value previously stored in the accumulation register ACC, the adder ADD transfers the output of the multiplier MUL to the accumulation register ACC as it is and stores it.

That is, the first arithmetic processing lane includes the elements (a _0,0 ) of the first row and first column of the A matrix and the elements (b _0,0 , b _0,1 , .. ., b _0,n ) with the element value (c ⁰ _0,0 , c ⁰ _0,1 , ..., c ⁰ ) of the first row (#1) of the first accumulation matrix (C ⁰ ) _0,n ). And the obtained element values (c ⁰ _0,0 , c ⁰ _0,1 , ..., c ⁰ _0,n ) of the first row #1 are stored in the accumulation register ACC of each process element PE. is saved

On the other hand, the second arithmetic processing lane is an element (a _1,0 ) of the second row of the first column (&1) of the A matrix and the b elements (b _0,0 ) of the first row (#1) of the B matrix. b _0,1 , ..., b _0,n ) is applied, and element a (a _1,0 ) is replaced with elements b (b _0,0 , b _0,1 , ..., b _0,n ) Multiply each to obtain and store the element values (c ⁰ _1,0 , c ⁰ _1,1 , ..., c ⁰ _1,n ) of the second row (#2) of the first cumulative matrix (C ⁰ ) do.

In this way, the mth arithmetic processing lane is an element a (a _m,0 ) of the mth row of the first column (&1) of the A matrix and the b elements (b ₀ ) of the first row (#1) of the B matrix _,0 , b _0,1 , ..., b _0,n ) to multiply the element value (c ⁰ _m,0 , c ⁰ _m ) of the mth row (#m) of the first cumulative matrix (C ⁰ ) ₁ , ..., c ⁰ _m,n ) are acquired and stored.

That is, the multiplication of all elements of the first column (&1) of the A matrix and all the elements of the first row (#1) of the B matrix by the plurality of operation processing lanes SIML of the operation unit 140 is performed in one operation. are carried out at the same time

Thereafter, the first buffer 120 stores the a elements (a _0,1 , a _1,1 , ..., a _m,1 ) of the second column (&2) of the A matrix into a plurality of arithmetic processing lanes ( SIMDL), the second buffer 130 transmits the b elements (b _1,0 , b _1,1 , ..., b ₁ ) of the second row (#2) of the B matrix to the corresponding operation processing lane. _{, n} ) to each of the multiple computational processing lanes (SIMDL).

Accordingly, in the process element PE of each operation processing lane SIMDL, one a element (a _0,1 , a _1,1 , ..., a _m of the second column &2 to which the multiplier MUL is applied) _,1 ) and the corresponding b elements among the b elements (b _1,0 , b _1,1 , ..., b _1,n ) of the second row (#2) are multiplied by the adder (ADD) and the multiplier ( MUL), the accumulated values (c ⁰ _0,0 , c ⁰ _0,1 , ..., c ⁰ _0,n ) previously obtained and stored in the accumulation register (ACC) are received and added, 2 Acquired as the element value (c ¹ _0,0 , c ¹ _0,1 , ..., c ¹ _0,n ) of the first row (#1) of the cumulative matrix (C ¹ ), and the obtained element value ( c ¹ _0,0 , c ¹ _0,1 , ..., c ¹ _0,n ) is again stored in the accumulation register (ACC).

Similarly, the second arithmetic processing lane includes the elements (a _1,1 ) of the second row of the second column (&2) of the A matrix and the elements (b _1,0 , b) of the second row (#2) of the B matrix. _1,0 , ..., b _1,n ) is applied, and an element a (a _1,1 ) is added to each of the elements (b _1,0 , b _1,0 , ..., b _1,n ) By multiplying and adding the multiplication result with the accumulated values (c ⁰ _1,0 , c ⁰ _1,1 , ..., c ⁰ _1,n ) stored in the accumulation register (ACC), the second accumulation matrix (C ¹ ) It is obtained and stored as element values (c ¹ _1,0 , c ¹ _1,1 , ..., c ¹ _1,n ) of the second row (#2).

And the m th operation processing lane is an element a (a _m,0 ) of the mth row of the second column (&2) of the A matrix and the b elements (b _1,0 ) of the second row (#2) of the B matrix a second cumulative matrix by multiplying b _1,0 , ..., b _1,n ) and adding the cumulative value (c ⁰ _m,0 , c ⁰ _m,1 , ..., c ⁰ _m,n ) It is obtained and stored as element values (c ¹ _m,0 , c ¹ _m,1 , ..., c ¹ _m,n ) of the mth row (#m) of (C ¹ ).

In this way, the operation unit 140 sequentially receives the elements up to the k-th column (&k) of the A matrix and the k-th row (#k) of the B matrix, multiplies the applied elements, and adds them to the previously calculated cumulative value to finally to obtain the k-th cumulative matrix (C ^k ), which is the matrix multiplication result of the A matrix and the B matrix.

If the above-described matrix multiplication algorithm is described again in terms of each of the plurality of process elements PE of the plurality of arithmetic processing lanes SIMDL, each of the plurality of process elements PE of the pth SIDM lane corresponds to the corresponding first in the A matrix. Each of the a elements of p row (a _p,0 , a _p,1 , ..., a _p,k ) is assigned to the b elements of the corresponding pth column in the B matrix (b _0,p , b _1,p , _. ^{_ _} _{_} ^_ _{_ ,0} , ..., c ^k _p,n ).

In addition, the calculation method of each of these process elements PE is the same as the process of calculating one element (#, &) of the C matrix in the general matrix multiplication operation shown in FIG. 2 . However, in the case of the algorithm of FIG. 2, the operation unit receives the elements of the A matrix and the B matrix required to calculate one element (#, &) of the C matrix at the same time, performs multiplication, and adds again to the result of the multiplication Since the operation has to be repeatedly performed, as shown in FIG. 3 , whenever each element (#, &) of the C matrix is obtained, the addition operation has to be performed a plurality of times after one multiplication operation.

However, since the matrix multiplication algorithm according to the present embodiment shown in FIG. 7 acquires sequentially accumulated cumulative matrices (C ⁰ , C ¹ , ..., C ^k ), only k multiplication operations and k addition operations A A C matrix, which is the result of multiplication between the matrix and the B matrix, can be obtained.

In particular, in each of the plurality of process elements PE of the plurality of arithmetic processing lanes SIMDL, the multiplier MUL generates a multiplication result output by the adder ADD from the previous multiplier MUL and the accumulated value stored in the accumulation register ACC. While adding , the multiplication operation may be performed by receiving an element a and an element b to be multiplied next. That is, the multiplier (MUL) and the adder (ADD) may perform simultaneous operation according to the pipeline technique.

This means that it takes k+1 computation time, rather than 2k computation time, to obtain the C matrix, which is the result of multiplication between the A matrix and the B matrix.

That is, since the time for the addition operation is hardly required in the matrix multiplication operation, the matrix multiplication operation time can be greatly reduced.

8 shows a matrix operation method according to an embodiment of the present invention.

Referring to FIGS. 4 to 7 , the matrix calculation method of FIG. 8 is described. First, two matrices to be multiplied are obtained ( S10 ). One of the two matrices is an m × k multiplicand matrix, called A matrix, and the other is a k × n multiplier matrix, which may be referred to as a B matrix. Here, matrix A may be all or part of a feature map (or input image) input to each layer of the artificial neural network, and matrix B may be all or part of a kernel specified for each layer. there is.

When two matrices to be calculated are obtained, the i-th column is selected from the matrix A, which is the multiplicand matrix (S20). Then, the i-th row is selected from the B matrix, which is a multiplier matrix (S30). Here, the initial value of i is 1, and first, the first column of the A matrix and the first row of the B matrix are selected.

And each element (a _0,i , a _1,i , ..., a _m,i ) of the i-th column of the selected A matrix is added to all the elements (b _i,0 , b _{i, 1} , ..., b _i,n ) to obtain m × n multiplication results (S40).

When m × n multiplication results are obtained, the obtained multiplication results are added to the previously obtained accumulated values (S50). If there is no previously obtained accumulated value, the multiplication result is obtained as an initial accumulated value, and if there is a previously obtained accumulated value, the result of adding the obtained multiplication result to the previously obtained accumulated value is stored as an updated accumulated value ( S60).

Then, it is determined whether i is smaller than k, which is the number of columns of the A matrix or the number of rows of the B matrix (S70). If i is less than k (i < k), i is changed to i+1 (S80). Accordingly, the next column and the next row previously selected from the A matrix and the B matrix are selected (S20).

However, if i is greater than or equal to k, the accumulated matrix composed of the stored accumulated values of m × n is output as the C matrix, which is the matrix multiplication result of the A matrix and the B matrix (S90).

The method according to the present invention may be implemented as a computer program stored in a medium for execution by a computer. Here, the computer-readable medium may be any available medium that can be accessed by a computer, and may include all computer storage media. Computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, and read dedicated memory), RAM (Random Access Memory), CD (Compact Disk)-ROM, DVD (Digital Video Disk)-ROM, magnetic tape, floppy disk, optical data storage, and the like.

Although the present invention has been described with reference to the embodiment shown in the drawings, which is only exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom.

Accordingly, the true technical protection scope of the present invention should be defined by the technical spirit of the appended claims.

110: arithmetic control unit 120: first buffer unit
130: second buffer unit 140: operation unit
SIMDL: arithmetic processing lane PE: process element
SIMDU: SIMD unit MUL: multiplier
ADD: Adder ACC: Accumulation Register

Claims (10)

a first buffer for receiving and storing a first matrix that is a multiplicand matrix;
a second buffer for receiving and storing a second matrix that is a multiplier matrix multiplied by the first matrix; and
receiving a plurality of elements sequentially selected in units of columns from the first matrix, receiving a plurality of elements sequentially selected in units of rows from the second matrix in correspondence to columns selected in the first matrix, Each element of a column is multiplied by all elements of a row selected in the second matrix, and the result of the multiplication operation between the sequentially selected column of the first matrix and the row of the second matrix is cumulatively added to the first matrix and the second matrix Including an operator for obtaining a result matrix that is a matrix multiplication operation result of
The calculation unit
Each of the elements of the column selected in the first matrix is applied and multiplied by a corresponding one element and all elements of the row selected in the second matrix, and the result of inter-element multiplication is added to the accumulated value of the previous multiplication result. a plurality of arithmetic processing lanes for obtaining an element of a row of a cumulative matrix;
Each of the plurality of arithmetic processing lanes is
While adding the result of inter-element multiplication to the cumulative added value of the previous multiplication result, the elements of the column in the first matrix and all the elements of the row in the second matrix are applied according to a predetermined sequence to perform a multiplication operation do,
the second buffer
When the i-th column of the first matrix (where i is a natural number) is selected from the first buffer, the matrix operator selects the i-th row of the second matrix.
delete delete 2. The method of claim 1, wherein each of the plurality of computational processing lanes comprises:
comprising a plurality of process elements;
Each of the plurality of process elements is
a multiplier for receiving a corresponding one element from the selected column of the first matrix and a corresponding one element from among a plurality of elements from the selected row of the second matrix for multiplication;
an adder for updating the accumulated value by adding the multiplication result output from the multiplier to the accumulated value obtained by adding the multiplication result of the previously applied element; and
and an accumulation register configured to store the accumulated value updated in the adder. delete The method of claim 1, wherein the matrix operator
It is implemented as an artificial neural network module for performing a specified operation on at least one layer among a plurality of layers of the artificial neural network,
The first matrix is a feature map applied to the at least one layer, and the second matrix is a kernel predetermined to the at least one layer. receiving and storing a first matrix that is a multiplicand matrix and a second matrix that is a multiplier matrix multiplied by the first matrix;
receiving a plurality of elements sequentially selected in units of columns in the first matrix and a plurality of elements sequentially selected in units of rows in the second matrix corresponding to columns selected in the first matrix;
multiplying each element of a column selected in the first matrix by all elements of a row selected in the second matrix; and
Accumulating the result of the multiplication operation between the sequentially selected columns of the first matrix and the rows of the second matrix to obtain a result matrix that is the result of the matrix multiplication operation of the first matrix and the second matrix,
The step of obtaining the result matrix is
The element of the partial accumulation matrix is obtained by adding the inter-element multiplication result obtained in the step of multiplying with all the elements to the accumulated value to which the previous corresponding inter-element multiplication result is accumulated,
Each of the plurality of arithmetic processing lanes is
While adding the result of inter-element multiplication to the cumulative added value of the previous multiplication result, the elements of the column in the first matrix and all the elements of the row in the second matrix are applied according to a predetermined sequence to perform a multiplication operation perform,
The step of receiving the selected plurality of elements is
When the i-th column of the first matrix (where i is a natural number) is selected, a matrix calculation method in which a plurality of elements of the i-th row of the second matrix are applied.

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