KR102303756B1 - Device and system including adaptive repair circuit - Google Patents

Abstract

The device or subsystem includes an internal circuit that performs a unique function, an input/output terminal unit, and a repair circuit. The input/output terminal unit includes a plurality of normal input/output terminals connected to an external device through a plurality of normal signal paths and at least one repair input/output terminal selectively connected to the external device through at least one repair signal path. The repair circuit repairs a bad signal path included in the normal signal paths based on a mode signal indicating whether the repair signal path is used or not and a bad information signal indicating bad information of the normal signal paths. Systems employing different repair methods including the adaptive repair circuit can be efficiently repaired, and design and manufacturing costs of the system can be reduced by supporting different repair methods using the same device configuration.

Description

DEVICE AND SYSTEM INCLUDING ADAPTIVE REPAIR CIRCUIT

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to devices and systems including adaptive repair circuits.

Recent high-performance systems require a rescue mechanism, that is, a repair mechanism, for components that are likely to fail. Among the many components in a system, there is a high probability that the interconnects between devices or subsystems will fail, and the failure of these interconnects can bring down the entire system. A software recovery mechanism may be applied to repair a defect in the interconnection device, but the software recovery mechanism is usually performed by reconfiguring hardware during a reboot process and cannot be a satisfactory solution.

One device may be connected to external devices supporting different repair methods through an interconnection device. In this case, although the unique functions performed by the device are the same, there is a problem in that each of the devices has to be implemented separately as a configuration for supporting each repair method due to a difference in the repair method.

SUMMARY OF THE INVENTION An object of the present invention is to provide an apparatus including an adaptive repair circuit capable of supporting different repair schemes.

Another object of the present invention is to provide a system including at least one subsystem including an adaptive repair circuit capable of supporting different repair schemes.

Another object of the present invention is to provide a stacked memory chip including an adaptive repair circuit capable of supporting different repair methods.

In order to achieve the above object, an apparatus according to embodiments of the present invention includes an internal circuit performing a unique function, an input/output terminal unit, and a repair circuit. The input/output terminal unit includes a plurality of normal input/output terminals connected to an external device through a plurality of normal signal paths and at least one repair input/output terminal selectively connected to the external device through at least one repair signal path. The repair circuit repairs a bad signal path included in the normal signal paths based on a mode signal indicating whether the repair signal path is used or not and a bad information signal indicating bad information of the normal signal paths.

In an embodiment, the repair circuit may selectively operate in one of a first repair mode not using the repair input/output terminal and a second repair mode using the repair input/output terminal based on the mode signal.

In an embodiment, the normal input/output terminals are main input/output terminals for transmitting main signals for a main operation of the internal circuit and at least one sub input/output terminal for transmitting a sub signal for a sub operation of the internal circuit may include.

In an embodiment, in the first repair mode, the repair circuit may repair a bad input/output terminal corresponding to the bad signal path among the normal input/output terminals using the sub input/output terminal.

In an embodiment, the internal circuit may stop the sub-operation in the first repair mode.

In an embodiment, in the second repair mode, the repair circuit may repair a defective input/output terminal corresponding to the defective signal path among the normal input/output terminals using the repair input/output terminal.

In an embodiment, the device may further include an initialization circuit connected to the repair input/output terminal and configured to apply an initialization voltage to the repair input/output terminal in response to the mode signal.

In an embodiment, the normal input/output terminals may be grouped into a plurality of groups, and at least one repair input/output terminal may be independently allocated to each of the groups.

In an embodiment, the normal input/output terminals may be grouped into a plurality of groups, and at least one repair input/output terminal may be commonly allocated to at least two of the groups.

In an embodiment, the repair circuit replaces a bad input/output terminal corresponding to the bad signal path among the normal input/output terminals with the normal input/output terminal adjacent to the bad input/output terminal or the repair input/output terminal adjacent to the bad input/output terminal A shifting repair operation may be performed.

In an embodiment, the repair circuit replaces a bad input/output terminal corresponding to the bad signal path among the normal input/output terminals with a sub input/output terminal corresponding to one of the normal input/output terminals or the repair input/output terminal. action can be performed.

In an embodiment, the device may further include a fuse circuit that is selectively programmed according to a repair method of the external device to provide the mode signal.

In an embodiment, the mode signal may be generated based on information stored in a mode register set.

In an embodiment, the repair circuit includes a repair control unit generating a plurality of path selection signals based on the mode signal and the failure information signal, and between the input/output terminal unit and the internal circuit in response to the path selection signals. It may include a path conversion circuit that controls the connection.

In one embodiment, the path conversion circuit, in response to each of the path selection signals, each of the input/output node of the internal circuit and a plurality of each for controlling the electrical connection between the two or more input/output terminals of the input/output terminal unit Conversion units may be included.

In an embodiment, each of the conversion units outputs a received signal input from one of two or more input/output terminals of the input/output terminal unit to each input/output node of the internal circuit in response to each of the path selection signals It may include a receiver that

In an embodiment, each of the conversion units outputs a transmission signal input from each input/output node of the internal circuit to one of two or more input/output terminals of the input/output terminal unit in response to each of the path selection signals It may include a transmitter.

In an embodiment, each of the conversion units outputs a received signal input from one of two or more input/output terminals of the input/output terminal unit to each input/output node of the internal circuit in response to each of the path selection signals and a transmitter for outputting a transmission signal input from each input/output node of the internal circuit to one of two or more input/output terminals of the input/output terminal unit in response to each of the selection signals.

In an embodiment, the normal input/output terminals are main input/output terminals for transmitting main signals for a main operation of the internal circuit and at least one sub input/output terminal for transmitting a sub signal for a sub operation of the internal circuit may include.

In an embodiment, each of the main conversion units corresponding to the main input/output terminals among the conversion units is connected to a corresponding normal input/output terminal and an adjacent normal input/output terminal among the normal input/output terminals, and one of the conversion units The sub conversion unit corresponding to the sub input/output terminal may be connected to the sub input/output terminal and the repair input/output terminal.

In an embodiment, the repair controller is configured to inactivate all of the path selection signals to a first logic level when the bad signal path is not included in the normal signal paths, and to provide the bad signal path to the normal signal paths. When is included, it is possible to activate the last path selection signal from the path selection signal corresponding to the bad signal path to the second logic level.

In an embodiment, a sub conversion unit corresponding to the sub input/output terminal among the conversion units may block an electrical connection between the internal circuit and the sub conversion unit in response to a block control signal.

In an embodiment, a main conversion unit corresponding to each of the main input/output terminals among the conversion units is connected to a corresponding normal input/output terminal, the sub input/output terminal, and the repair input/output terminal among the normal input/output terminals, Among the conversion units, a sub conversion unit corresponding to the sub input/output terminal may be connected to the sub input/output terminal and the repair input/output terminal.

In an embodiment, the repair controller is configured to inactivate all of the path selection signals to a first logic level when the bad signal path is not included in the normal signal paths, and to provide the bad signal path to the normal signal paths. When is included, only the path selection signal corresponding to the bad signal path may be activated to the second logic level.

In order to achieve the above object, a system according to embodiments of the present invention includes a first subsystem, a second subsystem, and a plurality of normal signal paths connecting the first subsystem and the second subsystem. . The first subsystem is selectively configured with the second subsystem through an internal circuit performing a unique function, a plurality of normal input/output terminals connected to the second subsystem through the normal signal paths, and at least one repair signal path. An input/output terminal unit including at least one repair input/output terminal connected to and a repair circuit for repairing a bad signal path.

In one embodiment, when the second subsystem does not support the use of the repair signal path, the system does not include the repair signal path, and the repair circuit of the first subsystem connects the repair terminal. When operating in an unused first repair mode, and the second subsystem supports the use of the repair signal path, the system further includes the repair signal path, wherein the repair circuit of the first subsystem comprises: It may operate in a second repair mode using the repair terminal.

In an embodiment, one of the first subsystem and the second subsystem may be a memory device, and the other may be a memory controller that controls the memory device.

In an embodiment, the memory controller may include a built-in self-test circuit that provides the failure information.

In one embodiment, each of the normal signal paths and the repair signal path may include at least one of a line of a signal bus, a through-silicon via of a semiconductor die, a line of an interposer, a conductive bump, and a pad. .

In order to achieve the above object, an apparatus according to embodiments of the present invention includes a base substrate and a plurality of semiconductor dies stacked on the base substrate. Each of the semiconductor dies includes an internal circuit performing a unique function, a plurality of normal input/output terminals connected to an external processor through normal signal paths, and at least one selectively connected to the processor through at least one repair signal path. Repair the bad signal path included in the normal signal paths based on an input/output terminal unit including a repair input/output terminal of A repair circuit is included.

The apparatus and system according to the embodiments of the present invention can efficiently repair systems employing different repair methods, including the adaptive repair circuit.

In addition, the device and the system according to the embodiments of the present invention support different repair methods using the same device configuration, thereby reducing design and manufacturing costs of the system.

1 is a block diagram illustrating an apparatus including a repair circuit according to embodiments of the present invention.
FIG. 2 is a block diagram illustrating a repair circuit included in the apparatus of FIG. 1 .
3 is a block diagram illustrating a path conversion circuit performing a shifting repair operation according to embodiments of the present invention.
4A is a diagram illustrating an embodiment of a path conversion circuit that performs a shifting repair operation and a reception operation.
4B is a diagram illustrating an embodiment of a path conversion circuit that performs a shifting repair operation and a transmission operation.
4C is a diagram illustrating an embodiment of a path conversion circuit that performs a shifting repair operation and a transmission/reception operation.
5 is a diagram illustrating an embodiment of a sub conversion unit included in the path conversion circuit of FIG. 3 .
FIG. 6 is a diagram for explaining operations of conversion units included in the path conversion circuit of FIG. 3 .
7 is a block diagram illustrating a system including the path conversion circuit of FIG. 3 and not supporting a repair signal path.
8A and 8B are diagrams for explaining a repair operation of the system of FIG. 7 .
9 is a block diagram illustrating a system including the path conversion circuit of FIG. 3 and supporting a repair signal path.
10A and 10B are diagrams for explaining a repair operation of the system of FIG. 9 .
11 is a diagram illustrating an embodiment of a repair control unit for providing path selection signals to the path conversion circuit of FIG. 3 .
FIG. 12 is a view for explaining the overall operation of the repair circuit including the path conversion circuit of FIG. 3 .
13 is a block diagram illustrating a path conversion circuit performing a shifting repair operation according to embodiments of the present invention.
14 is a block diagram illustrating a path conversion circuit performing a multiplexing repair operation according to embodiments of the present invention.
15A is a diagram illustrating an embodiment of a path conversion circuit that performs a multiplexing repair operation and a reception operation.
15B is a diagram illustrating an embodiment of a path conversion circuit that performs a multiplexing repair operation and a transmission operation.
15C is a diagram illustrating an embodiment of a path conversion circuit that performs a multiplexing repair operation and a transmission/reception operation.
16 is a diagram illustrating an embodiment of a sub conversion unit included in the path conversion circuit of FIG. 14 .
FIG. 17 is a diagram for explaining operations of conversion units included in the path conversion circuit of FIG. 14 .
18 is a block diagram illustrating a system including the path conversion circuit of FIG. 14 and not supporting a repair signal path.
19A and 19B are diagrams for explaining a repair operation of the system of FIG. 18 .
20 is a block diagram illustrating a system including the path conversion circuit of FIG. 14 and supporting a repair signal path.
21A and 21B are diagrams for explaining a repair operation of the system of FIG. 20 .
22 is a diagram illustrating an embodiment of a repair control unit for providing path selection signals to the path conversion circuit of FIG. 14 .
FIG. 23 is a view for explaining the overall operation of the repair circuit including the path conversion circuit of FIG. 14 .
24 is a block diagram illustrating a path conversion circuit performing a shifting repair operation according to embodiments of the present invention.
25 is a block diagram illustrating a path conversion circuit performing a shifting repair operation according to embodiments of the present invention.
26 is a block diagram illustrating a system including the path conversion circuit of FIG. 25 and not supporting a repair signal path.
27A and 27B are diagrams for explaining a repair operation of the system of FIG. 26 .
28 is a block diagram illustrating a system including the path conversion circuit of FIG. 25 and supporting a repair signal path.
29A and 29B are diagrams for explaining a repair operation of the system of FIG. 28 .
30 is a block diagram illustrating a path conversion circuit performing a shifting repair operation according to embodiments of the present invention.
31 is a block diagram illustrating a system including the path conversion circuit of FIG. 30 and not supporting a repair signal path.
32A and 32B are diagrams for explaining a repair operation of the system of FIG. 31 .
33 is a block diagram illustrating a system including the path conversion circuit of FIG. 30 and supporting a repair signal path.
34A and 34B are diagrams for explaining a repair operation of the system of FIG. 33 .
35 is a block diagram illustrating a memory system including a repair circuit according to embodiments of the present invention.
36 is a block diagram illustrating an example of an internal configuration of a memory device included in the memory system of FIG. 35 .
37 is a diagram illustrating an example of a fuse circuit providing a mode signal.
38 is a diagram illustrating a stacked memory chip according to embodiments of the present invention.
39 is a diagram illustrating a system according to embodiments of the present invention.
40 and 41 are diagrams illustrating memory modules according to embodiments of the present invention.
42 is a diagram illustrating an example in which memory modules according to embodiments of the present invention are connected to a memory controller.
43 is a diagram illustrating a structure of a stacked memory device according to an embodiment of the present invention.
44 is a block diagram illustrating a memory system according to embodiments of the present invention.
45 is a block diagram illustrating a mobile system according to embodiments of the present invention.
46 is a block diagram illustrating a computing system according to embodiments of the present invention.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are only exemplified for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention may be embodied in various forms. It is not to be construed as being limited to the embodiments described in .

Since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component.

When a component is referred to as being “connected” or “connected” to another component, it is understood that the other component may be directly connected or connected to the other component, but other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that no other element is present in the middle. Other expressions describing the relationship between elements, such as "between" and "immediately between" or "neighboring to" and "directly adjacent to", should be interpreted similarly.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as “comprise” or “have” are intended to designate that the described feature, number, step, operation, component, part, or combination thereof exists, and includes one or more other features or numbers. , it is to be understood that it does not preclude the possibility of the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as meanings consistent with the context of the related art, and unless explicitly defined in the present application, they are not to be interpreted in an ideal or excessively formal meaning. .

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repeated descriptions of the same components are omitted.

1 is a block diagram illustrating an apparatus including a repair circuit according to embodiments of the present invention.

Referring to FIG. 1 , the device 10 includes an internal circuit 20 , an input/output terminal unit 30 , and a repair circuit 100 .

The internal circuit 20 performs the intrinsic function of the device 10 . For example, when the device 10 is a memory device, the internal circuit 20 includes a memory cell array and circuits for operating the same, and performs main operations such as a data write operation and a data read operation and other sub-operations. can be done For another example, when the device 10 is a display device, the internal circuit 20 may include a pixel array and circuits for operating the same to perform main operations such as an image display operation and other sub-operations. . The internal circuit 20 may have various configurations according to a unique function to be performed by the device 10 .

The input/output terminal unit 30 includes a plurality of normal input/output terminals TN1 to TNk connected to an external device through a plurality of normal signal paths and at least one repair selectively connected to the external device through at least one repair signal path. Includes input/output terminals TR1 to TRs. The normal signal paths are for exchanging signals for performing an intrinsic function of the device 10 with the external device, and the normal input/output terminals TN1 to TNk are essentially connected to the normal signal paths. On the other hand, the repair signal path may be omitted according to the repair method of the external device, and the repair input/output terminals TR1 to TRs may be selectively connected to the repair signal paths.

The repair circuit 100 is configured to generate a bad signal path included in the normal signal paths based on a mode signal MD indicating whether the repair signal path is used or not and a bad information signal FLI indicating bad information of the normal signal paths. repair the

1 , the normal input/output terminals TN1 to TNk may respectively correspond to the input/output nodes ND1 to NDk of the internal circuit 20 . That is, the first normal input/output terminal TN1 corresponds to the first input/output node ND1 of the internal circuit 20 , and the second normal input/output terminal TN2 is connected to the first input/output node ND2 of the internal circuit 20 . Correspondingly, in this way, the kth normal input/output terminal TNk may correspond to the kth input/output node ND1 of the internal circuit 20 . The repair circuit 100 connects each input/output node NDi (i=1 to k) of the internal circuit 20 to a corresponding normal input/output terminal TNi when the normal signal paths do not include a bad signal path. It can be electrically connected. Meanwhile, the repair circuit 100 repairs the bad signal path when the normal signal paths include the bad signal path, so that the input/output nodes ND1 to NDk and the input/output terminals TN1 to TNk of the internal circuit 20 are repaired. , can change the electrical connection between TR1~TRs).

The repair circuit 100 is one of a first repair mode in which the repair input/output terminals TR1 to TRs are not used and a second repair mode in which the repair input/output terminals TR1 to TRs are used based on the mode signal MD. can be operated selectively. As such, the apparatus 10 according to embodiments of the present invention includes the adaptive repair circuit 100 capable of operating in different repair modes, and can efficiently repair systems employing different repair methods. . In addition, the device 10 according to embodiments of the present invention supports different repair methods using the same device configuration, thereby reducing system design and manufacturing costs.

FIG. 2 is a block diagram illustrating a repair circuit included in the apparatus of FIG. 1 .

Referring to FIG. 2 , the repair circuit 100 may include a repair controller 200 and a path conversion circuit 300 .

The repair control unit 200 may generate the path control signal PCON based on the mode signal MD and the failure information signal FLI. The path control signal PCON may include a plurality of path selection signals PSL1 to PSLk and a block control signal BLK respectively provided to the conversion units CU1 to CUk, as will be described later.

The path conversion circuit 300 may control the connection between the input/output terminal unit 30 and the internal circuit 20 of FIG. 1 in response to the path selection signals PSL1 to PSLk. As shown in FIG. 2 , the path conversion circuit 300 may include a plurality of conversion units CU1 to CUk. Each conversion unit (CUi) (i = 1 ~ k) in response to each path selection signal (PSLi) each input/output node (NDi) of the internal circuit 20 and two or more of the input/output terminal unit (30) Electrical connections between the input/output terminals may be individually controlled.

The repair circuit 100 is one of a first repair mode in which the repair input/output terminals TR1 to TRs are not used and a second repair mode in which the repair input/output terminals TR1 to TRs are used based on the mode signal MD. can be operated selectively. Meanwhile, the repair circuit 100 may be implemented to perform a shifting repair operation or a multiplexing repair operation. Hereinafter, embodiments of a repair circuit performing a shifting repair operation will be described with reference to FIGS. 3 to 13 , and embodiments of a repair circuit performing a multiplexing repair operation will be described with reference to FIGS. 14 to 24 .

3 is a block diagram illustrating a path conversion circuit performing a shifting repair operation according to embodiments of the present invention.

Referring to FIG. 3 , the path conversion circuit 301 responds to each of the path selection signals PSL1 , PSL2 , PSL3 , and PSL4 , respectively, and input/output nodes of the input/output nodes ND1 , ND2 , ND3 , and ND4 of the internal circuit. It may include a plurality of conversion units (CU1, CU2, CU3, CU4) (311, 312, 313, 314) for controlling the electrical connection between the two or more input/output terminals of the terminal unit 31, respectively. Although the first to fourth conversion units 311, 312, 313, and 314 are illustrated in FIG. 3 for convenience, the number of conversion units and input/output terminals may be variously changed.

As will be described later with reference to FIG. 7 , the normal input/output terminals TN1 , TN2 , TN3 , and TN4 are main input/output terminals for transmitting main signals for the main operation of the internal circuit 20 of FIG. 1 and the internal circuit At least one sub input/output terminal for transmitting a sub signal for the sub operation of (20) may be included. For example, in the configuration of FIG. 3 , the first, second, and third normal input/output terminals TN1 , TN2 , and TN3 may be main input/output terminals, and the fourth normal input/output terminal TN4 may be a sub input/output terminal.

Each of the main conversion units 311 , 312 , 313 corresponding to the main input/output terminals TN1 , TN2 , TN3 of the conversion units 311 , 312 , 313 , and 314 has normal input/output terminals TN1 , TN2 , TN3 , TN4) may be connected to a corresponding normal input/output terminal and an adjacent normal input/output terminal. That is, the first conversion unit 311 is connected to the first normal input/output terminal TN1 and the second normal input/output terminal TN2 , and the second conversion unit 312 is connected to the second normal input/output terminal TN2 and the third normal input/output terminal TN2 . It is connected to the input/output terminal TN3 , and the third conversion unit 313 may be connected to the third normal input/output terminal TN3 and the fourth normal input/output terminal TN4 .

Among the conversion units 311 , 312 , 313 , and 314 , the sub conversion unit 314 corresponding to the sub input/output terminal TN4 , that is, the fourth conversion unit 314 is a sub input/output terminal TN4 and a repair input/output terminal TR ) can be connected to

As will be described later with reference to FIGS. 11 and 12, the repair control unit 200 of FIG. 2 may control the logic levels of the path selection signals PSL1, PSL2, PSL3, and PSL4 to perform a shifting repair operation. Each of the conversion units 311 , 312 , 313 , and 314 may be selectively connected to one of the two input/output terminals according to the respective logic levels of the path selection signals PSL1 , PSL2 , PSL3 , and PSL4 . When the path selection signal PSLi is deactivated to the first logic level (eg, logic low level), the terminal '1' is selected so that the conversion unit CUi is connected to the corresponding input/output terminal, and the path selection signal ( When PSLi) is activated to a second logic level (eg, a logic high level), terminal '2' is selected so that the conversion unit CUi may be connected to an adjacent input/output terminal.

4A is a diagram illustrating an embodiment of a path conversion circuit that performs a shifting repair operation and a reception operation.

Referring to FIG. 4A , the path conversion circuit 301a may include a plurality of conversion units 311a, 312a, 313a, and 314a. FIG. 4A shows an embodiment in which the path conversion circuit 301a serves as a receiving interface, and each of the conversion units 311a, 312a, 313a, 314a transmits received signals from an external device to the internal circuit ( 20) and a receiver (RX) for forwarding. Each receiver RX receives a received signal input from one of two or more input/output terminals of the input/output terminal unit 31 in response to each of the path selection signals PSL1, PSL2, PSL3, and PSL4 internal circuit 20 output to each of the input/output nodes ND1, ND2, ND3, and ND4.

That is, the receiver of the first conversion unit 311a connects one of the first normal input/output terminal TN1 and the second normal input/output terminal TN2 to the second of the internal circuit 20 in response to the first path selection signal PSL1 . Electrically connected to the first input/output node ND1, and the receiver of the second conversion unit 312a responds to the second path selection signal PSL2 to the second normal input/output terminal TN2 and the third normal input/output terminal TN3 one of them is electrically connected to the second input/output node ND3 of the internal circuit 20 , and the receiver of the third conversion unit 313a responds to the third path selection signal PSL3 to the third normal input/output terminal TN3 ) and one of the fourth normal input/output terminals TN4 are electrically connected to the third input/output node ND2 of the internal circuit 20 , and the receiver of the fourth conversion unit 314a receives the fourth path selection signal PSL4 In response, one of the fourth normal input/output terminal TN4 and the repair input/output terminal TR may be electrically connected to the fourth input/output node ND4 of the internal circuit 20 .

4B is a diagram illustrating an embodiment of a path conversion circuit that performs a shifting repair operation and a transmission operation.

Referring to FIG. 4B , the path conversion circuit 301b may include a plurality of conversion units 311b, 312b, 313b, and 314b. 4B shows an embodiment in which the path conversion circuit 301b serves as a transmission interface, and each of the conversion units 311b, 312b, 313b, and 314b transmits the transmission signals from the internal circuit 20 of FIG. It may include a transmitter (TX) for transmitting to an external device. Each transmitter TX receives a transmission signal input from each of the input/output nodes ND1 , ND2 , ND3 , and ND4 of the internal circuit 20 in response to each of the path selection signals PSL1 , PSL2 , PSL3 , and PSL4 . may be output to one of two or more input/output terminals of the input/output terminal unit 31 .

That is, the transmitter of the first conversion unit 311b connects the first input/output node ND1 of the internal circuit 20 to the first normal input/output terminal TN1 and the second normal input/output terminal in response to the first path selection signal PSL1. electrically connected to one of the terminals TN2, and the transmitter of the second conversion unit 312b connects the second input/output node ND2 of the internal circuit 20 to a second normal in response to the second path selection signal PSL2 Electrically connected to one of the input/output terminal TN2 and the third normal input/output terminal TN3, the transmitter of the third conversion unit 313b responds to the third path selection signal PSL3 of the internal circuit 20 The 3 input/output node ND3 is electrically connected to one of the third normal input/output terminal TN3 and the fourth normal input/output terminal TN4, and the transmitter of the fourth conversion unit 314b transmits the fourth path selection signal PSL4. In response, the fourth input/output node ND4 of the internal circuit 20 may be electrically connected to one of the fourth normal input/output terminal TN4 and the repair input/output terminal TR.

4C is a diagram illustrating an embodiment of a path conversion circuit that performs a shifting repair operation and a transmission/reception operation.

Referring to FIG. 4C , the path conversion circuit 301c may include a plurality of conversion units 311c , 312c , 313c , and 314c . FIG. 4C shows an embodiment in which the path conversion circuit 301c serves as a transmit and receive interface, and each of the conversion units 311c, 312c, 313c, and 314c converts received signals from an external device into the inside of FIG. It may include a receiver RX for transmitting to the circuit 20 and a transmitter TX for transmitting transmission signals from the internal circuit 20 to an external device. As described with reference to FIG. 4A , each receiver RX receives an input from one of two or more input/output terminals of the input/output terminal 31 in response to each of the path selection signals PSL1, PSL2, PSL3, and PSL4. The received signal may be output to each of the input/output nodes ND1 , ND2 , ND3 , and ND4 of the internal circuit 20 . As described with reference to FIG. 4B , each transmitter TX receives input/output nodes ND1, ND2, ND3, and A transmission signal input from each of the ND4 may be output to one of two or more input/output terminals of the input/output terminal unit 31 .

5 is a diagram illustrating an embodiment of a sub conversion unit included in the path conversion circuit of FIG. 3 .

As will be described later with reference to FIG. 7 , the normal input/output terminals TN1 , TN2 , TN3 , and TN4 are main input/output terminals for transmitting main signals for the main operation of the internal circuit 20 of FIG. 1 and the internal circuit At least one sub input/output terminal for transmitting a sub signal for the sub operation of (20) may be included. For example, in the configuration of FIG. 3 , the first, second, and third normal input/output terminals TN1 , TN2 , and TN3 may be main input/output terminals, and the fourth normal input/output terminal TN4 may be a sub input/output terminal.

Referring to FIG. 5 , the fourth conversion unit CU4 corresponding to the sub input/output terminal TN4 may include a buffer unit BUF and a selection unit SEL.

The selection unit SEL responds to the fourth path selection signal PSL4 as described with reference to FIGS. 4A , 4B and 4C , the fourth input/output node ND4 and the input/output terminal unit 31 of the internal circuit 20 . and a receiver RX and/or a transmitter TX for controlling an electrical connection between the fourth normal input/output terminal TN4 and the repair input/output terminal TR. The buffer unit BUF may block an electrical connection between the fourth input/output node ND4 and the selection unit SEL in response to the block control signal BLK.

For example, when a sub-signal for the sub-operation is transmitted, the block control signal BLK is inactivated to a first logic level (eg, a logic low level L) and the buffer unit BUF is configured to generate a fourth The input/output node ND4 and the selection unit SEL may be electrically connected. On the other hand, when the sub-signal for the sub-operation is not transmitted, the block control signal BLK is activated to a second logic level (eg, a logic high level H) and the buffer unit BUF operates the fourth input/output. An electrical connection between the node ND4 and the selection unit SEL may be blocked.

As such, the sub conversion unit CU4 corresponding to the sub input/output terminal TN4 among the conversion units CU1, CU2, CU3, CU4 responds to the block control signal BLK with the internal circuit 20 and the sub conversion unit It is possible to break the electrical connection between (CU4).

FIG. 6 is a diagram for explaining operations of conversion units included in the path conversion circuit of FIG. 3 .

Referring to FIG. 6 , one of the terminals of the corresponding conversion unit CUi may be selected according to the logic level of the path selection signal PSLi. For example, when the path selection signal PSLi is inactivated to the first logic level (eg, the logic low level L), the terminal '1' is selected so that the conversion unit CUi is connected to the corresponding normal input/output terminal. It is connected to TNi, and when the path selection signal PSLi is activated to a second logic level (eg, logic high level H), the terminal '2' is selected so that the conversion unit CUi is connected to the adjacent normal It may be connected to the input/output terminal TNi+1.

As described above, in the configuration of FIG. 3 , the first, second, and third normal input/output terminals TN1 , TN2 , and TN3 may be main input/output terminals, and the fourth normal input/output terminal TN4 may be a sub input/output terminal. . In this case, the main conversion units CUi (i=1, 2, 3) corresponding to the main input/output terminals TN1, TN2, TN3 are connected to the corresponding path selection signal PSLi regardless of the block control signal BLK. ), the terminal '1' or the terminal '2' may be electrically connected to the corresponding input/output node NDi of the internal circuit 20 . As described with reference to FIG. 5 , the fourth conversion unit CU4 corresponding to the sub input/output terminal TN4 has the internal circuit 20 when the block control signal BLK is activated to the second logic level H. An electrical connection between the and the sub conversion unit CU4 may be cut off. When the block control signal BLK is deactivated to the first logic level L, the fourth conversion unit CU4 responds to the fourth path selection signal PSL4 like other main conversion units CU1 , CU2 , and CU3 . In response, the terminal '1' or the terminal '2' may be electrically connected to the fourth input/output node ND4 of the internal circuit 20 .

Hereinafter, for convenience of description, when the path selection signal PSLi is at the logic low level L, the terminal '1' of the conversion unit CUi is selected so that the conversion unit CUi is connected to the corresponding normal input/output terminal TNi. is electrically connected to and when the path selection signal PSLi is at the logic high level H, terminal '2' of the conversion unit CUi is selected so that the conversion unit CUi is connected to the adjacent normal input/output terminal TNi+1. It is assumed to be electrically connected. The logic level of the path selection signal PSLi for selecting a specific terminal may be changed according to the configuration of the conversion unit CUi.

The repair circuit described with reference to FIGS. 3 to 6 converts the defective input/output terminal corresponding to the defective signal path among the normal input/output terminals TN1, TN2, TN3, and TN4 to the normal input/output terminal adjacent to the defective input/output terminal or the defective A shifting repair operation is performed to replace the repair input/output terminal adjacent to the input/output terminal. A defective signal path may be repaired regardless of whether the repair signal path is supported by using a repair circuit having the same configuration. Hereinafter, the first repair mode not using the repair signal path and the repair input/output terminal will be described with reference to FIGS. 7, 8A and 8B, and the first repair mode using the repair signal path and the repair input/output terminal will be described with reference to FIGS. 9, 10A and 10B. 2 The repair mode will be described.

7 is a block diagram illustrating a system including the path conversion circuit of FIG. 3 and not supporting a repair signal path.

Referring to FIG. 7 , the system 51a includes a first subsystem 11 , a second subsystem 61a , and a signal path part 41a connecting the first subsystem 11 and the second subsystem 61a. ) may be included.

The first subsystem 11 selectively operates in one of a first repair mode not using the repair input/output terminal TR and a second repair mode using the repair input/output terminal TR according to embodiments of the present invention You have a configuration that you can do. The first subsystem 11 may include an input/output terminal unit 31 , a repair control unit (RC) 201 , and a path conversion circuit 301 . The internal circuit of the first subsystem 11 is omitted for convenience.

The input/output terminal unit 31 includes a plurality of normal input/output terminals TN1 , TN2 , TN3 , and TN4 and at least one repair input/output terminal TR. The repair control unit 201 may generate the path control signal PCON based on the mode signal MD and the failure information signal FLI. The path conversion circuit 301 may control the connection between the input/output terminal 31 and the internal circuit in response to the path control signal PCON.

As described above with reference to FIG. 3 , the path conversion circuit 301 responds to each of the path selection signals PSL1 , PSL2 , PSL3 , and PSL4 to the input/output nodes ND1 , ND2 , ND3 , and ND4 of the internal circuit. may include a plurality of conversion units CU1 , CU2 , CU3 , and CU4 for respectively controlling electrical connections between each of and the two or more input/output terminals of the input/output terminal unit 31 .

The second subsystem 61a has a configuration that does not support the repair signal path. The second subsystem 61a may include an input/output terminal unit 71a, a repair control unit (RCa) 81a, and a path conversion circuit 91a. The internal circuit of the second subsystem 61a is omitted for convenience.

The input/output terminal unit 71a includes only the plurality of normal input/output terminals TN1a, TN2a, TN3a, and TN4a, but does not include a repair input/output terminal. The repair control unit 81a may generate the path control signal PCONa based on the failure information signal FLI. The path conversion circuit 91a may control the connection between the input/output terminal 71a and the internal circuit in response to the path control signal PCONa.

Similar to the path converting circuit 301 of the first subsystem 11, the path converting circuit 91a of the second subsystem 61a responds to each of the path selection signals to input and output each of the input/output nodes of the internal circuit. It may include a plurality of conversion units (CU1a, CU2a, CU3a, CU4a) for controlling the electrical connection between the two or more input/output terminals of the terminal unit 71a, respectively. However, since the input/output terminal unit 71a does not include the repair input/output terminal, the last conversion unit CU4a may control the electrical connection between the input/output node of the internal circuit and one input/output terminal TN4a.

Since the second subsystem 61a is fixed to a configuration that does not support the repair signal path, the repair control unit 81a of the second subsystem 61a may not receive the mode signal MD. The failure information signal FLI provided to the first subsystem 11 and the failure information signal FLI provided to the second subsystem 61a may be the same.

The signal path unit 41a may include a plurality of normal signal paths MSP1, MSP2, MSP3, and SSP. The normal signal paths MSP1 , MSP2 , MSP3 , and SSP are first, second, and third main signals for transmitting main signals MS1 , MS2 , and MS3 for the main operation of the first subsystem 11 . It may include paths MSP1 , MSP2 , and MSP3 and at least one sub-signal path SSP for transmitting a sub-signal SS for a sub-operation of the first subsystem 11 . Accordingly, the first, second, and third normal input/output terminals TN1 , TN2 , and TN3 may be referred to as main input/output terminals, and the fourth normal input/output terminal TN4 may be referred to as a sub input/output terminal. In addition, the first, second, and third transformation units CU1 , CU2 , and CU3 may be referred to as main transformation units, and the fourth transformation unit CU4 may be referred to as a sub transformation unit.

The main operation indicates an operation that must be performed in order to perform a unique function of the subsystem, and the sub operation indicates an operation with no or insignificant influence on the main operation. For example, in the case of a memory device, the main operation may be a basic read operation and a write operation, and the sub operation performs ancillary functions such as data bus inversion (DBI), data mask (DM), and parity check. These may be actions to be performed.

FIG. 7 illustrates signal transmission when the bad signal path is not included in the normal signal paths MSP1, MSP2, MSP3, and SSP. That is, when there is no bad signal path, the repair function is disabled, and the first, second, and third main signals MS1 , MS2 , and MS3 are transmitted through the corresponding main signal paths MSP1 , MSP2 , and MSP3 . and the sub-signal SS may be transmitted through the sub-signal path SSP.

8A and 8B are diagrams for explaining a repair operation of the system of FIG. 7 .

For example, as shown in FIG. 8A , the first main signal path MSP1 may be a bad signal path. In this case, the first main signal MS1 is transmitted through the second main signal path MSP2, the second main signal MS2 is transmitted through the third main signal path MSP3, and the third main signal MS3) may be transmitted through a sub-signal path (SSP). The first, second, third, and fourth path selection signals PSL1 , PSL2 , PSL3 , and PSL4 are all activated to the logic high level H, and the first, second, third and fourth conversion units (CU1, CU2, CU3, CU4) can all select terminal '2'. As a result, the first, second, and third main signals MS1 , MS2 , and MS3 are to be respectively transmitted through the input/output nodes ND1 , ND2 , and ND3 of the internal circuit as in the case where the bad signal path is not included. can

For example, as shown in FIG. 8B , the second main signal path MSP2 may be a bad signal path. In this case, the first main signal MS1 is transmitted through the first main signal path MSP2 as it is, the second main signal MS2 is transmitted through the third main signal path MSP3, and the third main signal (MS3) may be transmitted through a sub-signal path (SSP). The first path selection signal PSL1 may maintain a deactivated state at the logic low level L, and the first conversion unit CU1 may select the terminal '1'. The second, third, and fourth path selection signals PSL2, PSL3, and PSL4 are all activated to the logic high level H, and the second, third, and fourth conversion units CU2, CU3, and CU4 are all Terminal '2' can be selected. As a result, the first, second, and third main signals MS1 , MS2 , and MS3 are to be respectively transmitted through the input/output nodes ND1 , ND2 , and ND3 of the internal circuit as in the case where the bad signal path is not included. can

As illustrated in FIGS. 8A and 8B , in the first repair mode that does not support the repair signal path, the bad signal path may be repaired using the sub signal path. The repair circuit including the path conversion circuit 301 of FIG. 3 performs a shifting repair operation to replace the bad input/output terminal corresponding to the bad signal path among the normal input/output terminals TN1, TN2, TN3, and TN4 to the sub input/output terminal ( It can be repaired using TN4). Transmission of the sub-signal SS is stopped and the sub-operation using the sub-signal SS is stopped. The block control signal BLK is activated to, for example, a logic high level H, and the electrical connection between the fourth conversion unit CU4 corresponding to the sub conversion unit and the fourth input/output node ND4 of the internal circuit is cut off or may be disabled.

9 is a block diagram illustrating a system including the path conversion circuit of FIG. 3 and supporting a repair signal path.

Referring to FIG. 9 , the system 51b includes a first subsystem 11 , a second subsystem 61b , and a signal path part 41b connecting the first subsystem 11 and the second subsystem 61b. ) may be included.

The first subsystem 11 selectively operates in one of a first repair mode not using the repair input/output terminal TR and a second repair mode using the repair input/output terminal TR according to embodiments of the present invention You have a configuration that you can do. The first subsystem 11 may include an input/output terminal unit 31 , a repair control unit (RC) 201 , and a path conversion circuit 301 . The internal circuit of the first subsystem 11 is omitted for convenience.

The input/output terminal unit 31 includes a plurality of normal input/output terminals TN1 , TN2 , TN3 , and TN4 and at least one repair input/output terminal TR. The repair control unit 201 may generate the path control signal PCON based on the mode signal MD and the failure information signal FLI. The path conversion circuit 301 may control the connection between the input/output terminal 31 and the internal circuit in response to the path control signal PCON.

As described above with reference to FIG. 3 , the path conversion circuit 301 responds to each of the path selection signals PSL1 , PSL2 , PSL3 , and PSL4 to the input/output nodes ND1 , ND2 , ND3 , and ND4 of the internal circuit. may include a plurality of conversion units CU1 , CU2 , CU3 , and CU4 for respectively controlling electrical connections between each of and the two or more input/output terminals of the input/output terminal unit 31 .

The second subsystem 61b has a configuration that supports the repair signal path. The second subsystem 61b may include an input/output terminal unit 71b, a repair control unit (RCb) 81b, and a path conversion circuit 91b. The internal circuit of the second subsystem 61b is omitted for convenience.

The input/output terminal unit 71b includes a plurality of normal input/output terminals TN1b, TN2b, TN3b, and TN4b and a repair input/output terminal TRb. The repair control unit 81b may generate the path control signal PCONb based on the failure information signal FLI. The path conversion circuit 91b may control the connection between the input/output terminal 71b and the internal circuit in response to the path control signal PCONb.

Similar to the path converting circuit 301 of the first subsystem 11, the path converting circuit 91b of the second subsystem 61b responds to each of the path selection signals to each of the input/output nodes of the internal circuit and input/output. It may include a plurality of conversion units (CU1b, CU2b, CU3b, CU4b) for controlling the electrical connection between the two or more input/output terminals of the terminal unit 71b, respectively.

Since the second subsystem 61b is fixed to a configuration supporting the repair signal path, the repair control unit 81b of the second subsystem 61b may not receive the mode signal MD. The failure information signal FLI provided to the first subsystem 11 and the failure information signal FLI provided to the second subsystem 61b may be the same.

The signal path unit 41b may include a plurality of normal signal paths MSP1, MSP2, MSP3, and SSP and at least one repair signal path RSP. The normal signal paths MSP1 , MSP2 , MSP3 , and SSP are first, second, and third main signals for transmitting main signals MS1 , MS2 , and MS3 for the main operation of the first subsystem 11 . It may include paths MSP1 , MSP2 , and MSP3 and at least one sub-signal path SSP for transmitting a sub-signal SS for a sub-operation of the first subsystem 11 . Accordingly, the first, second, and third normal input/output terminals TN1 , TN2 , and TN3 may be referred to as main input/output terminals, and the fourth normal input/output terminal TN4 may be referred to as a sub input/output terminal. In addition, the first, second, and third transformation units CU1 , CU2 , and CU3 may be referred to as main transformation units, and the fourth transformation unit CU4 may be referred to as a sub transformation unit.

The main operation indicates an operation that must be performed in order to perform a unique function of the subsystem, and the sub operation indicates an operation with no or insignificant influence on the main operation. For example, in the case of a memory device, the main operation may be a basic read operation and a write operation, and the sub operation performs ancillary functions such as data bus inversion (DBI), data mask (DM), and parity check. These may be actions to be performed.

FIG. 9 illustrates signal transmission when the bad signal path is not included in the normal signal paths MSP1, MSP2, MSP3, and SSP. That is, when there is no bad signal path, the repair function is disabled, and the first, second, and third main signals MS1 , MS2 , and MS3 are transmitted through the corresponding main signal paths MSP1 , MSP2 , and MSP3 . and the sub-signal SS may be transmitted through the sub-signal path SSP.

10A and 10B are diagrams for explaining a repair operation of the system of FIG. 9 .

For example, as shown in FIG. 10A , the first main signal path MSP1 may be a bad signal path. In this case, the first main signal MS1 is transmitted through the second main signal path MSP2, the second main signal MS2 is transmitted through the third main signal path MSP3, and the third main signal MS3) may be transmitted through the sub-signal path SSP, and the sub-signal SS may be transmitted through the repair signal path RSP. The first, second, third, and fourth path selection signals PSL1 , PSL2 , PSL3 , and PSL4 are all activated to the logic high level H, and the first, second, third and fourth conversion units (CU1, CU2, CU3, CU4) can all select terminal '2'. As a result, the first, second, and third main signals MS1 , MS2 , MS3 and the sub-signal SS are the input/output nodes ND1 , ND2 , and ND3 of the internal circuit as in the case where the bad signal path is not included. , ND4) can be transmitted respectively.

For example, as shown in FIG. 10B , the second main signal path MSP2 may be a bad signal path. In this case, the first main signal MS1 is transmitted through the first main signal path MSP2 as it is, the second main signal MS2 is transmitted through the third main signal path MSP3, and the third main signal MS3 may be transmitted through the sub-signal path SSP, and the sub-signal SS may be transmitted through the repair signal path RSP. The first path selection signal PSL1 may maintain a deactivated state at the logic low level L, and the first conversion unit CU1 may select the terminal '1'. The second, third, and fourth path selection signals PSL2, PSL3, and PSL4 are all activated to the logic high level H, and the second, third, and fourth conversion units CU2, CU3, and CU4 are all Terminal '2' can be selected. As a result, the first, second, and third main signals MS1 , MS2 , MS3 and the sub-signal SS are the input/output nodes ND1 , ND2 , and ND3 of the internal circuit as in the case where the bad signal path is not included. , ND4) can be transmitted respectively.

10A and 10B , in the second repair mode supporting the repair signal path, the bad signal path may be repaired using the repair signal path. The repair circuit including the path conversion circuit 301 of FIG. 3 performs a shifting repair operation to replace the defective input/output terminal corresponding to the defective signal path among the normal input/output terminals TN1, TN2, TN3, and TN4 to the repair input/output terminal ( TR) can be used to repair it. The transmission of the sub-signal SS is maintained, and a sub-operation using the sub-signal SS can also be performed. The block control signal BLK is, for example, deactivated to the logic low level L, and the fourth conversion unit CU4 corresponding to the sub conversion unit and the fourth input/output node ND4 of the internal circuit may be electrically connected. .

11 is a view illustrating an embodiment of a repair control unit for providing path selection signals to the path converting circuit of FIG. 3 , and FIG. 12 is a view for explaining the overall operation of the repair circuit including the path converting circuit of FIG. 3 am.

The bad information signal FLI may include a plurality of bit signals FLI1 , FLI2 , FLI3 , and FLI4 respectively corresponding to normal signal paths. 11 and 12 , bit signals FLI1 , FLI2 , FLI3 , FLI4 indicate that the corresponding normal signal path is not bad when the logic low level (L) and the corresponding normal when the logic high level (H). It may indicate that the signal path is bad. The path selection signals PSL1, PSL2, PSL3, and PSL4 have a corresponding conversion unit selecting terminal '1' when a logic low level (L) and a corresponding conversion unit selecting terminal '2' when a logic high level (H) is present. ' can be selected. The mode signal MD may indicate a first repair mode in which the repair signal path is not used when the logic high level (H) and the second repair mode using the repair signal path when the logic low level (L). . In FIG. 12 , cases 1 to 5 indicate a first repair mode not using a repair signal path, and cases 6 to 10 indicate a second repair mode using a repair signal path.

The definition of the logic level of the signals is an example for convenience of description, and the logic level of the signals may be defined in various ways according to the circuit configuration.

Referring to FIG. 11 , the repair control unit 201 may include first, second, third, and fourth OR gates 211 , 212 , 213 , and 214 and an OR gate 215 . The first OR gate 211 generates a first path selection signal PSL1 by performing an OR operation on the ground voltage signal VSS and the first bit signal FLI1 of the bad information signal. The second OR gate 212 generates a second path selection signal PSL2 by performing an OR operation on the first path selection signal PSL1 and the second bit signal FLI2 of the bad information signal FLI. The third OR gate 213 generates a third path selection signal PSL3 by performing an OR operation on the second path selection signal PSL2 and the third bit signal FLI3 of the bad information signal FLI. The fourth OR gate 214 generates a fourth path selection signal PSL4 by performing an OR operation on the third path selection signal PSL3 and the fourth bit signal FLI4 of the bad information signal FLI. The AND gate 215 generates a block control signal BLK by performing an AND operation on the fourth path selection signal PSL4 and the mode signal MD.

Referring to FIG. 12 , according to the configuration of FIG. 11 , when the bit signal FLIi corresponding to the bad signal path is activated to the logic high level H, the corresponding path selection signal PSLi to the last path selection signal PSL4 ) are all activated to the logic high level (H). When the first bit signal FLI1 is activated to the logic high level H, the first, second, third, and fourth path selection signals PSL1 , PSL2 , PSL3 , and PSL4 are activated to the logic high level H When the second bit signal FLI2 is activated to the logic high level H, the second, third, and fourth path selection signals PSL2, PSL3, and PSL4 are activated to the logic high level H, and the second bit signal FLI2 is activated to the logic high level H. When the 3-bit signal FLI3 is activated to the logic high level H, the third and fourth path selection signals PSL3 and PSL4 are activated to the logic high level H, and the fourth bit signal FLI4 is activated to the logic high level H. When activated to a high level (H), only the fourth path selection signal PSL4 is activated to a logic high level (H). When a bad signal path occurs using such path selection signals PSL1, PSL2, PSL3, and PSL4, a shifting repair operation of sequentially replacing each signal path with an adjacent signal path may be performed.

At least one bad signal path exists in the block control signal BLK, so that the fourth path selection signal PSL4 is activated to a logic high level (H) and the mode signal (MD) is a repair signal path as a logic high level (H). It has a logic high level (H) when indicating the first repair mode not using . In other cases, the block control signal BLK has a logic low level L.

In this way, the path control signal PCON, that is, the path selection signals PSL1, PSL2, PSL3, and PSL4, and the block control signal BLK may be generated based on the mode signal MD and the failure information signal FLI. . Using the path control signal PCON, the shifting repair operation is performed in the first repair mode that does not use the repair signal path as described with reference to FIGS. 7, 8A and 8B, or see FIGS. 9, 10A and 10B As described above, the shifting repair operation may be performed in the second repair mode using the repair signal path.

13 is a block diagram illustrating a path conversion circuit performing a shifting repair operation according to embodiments of the present invention.

Referring to FIG. 13 , the path conversion circuit 301 may include a plurality of conversion units CU1 , CU2 , CU3 , CU4 and an initialization circuit 315 .

As described above, the conversion units CU1, CU2, CU3, and CU4 are input/output nodes ND1, ND2, ND3, ND4 of the internal circuit in response to each of the path selection signals PSL1, PSL2, PSL3, and PSL4. ) and performing a shifting repair operation for respectively controlling electrical connections between two or more input/output terminals of the input/output terminal unit 31 .

The initialization circuit 315 may be connected to the repair input/output terminal TR, and may apply the initialization voltage VINT to the repair input/output terminal TR in response to the mode signal MD. For example, the initialization circuit 315 may include an NMOS transistor. In this case, when the mode signal MD has a logic high level H and indicates the first repair mode in which the repair signal path and the repair input/output terminal TR are not used, the NMOS transistor is turned on to obtain an initialization voltage VINT. It may be applied to the repair input/output terminal TR. On the other hand, when the mode signal MD has a logic low level L and indicates the second repair mode using the repair signal path and the repair input/output terminal TR, the NMOS transistor is turned off and the repair input/output terminal TR is turned off. ) may be blocked from being applied to the initialization voltage VINT.

Conventionally, due to the problem of the floating state of the repair signal path, it is necessary to implement a system by separating the case in which the repair signal path is supported and the case in which the repair signal path is not supported. According to embodiments of the present invention, it is possible to implement an integrated system that can selectively apply various repair methods by using an initialization circuit that holds the initial state of the repair input/output terminal TR.

14 is a block diagram illustrating a path conversion circuit performing a multiplexing repair operation according to embodiments of the present invention.

Referring to FIG. 14 , the path conversion circuit 302 responds to each of the path selection signals PSL1 , PSL2 , PSL3 , and PSL4 , respectively, and input/output nodes of the input/output nodes ND1 , ND2 , ND3 and ND4 of the internal circuit. It may include a plurality of conversion units (CU1, CU2, CU3, CU4) (321, 322, 323, 324) for controlling the electrical connection between the two or more input/output terminals of the terminal unit 32, respectively. Although the first to fourth conversion units 321 , 322 , 323 , and 324 are illustrated in FIG. 14 for convenience, the number of conversion units and input/output terminals may be variously changed.

As described with reference to FIG. 7 , the normal input/output terminals TN1 , TN2 , TN3 , and TN4 are main input/output terminals for transmitting main signals for the main operation of the internal circuit 20 of FIG. 1 and the internal circuit ( 20) may include at least one sub input/output terminal for transmitting a sub signal for the sub operation. For example, in the configuration of FIG. 14 , the first, second, and third normal input/output terminals TN1 , TN2 , and TN3 may be main input/output terminals, and the fourth normal input/output terminal TN4 may be a sub input/output terminal.

Each of the main conversion units 321 , 322 , 323 corresponding to the main input/output terminals TN1 , TN2 , TN3 of the conversion units 321 , 322 , 323 , and 324 are normal input/output terminals TN1 , TN2 , TN3 , TN4) may be connected to a corresponding normal input/output terminal, a sub input/output terminal TN4, and a repair input/output terminal TR. That is, the first conversion unit 321 is connected to the first normal input/output terminal TN1, the fourth input/output terminal TN4, and the repair input/output terminal TR, and the second conversion unit 322 is connected to the second normal input/output terminal ( TN2) is connected to the fourth input/output terminal TN4 and the repair input/output terminal TR, and the third conversion unit 323 includes the third normal input/output terminal TN3, the fourth input/output terminal TN4, and the repair input/output terminal ( TR) can be connected.

Among the conversion units 321 , 322 , 323 , and 324 , the sub conversion unit 324 corresponding to the sub input/output terminal TN4 may be connected to the sub input/output terminal TN4 and the repair input/output terminal TR. That is, the fourth conversion unit 314 may be connected to the sub input/output terminal TN4 and the repair input/output terminal TR.

As described with reference to FIGS. 22 and 23 , the repair control unit 200 of FIG. 2 may control the logic levels of the path selection signals PSL1 , PSL2 , PSL3 , and PSL4 to perform a multiplexing repair operation, and convert Each of the units 321 , 322 , 323 , and 324 may be selectively connected to one of the three input/output terminals according to the respective logic levels of the path selection signals PSL1 , PSL2 , PSL3 , and PSL4 . When the path selection signal PSLi is deactivated to a first logic level (eg, a logic low level), the terminal '1' is selected so that the conversion unit CUi may be connected to the corresponding input/output terminal. When the path selection signal PSLi is activated to a second logic level (eg, a logic high level), the terminal '2' or the terminal '3' is selected according to the logic level of the mode signal MD, so that the conversion unit ( CUi) may be connected to the sub input/output terminal TN4 or the repair input/output terminal TR.

15A is a diagram illustrating an embodiment of a path conversion circuit that performs a multiplexing repair operation and a reception operation.

Referring to FIG. 15A , the path conversion circuit 302a may include a plurality of conversion units 321a, 3212a, 323a, and 324a. 15A shows an embodiment in which the path conversion circuit 302a serves as a receiving interface, and each of the conversion units 321a, 322a, 323a, 324a converts received signals from an external device into the internal circuit ( 20) and a receiver (RX) for forwarding. Each receiver RX receives a reception signal input from one of two or more input/output terminals of the input/output terminal unit 32 in response to each of the path selection signals PSL1, PSL2, PSL3, and PSL4 and the mode signal MD. may be output to each of the input/output nodes ND1 , ND2 , ND3 , and ND4 of the internal circuit 20 .

That is, the receiver of the first conversion unit 321a responds to the mode signal MD and the first path selection signal PSL1 , the first normal input/output terminal TN1 , the fourth normal input/output terminal TN4 , and the repair input/output terminal One of (TR) is electrically connected to the first input/output node ND1 of the internal circuit 20, and the receiver of the second conversion unit 322a receives the mode signal MD and the second path selection signal PSL2. In response, one of the second normal input/output terminal TN2, the fourth normal input/output terminal TN4, and the repair input/output terminal TR is electrically connected to the second input/output node ND2 of the internal circuit 20, The receiver of the 3 conversion unit 323a responds to the mode signal MD and the third path selection signal PSL3 to the third normal input/output terminal TN3, the fourth normal input/output terminal TN4, and the repair input/output terminal TR. One of them is electrically connected to the third input/output node ND3 of the internal circuit 20, and the receiver of the fourth conversion unit 324a responds to the mode signal MD and the fourth path selection signal PSL4. One of the 4 normal input/output terminals TN4 and the repair input/output terminal TR may be electrically connected to the fourth input/output node ND4 of the internal circuit 20 .

15B is a diagram illustrating an embodiment of a path conversion circuit that performs a multiplexing repair operation and a transmission operation.

Referring to FIG. 15B , the path conversion circuit 302b may include a plurality of conversion units 321b, 322b, 323b, and 324b. Fig. 15b shows an embodiment in which the path conversion circuit 302b serves as a transmit interface, and each of the conversion units 321b, 322b, 323b, 324b transmits the transmit signals from the internal circuit 20 of Fig. 1 . It may include a transmitter (TX) for transmitting to an external device. Each transmitter TX receives the input/output nodes ND1, ND2, ND3, and ND4 of the internal circuit 20 in response to each of the path selection signals PSL1, PSL2, PSL3, and PSL4 and the mode signal MD. A transmission signal input from each may be output to one of two or more input/output terminals of the input/output terminal unit 32 .

That is, the transmitter of the first conversion unit 321b connects the first input/output node ND1 of the internal circuit 20 to the first normal input/output terminal TN1 in response to the mode signal MD and the first path selection signal PSL1 . ), the fourth normal input/output terminal TN4 and the repair input/output terminal TR are electrically connected to one of the transmitters of the second conversion unit 322b to the mode signal MD and the second path selection signal PSL2. In response, the second input/output node ND2 of the internal circuit 20 is electrically connected to one of the second normal input/output terminal TN2, the fourth normal input/output terminal TN4, and the repair input/output terminal TR, and a third The transmitter of the conversion unit 323b connects the third input/output node ND3 of the internal circuit 20 to the third normal input/output terminal TN3 and the fourth in response to the mode signal MD and the third path selection signal PSL3. Electrically connected to one of the normal input/output terminal TN4 and the repair input/output terminal TR, the transmitter of the fourth conversion unit 324b responds to the mode signal MD and the fourth path selection signal PSL4 to an internal circuit The fourth input/output node ND3 of ( 20 ) may be electrically connected to one of the fourth normal input/output terminal TN4 and the repair input/output terminal TR.

15C is a diagram illustrating an embodiment of a path conversion circuit that performs a multiplexing repair operation and a transmission/reception operation.

Referring to FIG. 15C , the path conversion circuit 302c may include a plurality of conversion units 321c , 322c , 323c , and 324c . FIG. 15C shows an embodiment in which the path conversion circuit 302c serves as a transmit and receive interface, and each of the conversion units 321c, 322c, 323c, and 324c converts received signals from an external device into the inside of FIG. 1 . It may include a receiver RX for transmitting to the circuit 20 and a transmitter TX for transmitting transmission signals from the internal circuit 20 to an external device. As described with reference to FIG. 15A , each receiver RX receives two or more input/output of the input/output terminal 32 in response to each of the path selection signals PSL1, PSL2, PSL3, and PSL4 and the mode signal MD. A reception signal input from one of the terminals may be output to each of the input/output nodes ND1 , ND2 , ND3 , and ND4 of the internal circuit 20 . As described with reference to FIG. 15B , each transmitter TX receives input/output nodes ( A transmission signal input from each of ND1 , ND2 , ND3 , and ND4 may be output to one of two or more input/output terminals of the input/output terminal unit 32 .

16 is a diagram illustrating an embodiment of a sub conversion unit included in the path conversion circuit of FIG. 14 .

As described above with reference to FIG. 7 , the normal input/output terminals TN1 , TN2 , TN3 , and TN4 are main input/output terminals for transmitting main signals for the main operation of the internal circuit 20 of FIG. 1 and the internal circuit At least one sub input/output terminal for transmitting a sub signal for the sub operation of (20) may be included. For example, in the configuration of FIG. 14 , the first, second, and third normal input/output terminals TN1 , TN2 , and TN3 may be main input/output terminals, and the fourth normal input/output terminal TN4 may be a sub input/output terminal.

Referring to FIG. 16 , the fourth conversion unit CU4 corresponding to the sub input/output terminal TN4 may include a buffer unit BUF and a selection unit SEL.

The selection unit SEL responds to the fourth path selection signal PSL4 and the mode signal MD as described with reference to FIGS. 15A, 15B and 15C , and the fourth input/output node ND4 of the internal circuit 20 . and a receiver RX and/or a transmitter TX for controlling an electrical connection between the fourth normal input/output terminal TN4 and the repair input/output terminal TR of the input/output terminal unit 32 . The terminal '2' of the selection unit SEL may be in a floating state. The buffer unit BUF may block an electrical connection between the fourth input/output node ND4 and the selection unit SEL in response to the block control signal BLK.

For example, when a sub-signal for the sub-operation is transmitted, the block control signal BLK is inactivated to a first logic level (eg, a logic low level L) and the buffer unit BUF is configured to generate a fourth The input/output node ND4 and the selection unit SEL may be electrically connected. On the other hand, when the sub-signal for the sub-operation is not transmitted, the block control signal BLK is activated to a second logic level (eg, a logic high level H) and the buffer unit BUF operates the fourth input/output. An electrical connection between the node ND4 and the selection unit SEL may be blocked.

As such, the sub conversion unit CU4 corresponding to the sub input/output terminal TN4 among the conversion units CU1, CU2, CU3, CU4 responds to the block control signal BLK with the internal circuit 20 and the sub conversion unit It is possible to break the electrical connection between (CU4).

FIG. 17 is a diagram for explaining operations of conversion units included in the path conversion circuit of FIG. 14 .

Referring to FIG. 17 , one of the terminals of the corresponding conversion unit CUi may be selected according to the logic levels of the mode signal MD and the path selection signal PSLi. For example, when the path selection signal PSLi is inactivated to the first logic level (eg, the logic low level L), the terminal '1' is selected so that the conversion unit CUi is connected to the corresponding normal input/output terminal. (TNi) can be connected. When the path selection signal PSLi is activated to the second logic level (eg, the logic high level H) and the mode signal MD is the second logic level, the terminal '2' is selected and the conversion unit CUi ) may be connected to the fourth input/output terminal TN4 which is a sub input/output terminal. When the path selection signal PSLi is activated to the second logic level and the mode signal MD is at the first logic level (eg, the logic low level L), the terminal '3' is selected and the conversion unit CUi ) may be connected to the repair input/output terminal TR.

As described above, in the configuration of FIG. 14 , the first, second, and third normal input/output terminals TN1 , TN2 , and TN3 may be main input/output terminals, and the fourth normal input/output terminal TN4 may be a sub input/output terminal. . In this case, the main conversion units CUi (i=1, 2, 3) corresponding to the main input/output terminals TN1, TN2, TN3 are connected to the corresponding mode signal MD regardless of the block control signal BLK. and the terminal '1', the terminal '2', or the terminal '3' may be electrically connected to the corresponding input/output node NDi of the internal circuit 20 in response to the path selection signal PSLi. As described with reference to FIG. 16 , the fourth conversion unit CU4 corresponding to the sub input/output terminal TN4 has the internal circuit 20 when the block control signal BLK is activated to the second logic level H. An electrical connection between the and the sub conversion unit CU4 may be cut off. When the block control signal BLK is deactivated to the first logic level H, the fourth conversion unit CU4 has a mode signal MD and a fourth path like other main conversion units CU1 , CU2 , and CU3 . The terminal '1', the terminal '2', or the terminal '3' may be electrically connected to the fourth input/output node ND4 of the internal circuit 20 in response to the selection signal PSL4 .

Hereinafter, for convenience of description, when the path selection signal PSLi is at the logic low level L, the terminal '1' of the conversion unit CUi is selected so that the conversion unit CUi is connected to the corresponding normal input/output terminal TNi. is electrically connected to, and when the mode signal MD is at the logic high level (H) and the path selection signal (PSLi) is at the logic high level (H), the terminal '2' of the conversion unit CUi is selected so that the conversion unit ( CUi) is electrically connected to the sub input/output terminal TN4, and when the mode signal MD is at the logic low level L and the path selection signal PSLi is at the logic high level H, the terminal of the conversion unit CUi It is assumed that '3' is selected so that the conversion unit CUi is electrically connected to the repair input/output terminal TR. The logic levels of the mode signal MD and the path selection signal PSLi for selecting a specific terminal may be changed according to the configuration of the conversion unit CUi.

The repair circuit described with reference to FIGS. 14 to 17 is a multiplexing that replaces the bad input/output terminal corresponding to the bad signal path among the normal input/output terminals TN1, TN2, TN3, and TN4 with the sub input/output terminal or the repair input/output terminal. Perform a repair operation. A defective signal path may be repaired regardless of whether the repair signal path is supported by using a repair circuit having the same configuration. Hereinafter, the first repair mode will be described in which the repair signal path and the repair input/output terminal are not used with reference to FIGS. 18, 19A and 19B, and the first repair mode using the repair signal path and the repair input/output terminal will be described with reference to FIGS. 20, 21A and 21B. 2 The repair mode will be described.

18 is a block diagram illustrating a system including the path conversion circuit of FIG. 14 and not supporting a repair signal path.

Referring to FIG. 18 , the system 52a includes a first subsystem 12 , a second subsystem 62a , and a signal path part 42a connecting the first subsystem 12 and the second subsystem 62a. ) may be included.

The first subsystem 12 selectively operates in one of a first repair mode not using the repair input/output terminal TR and a second repair mode using the repair input/output terminal TR according to embodiments of the present invention You have a configuration that you can do. The first subsystem 12 may include an input/output terminal unit 32 , a repair control unit (RC) 202 , and a path conversion circuit 302 . The internal circuit of the first subsystem 12 is omitted for convenience.

The input/output terminal unit 32 includes a plurality of normal input/output terminals TN1 , TN2 , TN3 , and TN4 and at least one repair input/output terminal TR. The repair control unit 202 may generate the path control signal PCON based on the mode signal MD and the failure information signal FLI. The path conversion circuit 302 may control the connection between the input/output terminal 32 and the internal circuit in response to the path control signal PCON.

14, in response to each of the mode signal MD and the path selection signals PSL1, PSL2, PSL3, and PSL4, the path conversion circuit 302 operates the input/output nodes ND1 and ND1 of the internal circuit. It may include a plurality of conversion units (CU1, CU2, CU3, CU4) for controlling each of the ND2, ND3, ND4 and the electrical connection between the two or more input and output terminals of the input/output terminal unit 32, respectively.

The second subsystem 62a has a configuration that does not support the repair signal path. The second subsystem 62a may include an input/output terminal unit 72a, a repair control unit (RCa) 82a, and a path conversion circuit 92a. The internal circuit of the second subsystem 62a is omitted for convenience.

The input/output terminal unit 72a includes only the plurality of normal input/output terminals TN1a, TN2a, TN3a, and TN4a, but does not include a repair input/output terminal. The repair control unit 82a may generate the path control signal PCONa based on the failure information signal FLI. The path conversion circuit 92a may control the connection between the input/output terminal unit 72a and the internal circuit in response to the path control signal PCONa.

The path conversion circuit 92a of the second subsystem 62a controls the electrical connection between each of the input/output nodes of the internal circuit and two or more input/output terminals of the input/output terminal unit 72a in response to each of the path selection signals, respectively. and a plurality of conversion units CU1a, CU2a, CU3a, CU4a. However, since the input/output terminal unit 72a does not include the repair input/output terminal, the last conversion unit CU4a may control the electrical connection between the input/output node of the internal circuit and one input/output terminal TN4a.

Since the second subsystem 62a is fixed to a configuration that does not support the repair signal path, the repair control unit 82a of the second subsystem 62a may not receive the mode signal MD. The failure information signal FLI provided to the first subsystem 12 and the failure information signal FLI provided to the second subsystem 62a may be the same.

The signal path unit 42a may include a plurality of normal signal paths MSP1, MSP2, MSP3, and SSP. The normal signal paths MSP1 , MSP2 , MSP3 , and SSP are first, second, and third main signals for transmitting main signals MS1 , MS2 , and MS3 for the main operation of the first subsystem 12 . It may include paths MSP1 , MSP2 , and MSP3 and at least one sub-signal path SSP for transmitting a sub-signal SS for a sub-operation of the first subsystem 12 . Accordingly, the first, second, and third normal input/output terminals TN1 , TN2 , and TN3 may be referred to as main input/output terminals, and the fourth normal input/output terminal TN4 may be referred to as a sub input/output terminal. In addition, the first, second, and third transformation units CU1 , CU2 , and CU3 may be referred to as main transformation units, and the fourth transformation unit CU4 may be referred to as a sub transformation unit.

The main operation indicates an operation that must be performed in order to perform a unique function of the subsystem, and the sub operation indicates an operation with no or insignificant influence on the main operation. For example, in the case of a memory device, the main operation may be a basic read operation and a write operation, and the sub operation performs ancillary functions such as data bus inversion (DBI), data mask (DM), and parity check. These may be actions to be performed.

18 illustrates signal transmission when the bad signal path is not included in the normal signal paths MSP1, MSP2, MSP3, and SSP. That is, when there is no bad signal path, the repair function is disabled, and the first, second, and third main signals MS1 , MS2 , and MS3 are transmitted through the corresponding main signal paths MSP1 , MSP2 , and MSP3 . and the sub-signal SS may be transmitted through the sub-signal path SSP.

19A and 19B are diagrams for explaining a repair operation of the system of FIG. 18 .

For example, as shown in FIG. 19A , the first main signal path MSP1 may be a bad signal path. In this case, the first main signal MS1 is transmitted through the sub signal path SSP, the second main signal MS2 is transmitted through the second main signal path MSP2, and the third main signal MS3 is transmitted through the second main signal path MSP2. may be transmitted through the third main signal path MSP3. The mode signal MD may have a logic high level H to indicate the first repair mode that does not use the repair signal path. The first path selection signal PSL1 may be activated to a logic high level H, and the first conversion unit CU1 may select the terminal '2'. The second, third and fourth path selection signals PSL2, PSL3, and PSL4 are all deactivated to the logic low level L, and the second, third, and fourth conversion units CU2, CU3, and CU4 are all Terminal '1' can be selected. As a result, the first, second, and third main signals MS1 , MS2 , and MS3 are to be respectively transmitted through the input/output nodes ND1 , ND2 , and ND3 of the internal circuit as in the case where the bad signal path is not included. can

For example, as shown in FIG. 19B , the second main signal path MSP2 may be a bad signal path. In this case, the first main signal MS1 is transmitted through the first main signal path MSP1 , the second main signal MS2 is transmitted through the sub signal path SSP, and the third main signal MS3 is transmitted through the sub signal path SSP. may be transmitted through the third main signal path MSP3. The mode signal MD may have a logic high level H to indicate the first repair mode that does not use the repair signal path. The second path selection signal PSL2 may be activated to a logic high level H, and the second conversion unit CU2 may select the terminal '2'. All of the first, third, and fourth path selection signals PSL1 , PSL3 and PSL4 maintain an inactive state at the logic low level L, and the first, third, and fourth conversion units CU1, CU3, CU4) can all select terminal '1'. As a result, the first, second, and third main signals MS1 , MS2 , and MS3 are to be respectively transmitted through the input/output nodes ND1 , ND2 , and ND3 of the internal circuit as in the case where the bad signal path is not included. can

19A and 19B , in the first repair mode that does not support the repair signal path, the bad signal path may be repaired using the sub signal path. The repair circuit including the path conversion circuit 302 of FIG. 14 performs a multiplexing repair operation to replace the bad input/output terminal corresponding to the bad signal path among the normal input/output terminals TN1, TN2, TN3, and TN4 to the sub input/output terminal ( It can be repaired using TN4). Transmission of the sub-signal SS is stopped and the sub-operation using the sub-signal SS is stopped. The block control signal BLK is activated to, for example, a logic high level H, and the electrical connection between the fourth conversion unit CU4 corresponding to the sub conversion unit and the fourth input/output node ND4 of the internal circuit is cut off or may be disabled.

20 is a block diagram illustrating a system including the path conversion circuit of FIG. 14 and supporting a repair signal path.

Referring to FIG. 20 , the system 52b includes a first subsystem 12 , a second subsystem 62b , and a signal path part 42b connecting the first subsystem 12 and the second subsystem 62b. ) may be included.

The first subsystem 12 selectively operates in one of a first repair mode not using the repair input/output terminal TR and a second repair mode using the repair input/output terminal TR according to embodiments of the present invention You have a configuration that you can do. The first subsystem 12 may include an input/output terminal unit 32 , a repair control unit (RC) 202 , and a path conversion circuit 302 . The internal circuit of the first subsystem 12 is omitted for convenience.

The input/output terminal unit 32 includes a plurality of normal input/output terminals TN1 , TN2 , TN3 , and TN4 and at least one repair input/output terminal TR. The repair control unit 202 may generate the path control signal PCON based on the mode signal MD and the failure information signal FLI. The path conversion circuit 302 may control the connection between the input/output terminal 32 and the internal circuit in response to the path control signal PCON.

14, in response to each of the mode signal MD and the path selection signals PSL1, PSL2, PSL3, and PSL4, the path conversion circuit 302 operates the input/output nodes ND1 and ND1 of the internal circuit. It may include a plurality of conversion units (CU1, CU2, CU3, CU4) for controlling each of the ND2, ND3, ND4 and the electrical connection between the two or more input and output terminals of the input/output terminal unit 32, respectively.

The second subsystem 62b has a configuration that supports the repair signal path. The second subsystem 62b may include an input/output terminal unit 72b, a repair control unit (RCb) 82b, and a path conversion circuit 92b. The internal circuit of the second subsystem 62b is omitted for convenience.

The input/output terminal unit 72b includes a plurality of normal input/output terminals TN1b, TN2b, TN3b, and TN4b and a repair input/output terminal TRb. The repair control unit 82b may generate the path control signal PCONb based on the failure information signal FLI. The path conversion circuit 92b may control the connection between the input/output terminal unit 72b and the internal circuit in response to the path control signal PCONb.

Similar to the path converting circuit 302 of the first subsystem 12, the path converting circuit 92b of the second subsystem 62b responds to each of the path selection signals to input and output each of the input/output nodes of the internal circuit. It may include a plurality of conversion units (CU1b, CU2b, CU3b, CU4b) for controlling the electrical connection between the two or more input/output terminals of the terminal unit 72b, respectively.

Since the second subsystem 62b is fixed to a configuration supporting the repair signal path, the repair control unit 82b of the second subsystem 62b may not receive the mode signal MD. The failure information signal FLI provided to the first subsystem 12 and the failure information signal FLI provided to the second subsystem 62b may be the same.

The signal path unit 42b may include a plurality of normal signal paths MSP1, MSP2, MSP3, and SSP and at least one repair signal path RSP. The normal signal paths MSP1 , MSP2 , MSP3 , and SSP are first, second, and third main signals for transmitting main signals MS1 , MS2 , and MS3 for the main operation of the first subsystem 12 . It may include paths MSP1 , MSP2 , and MSP3 and at least one sub-signal path SSP for transmitting a sub-signal SS for a sub-operation of the first subsystem 12 . Accordingly, the first, second, and third normal input/output terminals TN1 , TN2 , and TN3 may be referred to as main input/output terminals, and the fourth normal input/output terminal TN4 may be referred to as a sub input/output terminal. In addition, the first, second, and third transformation units CU1 , CU2 , and CU3 may be referred to as main transformation units, and the fourth transformation unit CU4 may be referred to as a sub transformation unit.

The main operation indicates an operation that must be performed in order to perform a unique function of the subsystem, and the sub operation indicates an operation with no or insignificant influence on the main operation. For example, in the case of a memory device, the main operation may be a basic read operation and a write operation, and the sub operation performs ancillary functions such as data bus inversion (DBI), data mask (DM), and parity check. These may be actions to be performed.

FIG. 20 shows signal transmission when the bad signal path is not included in the normal signal paths MSP1, MSP2, MSP3, and SSP. That is, when there is no bad signal path, the repair function is disabled, and the first, second, and third main signals MS1 , MS2 , and MS3 are transmitted through the corresponding main signal paths MSP1 , MSP2 , and MSP3 . and the sub-signal SS may be transmitted through the sub-signal path SSP.

21A and 21B are diagrams for explaining a repair operation of the system of FIG. 20 .

For example, as shown in FIG. 21A , the first main signal path MSP1 may be a bad signal path. In this case, the first main signal MS1 is transmitted through the repair signal path RSP, the second main signal MS2 is transmitted through the second main signal path MSP2, and the third main signal MS3 may be transmitted through the third signal path MSP3, and the sub-signal SS may be transmitted through the sub-signal path SSP. The mode signal MD may have a logic low level L to indicate the second repair mode using the repair signal path. The first path selection signal PSL1 may be activated to a logic high level H, and the first conversion unit CU1 may select the terminal '3'. All of the second, third, and fourth path selection signals PSL2, PSL3, and PSL4 maintain an inactive state at the logic low level L, and the second, third, and fourth conversion units CU2, CU3, CU4) can all select terminal '1'.

As a result, the first, second, and third main signals MS1 , MS2 , MS3 and the sub-signal SS are the input/output nodes ND1 , ND2 , and ND3 of the internal circuit as in the case where the bad signal path is not included. , ND4) can be transmitted respectively.

For example, as shown in FIG. 21B , the second main signal path MSP2 may be a bad signal path. In this case, the first main signal MS1 is transmitted through the first main signal path MSP1 , the second main signal MS2 is transmitted through the repair signal path RSP, and the third main signal MS3 is transmitted through the repair signal path RSP. may be transmitted through the third main signal path MSP3, and the sub signal SS may be transmitted through the sub signal path SSP. The mode signal MD may have a logic low level L to indicate the second repair mode using the repair signal path. The second path selection signal PSL2 may be activated to a logic high level H, and the second conversion unit CU2 may select the terminal '3'. All of the first, third, and fourth path selection signals PSL1 , PSL3 and PSL4 maintain an inactive state at the logic low level L, and the first, third, and fourth conversion units CU1, CU3, CU4) can all select terminal '1'. As a result, the first, second, and third main signals MS1 , MS2 , MS3 and the sub-signal SS are the input/output nodes ND1 , ND2 , and ND3 of the internal circuit as in the case where the bad signal path is not included. , ND4) can be transmitted respectively.

21A and 21B , in the second repair mode supporting the repair signal path, the bad signal path may be repaired using the repair signal path. The repair circuit including the path conversion circuit 302 of FIG. 14 performs a multiplexing repair operation to replace the defective input/output terminal corresponding to the defective signal path among the normal input/output terminals TN1, TN2, TN3, and TN4 to the repair input/output terminal ( TR) can be used to repair it. The transmission of the sub-signal SS is maintained, and a sub-operation using the sub-signal SS can also be performed. The block control signal BLK is, for example, deactivated to the logic low level L, and the fourth conversion unit CU4 corresponding to the sub conversion unit and the fourth input/output node ND4 of the internal circuit may be electrically connected. .

22 is a diagram illustrating an embodiment of a repair control unit for providing path selection signals to the path converting circuit of FIG. 14 , and FIG. 23 is a view for explaining the overall operation of the repair circuit including the path converting circuit of FIG. 14 am.

The bad information signal FLI may include a plurality of bit signals FLI1 , FLI2 , FLI3 , and FLI4 respectively corresponding to normal signal paths. 22 and 23 , bit signals FLI1 , FLI2 , FLI3 , FLI4 indicate that the corresponding normal signal path is not bad when the logic low level (L) and the corresponding normal when the logic high level (H). It may indicate that the signal path is bad. The path selection signals PSL1, PSL2, PSL3, and PSL4 are at the logic low level L when the corresponding conversion unit selects the terminal '1' and the logic level of the mode signal MD when the logic high level H. Accordingly, the corresponding conversion unit can select either terminal '2' or terminal '3'. The mode signal MD may indicate a first repair mode in which the repair signal path is not used when the logic high level (H) and the second repair mode using the repair signal path when the logic low level (L). . In FIG. 23 , cases 1 to 5 indicate a first repair mode not using a repair signal path, and cases 6 to 10 indicate a second repair mode using a repair signal path.

The definition of the logic level of the signals is an example for convenience of description, and the logic level of the signals may be defined in various ways according to the circuit configuration.

Referring to FIG. 22 , the repair control unit 202 may include first, second, third and fourth buffers 221 , 222 , 223 , 224 , an OR gate 225 and an OR gate 226 . can The first buffer 221 buffers the first bit signal FLI1 to generate the first path selection signal PSL1 . The second buffer 222 generates the second path selection signal PSL2 by buffering the second bit signal FLI2 of the bad information signal FLI. The third buffer 223 generates a third path selection signal PSL3 by buffering the third bit signal FLI3 of the bad information signal FLI. The fourth buffer 224 generates the fourth path selection signal PSL4 by buffering the fourth bit signal FLI4 of the bad information signal FLI. The OR gate 225 performs an OR operation on the first, second, third, and fourth path selection signals PSL1 , PSL2 , PSL3 , and PSL4 and outputs the OR operation. The AND gate 226 generates a block control signal BLK by performing an OR operation on the output of the OR gate 225 and the mode signal MD. In another embodiment, the buffers 221 , 222 , 223 , and 224 are omitted and the first, second, third and fourth bit signals FLI1 , FLI2 , FLI3 , and FLI4 of the bad information signal FLI are They may be provided as the path selection signals PSL1, PSL2, PSL3, and PSL4 as they are.

Referring to FIG. 23 , according to the configuration of FIG. 22 , when the bit signal FLIi corresponding to the bad signal path is activated to the logic high level H, only the corresponding path selection signal PSLi has the logic high level H. is activated with When the first bit signal FLI1 is activated to the logic high level H, only the first path selection signal PSL1 is activated to the logic high level H, and the second bit signal FLI2 is activated to the logic high level H When activated as , the second path selection signal PSL2 is activated to a logic high level H, and when the third bit signal FLI3 is activated to a logic high level H, only the third path selection signal PSL3 is activated to a logic high level H. When the level H is activated and the fourth bit signal FLI4 is activated at the logic high level H, only the fourth path selection signal PSL4 is activated at the logic high level H. When a bad signal path occurs using the path selection signals PSL1, PSL2, PSL3, and PSL4, the multiplexing repair replaces each signal path with a sub signal path or a repair signal path according to the logic level of the mode signal MD. action can be performed.

At least one bad signal path exists in the block control signal BLK so that the output of the OR gate 225 is activated to a logic high level (H) and the mode signal (MD) is a logic high level (H) to make a repair signal path. When indicating the unused first repair mode, it has a logic high level (H). In other cases, the block control signal BLK has a logic low level L.

In this way, the path control signal PCON, that is, the path selection signals PSL1, PSL2, PSL3, and PSL4, and the block control signal BLK may be generated based on the mode signal MD and the failure information signal FLI. . Using the path control signal PCON, the multiplexing repair operation is performed in the first repair mode that does not use the repair signal path as described with reference to FIGS. 18, 19A and 19B, or see FIGS. 20, 21A and 21B As described above, the multiplexing repair operation may be performed in the second repair mode using the repair signal path.

24 is a block diagram illustrating a path conversion circuit performing a shifting repair operation according to embodiments of the present invention.

Referring to FIG. 24 , the path conversion circuit 302 may include a plurality of conversion units CU1 , CU2 , CU3 , CU4 and an initialization circuit 325 .

As described above, the conversion units CU1, CU2, CU3, and CU4 are input/output nodes ND1, ND2, ND3, ND4 of the internal circuit in response to each of the path selection signals PSL1, PSL2, PSL3, and PSL4. ) and performing a multiplexing repair operation for respectively controlling electrical connections between two or more input/output terminals of the input/output terminal unit 32 .

The initialization circuit 325 may be connected to the repair input/output terminal TR, and may apply the initialization voltage VINT to the repair input/output terminal TR in response to the mode signal MD. For example, the initialization circuit 325 may include an NMOS transistor. In this case, when the mode signal MD has a logic high level H and indicates the first repair mode in which the repair signal path and the repair input/output terminal TR are not used, the NMOS transistor is turned on to obtain an initialization voltage VINT. It may be applied to the repair input/output terminal TR. On the other hand, when the mode signal MD has a logic low level L and indicates the second repair mode using the repair signal path and the repair input/output terminal TR, the NMOS transistor is turned off and the repair input/output terminal TR is turned off. ) may be blocked from being applied to the initialization voltage VINT.

Conventionally, due to the problem of the floating state of the repair signal path, it is necessary to implement a system by separating the case in which the repair signal path is supported and the case in which the repair signal path is not supported. According to embodiments of the present invention, it is possible to implement an integrated system that can selectively apply various repair methods by using an initialization circuit that holds the initial state of the repair input/output terminal TR.

25 is a block diagram illustrating a path conversion circuit performing a shifting repair operation according to embodiments of the present invention.

Referring to FIG. 25 , the path conversion circuit 303 responds to each of the path selection signals PSL11, PSL12, PSL21, and PSL22, respectively, and input/output nodes of the input/output nodes ND11, ND12, ND21, and ND22 of the internal circuit. It may include a plurality of conversion units (CU11, CU12, CU21, CU22) (331, 332, 333, 334) for controlling the electrical connection between the two or more input/output terminals of the terminal unit 33, respectively. Although the first to fourth conversion units 331, 332, 333, and 334 are illustrated in FIG. 25 for convenience, the number of conversion units and input/output terminals may be variously changed.

The normal input/output terminals TN11, TN12, TN21, and TN22 may be grouped into a plurality of groups, and at least one repair input/output terminal may be independently allocated to each of the groups. For example, as shown in FIG. 25 , the first group includes first and second normal input/output terminals TN11 and TN12 , and the first repair input/output terminal TR1 is allocated to the first group, The second group may include the third and fourth normal input/output terminals TN21 and TN22 , and the second repair input/output terminal TR2 may be allocated to the second group.

As described above, the normal input/output terminals TN11 , TN12 , TN21 , and TN22 are main input/output terminals for transmitting main signals for the main operation of the internal circuit 20 of FIG. 1 and a sub of the internal circuit 20 . It may include at least one sub input/output terminal for transmitting a sub signal for operation. For example, in the configuration of FIG. 25 , the first and third normal input/output terminals TN11 and TN21 may be main input/output terminals, and the second and fourth normal input/output terminals TN12 and TN22 may be sub input/output terminals.

Each of the main conversion units 331 and 333 corresponding to the main input/output terminals TN11 and TN21 among the conversion units 331 , 332 , 333 and 334 corresponds to one of the normal input/output terminals TN11 , TN12 , TN21 and TN22 . may be connected to a normal input/output terminal and an adjacent normal input/output terminal. That is, the first conversion unit 331 is connected to the first normal input/output terminal TN11 and the second normal input/output terminal TN12 , and the third conversion unit 333 is connected to the third normal input/output terminal TN21 and the fourth normal input/output terminal TN21 . It may be connected to the input/output terminal TN22.

The sub conversion units 332 and 334 corresponding to the sub input/output terminals TN12 and TN22 among the conversion units 331, 332, 333, 334 are connected to the corresponding normal input/output terminal and the repair input/output terminal of the corresponding group. can That is, the second conversion unit 332 is connected to the second normal input/output terminal TN12 and the first repair input/output terminal TR1 , and the fourth conversion unit 334 includes the fourth normal input/output terminal TN22 and the second repair It may be connected to the input/output terminal TR2.

As described above, the repair control unit 200 of FIG. 2 may control the logic levels of the path selection signals PSL11, PSL12, PSL21, and PSL22 to perform the shifting repair operation, and the conversion units 331, 332, Each of 333 and 334 may be selectively connected to one of the two input/output terminals according to the respective logic levels of the path selection signals PSL1 , PSL2 , PSL3 , and PSL4 . When the path selection signal PSLi is deactivated to the first logic level (eg, logic low level), the terminal '1' is selected so that the conversion unit CUi is connected to the corresponding input/output terminal, and the path selection signal ( When PSLi) is activated to a second logic level (eg, a logic high level), terminal '2' is selected so that the conversion unit CUi may be connected to an adjacent input/output terminal.

26 is a block diagram illustrating a system including the path conversion circuit of FIG. 25 and not supporting a repair signal path.

Referring to FIG. 26 , the system 53a includes a first subsystem 13 , a second subsystem 63a , and a signal path part 43a connecting the first subsystem 13 and the second subsystem 63a. ) may be included.

The first subsystem 13 is configured in a first repair mode in which the repair input/output terminals TR1 and TR2 are not used and a second repair mode in which the repair input/output terminals TR1 and TR2 are used according to embodiments of the present invention. It has a configuration that can operate selectively in one of them. The first subsystem 13 may include an input/output terminal unit 33 , a repair control unit (RC) 203 , and a path conversion circuit 303 . The internal circuit of the first subsystem 13 is omitted for convenience.

The input/output terminal unit 33 is independently allocated to the normal input/output terminals TN11 and TN12 belonging to the first group, the normal input/output terminals TN21 and TN22 belonging to the second group, and the first and third groups. and repair input/output terminals TR1 and TR2. The repair control unit 203 may generate the path control signal PCON based on the mode signal MD and the failure information signal FLI. The path conversion circuit 303 may control the connection between the input/output terminal 33 and the internal circuit in response to the path control signal PCON.

As described above with reference to FIG. 25 , the path conversion circuit 303 responds to each of the path selection signals PSL11, PSL12, PSL21, and PSL22 to the input/output nodes ND11, ND12, ND21, and ND22 of the internal circuit. It may include a plurality of conversion units (CU11, CU12, CU21, CU22) for controlling each of and the electrical connection between the two or more input/output terminals of the input/output terminal unit 33, respectively.

The second subsystem 63a has a configuration that does not support the repair signal path. The second subsystem 63a may include an input/output terminal unit 73a, a repair control unit (RCa) 83a, and a path conversion circuit 93a. The internal circuit of the second subsystem 63a is omitted for convenience.

The input/output terminal unit 73a includes only the plurality of normal input/output terminals TN11a, TN12a, TN21a, and TN22a and does not include repair input/output terminals. The repair control unit 83a may generate the path control signal PCONa based on the failure information signal FLI. The path conversion circuit 93a may control the connection between the input/output terminal 73a and the internal circuit in response to the path control signal PCONa.

Similar to the path converting circuit 303 of the first subsystem 13, the path converting circuit 93a of the second subsystem 63a responds to each of the path selection signals to input and output each of the input/output nodes of the internal circuit. It may include a plurality of conversion units (CU11a, CU12a, CU21a, CU22a) for controlling the electrical connection between the two or more input/output terminals of the terminal unit 73a, respectively. However, since the input/output terminal unit 73a does not include the repair input/output terminals, the last conversion units CU12a and CU22a of each group are electrically connected between the input/output nodes of the internal circuit and the corresponding input/output terminals TN12a, TN22a, respectively. can be controlled

Since the second subsystem 63a is fixed to a configuration that does not support the repair signal path, the repair control unit 83a of the second subsystem 63a may not receive the mode signal MD. The failure information signal FLI provided to the first subsystem 13 and the failure information signal FLI provided to the second subsystem 63a may be the same.

The signal path unit 43a may include a plurality of normal signal paths MSP1, MSP2, SSP1, and SSP2, but may not include repair signal paths. The normal signal paths MSP1, MSP2, SSP1, and SSP2 are first and second main signal paths MSP1, MSP2) and first and second sub-signal paths SSP1 and SSP2 for transmitting sub-signals SS1 and SS2 for sub-operation of the first subsystem 13 may be included. Accordingly, the first and third normal input/output terminals TN11 and TN21 may be referred to as main input/output terminals, and the second and fourth normal input/output terminals TN12 and TN22 may be referred to as sub input/output terminals. . In addition, the first and third transformation units CU11 and CU21 may be referred to as main transformation units, and the second and fourth transformation units CU12 and CU22 may be referred to as sub transformation units.

FIG. 26 shows signal transmission when the bad signal path is not included in the normal signal paths MSP1, MSP2, SSP1, and SSP2. That is, when there is no bad signal path, the repair function is disabled, and the first and second main signals MS1 and MS2 are transmitted through the corresponding main signal paths MSP1 and MSP2, and the first and second sub signals are transmitted through the corresponding main signal paths MSP1 and MSP2. Signals SS1 and SS2 may be transmitted through corresponding sub-signal paths SSP1 and SSP2.

27A and 27B are diagrams for explaining a repair operation of the system of FIG. 26 .

For example, as shown in FIG. 27A , the second main signal path MSP2 belonging to the second group may be a bad signal path. In this case, for the first group not including the bad signal path, the first main signal MS1 is transmitted through the first main signal path MSP1, and the first sub signal SS1 is the first sub signal path. (SSP1). For the second group including the bad signal path, the second main signal MS2 may be transmitted through the second sub signal path SSP2. The first and second path selection signals PSL11 and PSL12 maintain an inactive state at a logic low level L, and the first and second conversion units CU11 and CU12 may select the terminal '1'. have. The third and fourth path selection signals PSL21 and PSL33 may be activated to a logic high level H, and the third and fourth conversion units CU21 and CU22 may select the terminal '2'. As a result, the first and second main signals MS1 and MS2 may be respectively transmitted through the input/output nodes ND11 and ND21 of the internal circuit as in the case where the bad signal path is not included. The first sub-signal SS1 may be transmitted through the input/output node ND12 of the internal circuit as in the case where the bad signal path is not included, but the transmission of the second sub-signal SS2 is stopped and the second sub-signal ( The sub operation using SS2) is stopped. The first block control signal BLK1 maintains an inactive state at the logic low level L, and the second conversion unit CU12 corresponding to the sub conversion unit and the second input/output node ND12 of the internal circuit are electrically connected. can The second block control signal BLK2 is activated to a logic high level H, and the electrical connection between the fourth conversion unit CU22 corresponding to the sub conversion unit and the fourth input/output node ND22 of the internal circuit is blocked or may be disabled.

For example, as shown in FIG. 27B , the first main signal path MSP1 belonging to the first group and the second sub signal path SSP2 belonging to the second group may be bad signal paths. In this case, for the first group, the first main signal MS1 is transmitted through the first sub-signal path SSP1, and for the second group, the second main signal MS2 is transmitted through the second main signal path MSP2. can be transmitted through The first, second and fourth path selection signals PSL11, PSL12, and PSL22 are activated to a logic high level H, and the first, second and fourth conversion units CU11, CU12, CU22 are connected to the terminal ' 2' can be selected. The third path selection signal PSL21 may maintain a deactivated state at the logic low level L, and the third conversion unit CU21 may select the terminal '1'. As a result, the first and second main signals MS1 and MS2 may be respectively transmitted through the input/output nodes ND11 and ND21 of the internal circuit as in the case where the bad signal path is not included. Transmission of the first and second sub-signals SS1 and SS2 is stopped, and sub-operations using the first and second sub-signals SS1 and SS2 are stopped. The first and second block control signals BLK1 and BLK2 are activated to a logic high level H, and the second and fourth conversion units CU12 and CU22 corresponding to the sub conversion unit and the second and second blocks of the internal circuit An electrical connection between the fourth input/output nodes ND12 and ND22 may be blocked or disabled.

27A and 27B , in the first repair mode that does not support the repair signal path, the bad signal path may be repaired using the sub signal path. The repair circuit including the path conversion circuit 303 of FIG. 25 performs a shifting repair operation for each group, thereby converting the defective input/output terminal corresponding to the defective signal path among the main input/output terminals TN11 and TN21 to the sub input/output terminals. (TN12, TN22) can be used to repair.

28 is a block diagram illustrating a system including the path conversion circuit of FIG. 25 and supporting a repair signal path.

Referring to FIG. 28 , the system 53b includes a first subsystem 13 , a second subsystem 63b , and a signal path part 43b connecting the first subsystem 13 and the second subsystem 63b. ) may be included.

The first subsystem 13 is configured in a first repair mode in which the repair input/output terminals TR1 and TR2 are not used and a second repair mode in which the repair input/output terminals TR1 and TR2 are used according to embodiments of the present invention. It has a configuration that can operate selectively in one of them. The first subsystem 13 may include an input/output terminal unit 33 , a repair control unit (RC) 203 , and a path conversion circuit 303 . The internal circuit of the first subsystem 13 is omitted for convenience.

The input/output terminal unit 33 is independently allocated to the normal input/output terminals TN11 and TN12 belonging to the first group, the normal input/output terminals TN21 and TN22 belonging to the second group, and the first and second groups. and repair input/output terminals TR1 and TR2. The repair control unit 203 may generate the path control signal PCON based on the mode signal MD and the failure information signal FLI. The path conversion circuit 303 may control the connection between the input/output terminal 33 and the internal circuit in response to the path control signal PCON.

As described above with reference to FIG. 25 , the path conversion circuit 303 responds to each of the path selection signals PSL11, PSL12, PSL21, and PSL22 to the input/output nodes ND11, ND12, ND21, and ND22 of the internal circuit. It may include a plurality of conversion units (CU11, CU12, CU21, CU22) for controlling each of and the electrical connection between the two or more input/output terminals of the input/output terminal unit 33, respectively.

The second subsystem 63b has a configuration that supports the repair signal path. The second subsystem 63b may include an input/output terminal unit 73b, a repair control unit (RCa) 83b, and a path conversion circuit 93b. The internal circuit of the second subsystem 63b is omitted for convenience.

The input/output terminal unit 73b includes a plurality of normal input/output terminals TN11b, TN12b, TN21b, and TN22b and repair input/output terminals TR1b and TT2b. The repair control unit 83b may generate the path control signal PCONb based on the failure information signal FLI. The path conversion circuit 93b may control the connection between the input/output terminal 73b and the internal circuit in response to the path control signal PCONb.

Similar to the path converting circuit 303 of the first subsystem 13, the path converting circuit 93b of the second subsystem 63b responds to each of the path selection signals to each of the input/output nodes of the internal circuit and input/output. It may include a plurality of conversion units (CU11b, CU12b, CU21b, CU22b) for controlling the electrical connection between the two or more input/output terminals of the terminal unit 73b, respectively.

Since the second subsystem 63b is fixed to a configuration supporting the repair signal path, the repair control unit 83b of the second subsystem 63b may not receive the mode signal MD. The failure information signal FLI provided to the first subsystem 13 and the failure information signal FLI provided to the second subsystem 63b may be the same.

The signal path unit 43b may include a plurality of normal signal paths MSP1, MSP2, SSP1, and SSP2 and repair signal paths RSP1 and RSP2. The normal signal paths MSP1, MSP2, SSP1, and SSP2 are first and second main signal paths MSP1, MSP2) and first and second sub-signal paths SSP1 and SSP2 for transmitting sub-signals SS1 and SS2 for sub-operation of the first subsystem 13 may be included. Accordingly, the first and third normal input/output terminals TN11 and TN21 may be referred to as main input/output terminals, and the second and fourth normal input/output terminals TN12 and TN22 may be referred to as sub input/output terminals. . In addition, the first and third transformation units CU11 and CU21 may be referred to as main transformation units, and the second and fourth transformation units CU12 and CU22 may be referred to as sub transformation units.

FIG. 28 shows signal transmission when the bad signal path is not included in the normal signal paths MSP1, MSP2, SSP1, and SSP2. That is, when there is no bad signal path, the repair function is disabled, and the first and second main signals MS1 and MS2 are transmitted through the corresponding main signal paths MSP1 and MSP2, and the first and second sub signals are transmitted through the corresponding main signal paths MSP1 and MSP2. Signals SS1 and SS2 may be transmitted through corresponding sub-signal paths SSP1 and SSP2.

29A and 29B are diagrams for explaining a repair operation of the system of FIG. 28 .

For example, as shown in FIG. 29A , the second main signal path MSP2 belonging to the second group may be a bad signal path. In this case, for the first group not including the bad signal path, the first main signal MS1 is transmitted through the first main signal path MSP1, and the first sub signal SS1 is the first sub signal path. (SSP1). For the second group including the bad signal path, the second main signal MS2 is transmitted through the second sub-signal path SSP2, and the second sub-signal SS2 is transmitted through the second repair signal path RSP2. can be transmitted through The first and second path selection signals PSL11 and PSL12 maintain an inactive state at a logic low level L, and the first and second conversion units CU11 and CU12 may select the terminal '1'. have. The third and fourth path selection signals PSL21 and PSL22 may be activated to a logic high level H, and the third and fourth conversion units CU21 and CU22 may select the terminal '2'. As a result, the first and second main signals MS1 and MS2 and the first and second sub-signals SS1 and SS2 are input/output nodes ND11, ND12, ND21, and ND22) respectively.

For example, as shown in FIG. 29B , the first main signal path MSP1 belonging to the first group and the second sub signal path SSP2 belonging to the second group may be bad signal paths. In this case, for the first group, the first main signal MS1 is transmitted through the first sub-signal path SSP1 and the first sub-signal SS1 is transmitted through the first repair signal path RSP1, For the two groups, the second main signal MS2 may be transmitted through the second main signal path MSP2 , and the second sub-signal SS2 may be transmitted through the second repair signal path RSP2 . The first, second and fourth path selection signals PSL11, PSL12, and PSL22 are activated to a logic high level H, and the first, second and fourth conversion units CU11, CU12, CU22 are connected to the terminal ' 2' can be selected. The third path selection signal PSL21 may maintain a deactivated state at the logic low level L, and the third conversion unit CU21 may select the terminal '1'. As a result, the first and second main signals MS1 and MS2 and the first and second sub-signals SS1 and SS2 are input/output nodes ND11, ND12, ND21, and ND22) respectively.

29A and 29B , in the second repair mode supporting the repair signal path, the bad signal path may be repaired using the repair signal paths allocated to each of the groups. The repair circuit including the path conversion circuit 303 of FIG. 25 performs a shifting repair operation for each group, thereby replacing the defective input/output terminals corresponding to the defective signal path among the normal input/output terminals TN11, TN12, TN21, and TN22. Repair may be performed using the repair input/output terminals TR1 and TR2. Transmission of the sub-signals SS1 and SS2 is maintained, and sub-operations using the sub-signals SS1 and SS2 can also be performed. The first and second block control signals BLK1 and BLK2 are deactivated to, for example, a logic low level L, and the second and fourth conversion units CU12 and CU22 corresponding to the sub conversion unit and the internal circuit The second and fourth input/output nodes ND12 and ND22 may be electrically connected to each other.

30 is a block diagram illustrating a path conversion circuit performing a shifting repair operation according to embodiments of the present invention.

Referring to FIG. 30 , the path conversion circuit 304 responds to each of the path selection signals PSL11, PSL12, PSL21, and PSL22, respectively, and input/output nodes of the input/output nodes ND11, ND12, ND21, and ND22 of the internal circuit. It may include a plurality of conversion units (CU11, CU12, CU21, CU22) (341, 342, 343, 344) for controlling the electrical connection between the two or more input/output terminals of the terminal unit 34, respectively. Although the first to fourth conversion units 341, 342, 343, and 344 are illustrated in FIG. 30 for convenience, the number of conversion units and input/output terminals may be variously changed.

The normal input/output terminals TN11 , TN12 , TN21 , and TN22 may be grouped into a plurality of groups, and at least one repair input/output terminal may be commonly assigned to the groups. For example, as shown in FIG. 30 , the first group includes first and second normal input/output terminals TN11 and TN12, and the second group includes third and fourth normal input/output terminals TN21 and TN12. TN22), and the repair input/output terminal TR may be commonly allocated to the second group and the second group.

As described above, the normal input/output terminals TN11 , TN12 , TN21 , and TN22 are main input/output terminals for transmitting main signals for the main operation of the internal circuit 20 of FIG. 1 and a sub of the internal circuit 20 . It may include at least one sub input/output terminal for transmitting a sub signal for operation. For example, in the configuration of FIG. 30 , the first and third normal input/output terminals TN11 and TN21 may be main input/output terminals, and the second and fourth normal input/output terminals TN12 and TN22 may be sub input/output terminals.

Each of the main conversion units 341 and 343 corresponding to the main input/output terminals TN11 and TN21 among the conversion units 341 , 342 , 343 and 344 corresponds to one of the normal input/output terminals TN11 , TN12 , TN21 and TN22 . may be connected to a normal input/output terminal and an adjacent normal input/output terminal. That is, the first conversion unit 341 is connected to the first normal input/output terminal TN11 and the second normal input/output terminal TN12 , and the third conversion unit 343 is connected to the third normal input/output terminal TN21 and the fourth normal input/output terminal TN21 . It may be connected to the input/output terminal TN22.

Among the conversion units 341 , 342 , 343 , and 344 , the sub conversion units 342 and 344 corresponding to the sub input/output terminals TN12 and TN22 may be connected to the corresponding normal input/output terminal and the common repair input/output terminal. That is, the second conversion unit 342 is connected to the second normal input/output terminal TN12 and the repair input/output terminal TR, and the fourth conversion unit 344 is connected to the fourth normal input/output terminal TN22 and the common repair input/output terminal ( TR) can be connected.

As described above, the repair control unit 200 of FIG. 2 may control the logic levels of the path selection signals PSL11, PSL12, PSL21, and PSL22 to perform the shifting repair operation, and the conversion units 341, 342, Each of 343 and 344 may be selectively connected to one of the two input/output terminals according to the respective logic levels of the path selection signals PSL1 , PSL2 , PSL3 , and PSL4 . When the path selection signal PSLi is deactivated to the first logic level (eg, logic low level), the terminal '1' is selected so that the conversion unit CUi is connected to the corresponding input/output terminal, and the path selection signal ( When PSLi) is activated to a second logic level (eg, a logic high level), terminal '2' is selected so that the conversion unit CUi may be connected to an adjacent input/output terminal.

31 is a block diagram illustrating a system including the path conversion circuit of FIG. 30 and not supporting a repair signal path.

Referring to FIG. 31 , the system 54a includes a first subsystem 14 , a second subsystem 64a , and a signal path part 44a connecting the first subsystem 14 and the second subsystem 64a. ) may be included.

The first subsystem 14 selectively operates in one of a first repair mode not using the repair input/output terminal TR and a second repair mode using the repair input/output terminal TR according to embodiments of the present invention You have a configuration that you can do. The first subsystem 14 may include an input/output terminal unit 34 , a repair control unit (RC) 204 , and a path conversion circuit 304 . The internal circuit of the first subsystem 14 is omitted for convenience.

The input/output terminal unit 34 includes the normal input/output terminals TN11 and TN12 belonging to the first group, the normal input/output terminals TN21 and TN22 belonging to the second group, and the repair commonly allocated to the first and second groups. It includes an input/output terminal TR. The repair control unit 204 may generate the path control signal PCON based on the mode signal MD and the failure information signal FLI. The path conversion circuit 304 may control the connection between the input/output terminal unit 34 and the internal circuit in response to the path control signal PCON.

As described above with reference to FIG. 30 , the path conversion circuit 304 responds to each of the path selection signals PSL11, PSL12, PSL21, and PSL22 to the input/output nodes ND11, ND12, ND21, and ND22 of the internal circuit. It may include a plurality of conversion units (CU11, CU12, CU21, CU22) for controlling each of and the electrical connection between the two or more input/output terminals of the input/output terminal unit 34, respectively.

The second subsystem 64a has a configuration that does not support the repair signal path. The second subsystem 64a may include an input/output terminal unit 74a, a repair control unit (RCa) 84a, and a path conversion circuit 94a. The internal circuit of the second subsystem 64a is omitted for convenience.

The input/output terminal unit 74a includes only the plurality of normal input/output terminals TN11a, TN12a, TN21a, and TN22a and does not include repair input/output terminals. The repair control unit 84a may generate the path control signal PCONa based on the failure information signal FLI. The path conversion circuit 94a may control the connection between the input/output terminal 74a and the internal circuit in response to the path control signal PCONa.

Similar to the path converting circuit 304 of the first subsystem 14, the path converting circuit 94a of the second subsystem 64a is responsive to each of the path selection signals to input and output each of the input and output nodes of the internal circuit. It may include a plurality of conversion units (CU11a, CU12a, CU21a, CU22a) for controlling the electrical connection between the two or more input/output terminals of the terminal unit 74a, respectively. However, since the input/output terminal unit 74a does not include the repair input/output terminals, the last conversion units CU12a and CU22a of each group are electrically connected between the input/output nodes of the internal circuit and the corresponding input/output terminals TN12a, TN22a, respectively. can be controlled

Since the second subsystem 64a is fixed to a configuration that does not support the repair signal path, the repair control unit 84a of the second subsystem 64a may not receive the mode signal MD. The failure information signal FLI provided to the first subsystem 14 and the failure information signal FLI provided to the second subsystem 64a may be the same.

The signal path unit 44a may include a plurality of normal signal paths MSP1, MSP2, SSP1, and SSP2, but may not include a repair signal path. The normal signal paths MSP1, MSP2, SSP1, and SSP2 are first and second main signal paths MSP1, MSP2) and first and second sub-signal paths SSP1 and SSP2 for transmitting sub-signals SS1 and SS2 for sub-operations of the first subsystem 14 . Accordingly, the first and third normal input/output terminals TN11 and TN21 may be referred to as main input/output terminals, and the second and fourth normal input/output terminals TN12 and TN22 may be referred to as sub input/output terminals. . In addition, the first and third transformation units CU11 and CU21 may be referred to as main transformation units, and the second and fourth transformation units CU12 and CU22 may be referred to as sub transformation units.

FIG. 31 shows signal transmission when the bad signal path is not included in the normal signal paths MSP1, MSP2, SSP1, and SSP2. That is, when there is no bad signal path, the repair function is disabled, and the first and second main signals MS1 and MS2 are transmitted through the corresponding main signal paths MSP1 and MSP2, and the first and second sub signals are transmitted through the corresponding main signal paths MSP1 and MSP2. Signals SS1 and SS2 may be transmitted through corresponding sub-signal paths SSP1 and SSP2.

32A and 32B are diagrams for explaining a repair operation of the system of FIG. 31 .

For example, as shown in FIG. 32A , the second main signal path MSP2 belonging to the second group may be a bad signal path. In this case, for the first group not including the bad signal path, the first main signal MS1 is transmitted through the first main signal path MSP1, and the first sub signal SS1 is the first sub signal path. (SSP1). For the second group including the bad signal path, the second main signal MS2 may be transmitted through the second sub signal path SSP2. The first and second path selection signals PSL11 and PSL12 maintain an inactive state at a logic low level L, and the first and second conversion units CU11 and CU12 may select the terminal '1'. have. The third and fourth path selection signals PSL21 and PSL33 may be activated to a logic high level H, and the third and fourth conversion units CU21 and CU22 may select the terminal '2'. As a result, the first and second main signals MS1 and MS2 may be respectively transmitted through the input/output nodes ND11 and ND21 of the internal circuit as in the case where the bad signal path is not included. The first sub-signal SS1 may be transmitted through the input/output node ND12 of the internal circuit as in the case where the bad signal path is not included, but the transmission of the second sub-signal SS2 is stopped and the second sub-signal ( The sub operation using SS2) is stopped. The first block control signal BLK1 maintains an inactive state at the logic low level L, and the second conversion unit CU12 corresponding to the sub conversion unit and the second input/output node ND12 of the internal circuit are electrically connected. can The second block control signal BLK2 is activated to a logic high level H, and the electrical connection between the fourth conversion unit CU22 corresponding to the sub conversion unit and the fourth input/output node ND22 of the internal circuit is blocked or may be disabled.

For example, as shown in FIG. 32B , the first main signal path MSP1 belonging to the first group and the second sub signal path SSP2 belonging to the second group may be bad signal paths. In this case, for the first group, the first main signal MS1 is transmitted through the first sub-signal path SSP1, and for the second group, the second main signal MS2 is transmitted through the second main signal path MSP2. can be transmitted through The first, second and fourth path selection signals PSL11, PSL12, and PSL22 are activated to a logic high level H, and the first, second and fourth conversion units CU11, CU12, CU22 are connected to the terminal ' 2' can be selected. The third path selection signal PSL21 may maintain a deactivated state at the logic low level L, and the third conversion unit CU21 may select the terminal '1'. As a result, the first and second main signals MS1 and MS2 may be respectively transmitted through the input/output nodes ND11 and ND21 of the internal circuit as in the case where the bad signal path is not included. Transmission of the first and second sub-signals SS1 and SS2 is stopped, and sub-operations using the first and second sub-signals SS1 and SS2 are stopped. The first and second block control signals BLK1 and BLK2 are activated to a logic high level H, and the second and fourth conversion units CU12 and CU22 corresponding to the sub conversion unit and the second and second blocks of the internal circuit An electrical connection between the fourth input/output nodes ND12 and ND22 may be blocked or disabled.

32A and 32B , in the first repair mode that does not support the repair signal path, the bad signal path may be repaired using the sub signal path. The repair circuit including the path conversion circuit 304 of FIG. 30 performs a shifting repair operation for each group, thereby replacing the defective input/output terminal corresponding to the defective signal path among the normal input/output terminals TN11, TN12, TN21, and TN22. The repair may be performed using the sub input/output terminals TN21 and TN22.

33 is a block diagram illustrating a system including the path conversion circuit of FIG. 30 and supporting a repair signal path.

Referring to FIG. 33 , the system 54b includes a first subsystem 14 , a second subsystem 64b , and a signal path part 44b connecting the first subsystem 14 and the second subsystem 64b. ) may be included.

The first subsystem 14 selectively operates in one of a first repair mode not using the repair input/output terminal TR and a second repair mode using the repair input/output terminal TR according to embodiments of the present invention You have a configuration that you can do. The first subsystem 14 may include an input/output terminal unit 34 , a repair control unit (RC) 204 , and a path conversion circuit 304 . The internal circuit of the first subsystem 14 is omitted for convenience.

The input/output terminal unit 34 includes the normal input/output terminals TN11 and TN12 belonging to the first group, the normal input/output terminals TN21 and TN22 belonging to the second group, and the repair commonly allocated to the first and second groups. It includes an input/output terminal TR. The repair control unit 204 may generate the path control signal PCON based on the mode signal MD and the failure information signal FLI. The path conversion circuit 304 may control the connection between the input/output terminal unit 34 and the internal circuit in response to the path control signal PCON.

As described above with reference to FIG. 30 , the path conversion circuit 304 responds to each of the path selection signals PSL11, PSL12, PSL21, and PSL22 to the input/output nodes ND11, ND12, ND21, and ND22 of the internal circuit. It may include a plurality of conversion units (CU11, CU12, CU21, CU22) for controlling each of and the electrical connection between the two or more input/output terminals of the input/output terminal unit 34, respectively.

The second subsystem 64b has a configuration that supports the repair signal path. The second subsystem 64b may include an input/output terminal unit 74b, a repair control unit (RCa) 84b, and a path conversion circuit 94b. The internal circuit of the second subsystem 64b is omitted for convenience.

The input/output terminal unit 74b includes a plurality of normal input/output terminals TN11b, TN12b, TN21b, and TN22b and a common repair input/output terminal TRb. The repair control unit 84b may generate the path control signal PCONb based on the failure information signal FLI. The path conversion circuit 94b may control the connection between the input/output terminal 74b and the internal circuit in response to the path control signal PCONb.

Similar to the path converting circuit 304 of the first subsystem 14, the path converting circuit 94b of the second subsystem 64b is responsive to each of the path selection signals to input and output each of the input and output nodes of the internal circuit. It may include a plurality of conversion units (CU11b, CU12b, CU21b, CU22b) for controlling the electrical connection between the two or more input/output terminals of the terminal unit 74b, respectively.

Since the second subsystem 64b is fixed to a configuration supporting the repair signal path, the repair control unit 84b of the second subsystem 64b may not receive the mode signal MD. The failure information signal FLI provided to the first subsystem 14 and the failure information signal FLI provided to the second subsystem 64b may be the same.

The signal path unit 44b may include a plurality of normal signal paths MSP1, MSP2, SSP1, and SSP2 and a repair signal path RSP. The normal signal paths MSP1, MSP2, SSP1, and SSP2 are first and second main signal paths MSP1, MSP2) and first and second sub-signal paths SSP1 and SSP2 for transmitting sub-signals SS1 and SS2 for sub-operations of the first subsystem 14 . Accordingly, the first and third normal input/output terminals TN11 and TN21 may be referred to as main input/output terminals, and the second and fourth normal input/output terminals TN12 and TN22 may be referred to as sub input/output terminals. . In addition, the first and third transformation units CU11 and CU21 may be referred to as main transformation units, and the second and fourth transformation units CU12 and CU22 may be referred to as sub transformation units.

FIG. 33 shows signal transmission when the bad signal path is not included in the normal signal paths MSP1, MSP2, SSP1, and SSP2. That is, when there is no bad signal path, the repair function is disabled, and the first and second main signals MS1 and MS2 are transmitted through the corresponding main signal paths MSP1 and MSP2, and the first and second sub signals are transmitted through the corresponding main signal paths MSP1 and MSP2. Signals SS1 and SS2 may be transmitted through corresponding sub-signal paths SSP1 and SSP2.

34A and 34B are diagrams for explaining a repair operation of the system of FIG. 33 .

For example, as shown in FIG. 34A , the second main signal path MSP2 belonging to the second group may be a bad signal path. In this case, for the first group not including the bad signal path, the first main signal MS1 is transmitted through the first main signal path MSP1, and the first sub signal SS1 is the first sub signal path. (SSP1). For the second group including the bad signal path, the second main signal MS2 is transmitted through the second sub signal path SSP2 and the second sub signal SS2 is transmitted through the repair signal path RSP. can be The first and second path selection signals PSL11 and PSL12 maintain an inactive state at a logic low level L, and the first and second conversion units CU11 and CU12 may select the terminal '1'. have. The third and fourth path selection signals PSL21 and PSL22 may be activated to a logic high level H, and the third and fourth conversion units CU21 and CU22 may select the terminal '2'. As a result, the first and second main signals MS1 and MS2 and the first and second sub-signals SS1 and SS2 are input/output nodes ND11, ND12, ND21, and ND22) respectively. The first and second block control signals BLK1 and BLK2 maintain an inactive state at a logic low level L, and the second and fourth conversion units CU12 and CU22 corresponding to the sub conversion unit and the second block of the internal circuit The second and fourth input/output nodes ND12 and ND22 may be electrically connected to each other.

For example, as shown in FIG. 34B , the first main signal path MSP1 belonging to the first group and the second sub signal path SSP2 belonging to the second group may be bad signal paths. In this case, for the first group, the first main signal MS1 is transmitted through the first sub-signal path SSP1 and the first sub-signal SS1 is transmitted through the repair signal path RSP, and the second group For , the second main signal MS2 may be transmitted through the second main signal path MSP2. The first, second and fourth path selection signals PSL11, PSL12, and PSL22 are activated to a logic high level H, and the first, second and fourth conversion units CU11, CU12, CU22 are connected to the terminal ' 2' can be selected. The third path selection signal PSL21 may maintain a deactivated state at the logic low level L, and the third conversion unit CU21 may select the terminal '1'. As a result, the first and second main signals MS1 and MS2 may be respectively transmitted through the input/output nodes ND11 and ND21 of the internal circuit as in the case where the bad signal path is not included. The first sub-signal SS1 may be transmitted through the input/output node ND12 of the internal circuit as in the case where the bad signal path is not included, but the transmission of the second sub-signal SS2 is stopped and the second sub-signal ( The sub operation using SS2) is stopped. The first block control signal BLK1 maintains an inactive state at the logic low level L, and the second conversion unit CU12 corresponding to the sub conversion unit and the second input/output node ND12 of the internal circuit are electrically connected. can The second block control signal BLK2 is activated to a logic high level H, and the electrical connection between the fourth conversion unit CU22 corresponding to the sub conversion unit and the fourth input/output node ND22 of the internal circuit is blocked or may be disabled.

34A and 34B , in the second repair mode supporting the repair signal path, the bad signal path may be repaired using the repair signal path commonly allocated to the groups. The repair circuit including the path conversion circuit 304 of FIG. 30 performs a shifting repair operation for each group, thereby repairing the defective input/output terminals corresponding to the defective signal path among the normal input/output terminals TN11, TN12, TN21, and TN22. Repair may be performed using the repair input/output terminal TR.

In the above, embodiments in which the shifting repair operation as described with reference to FIGS. 3 to 13 is applied to a case in which normal input/output terminals are grouped into a plurality of groups have been described with reference to FIGS. 25 to 34B. It will be appreciated that the multiplexing repair operation as described with reference to FIGS. 14 to 24 may be applied to a case in which normal input/output terminals are grouped into a plurality of groups in a similar manner.

35 is a block diagram illustrating a memory system including a repair circuit according to embodiments of the present invention.

Referring to FIG. 35 , the memory system 400 may include a memory controller 401 and a memory device 402 . Internal circuits that perform respective unique functions of the memory controller 401 and the memory device 402 are omitted for convenience.

Each of the memory controller 401 and the memory device 402 includes input/output terminal units IOPAD, and a command-address signal CMD/ADD and data DATA through signal paths connecting the input/output terminal units IOPAD. can pass The memory controller 401 and the memory device 402 may include repair circuits REP or interface circuits respectively connected to the input/output terminal units IOPAD. At least one of the repair circuits REP may be an adaptive repair circuit capable of efficiently repairing systems employing different repair methods according to embodiments of the present invention as described above.

The memory controller 401 may include a built-in self-test circuit (BIST) that provides the failure information. The built-in self-test circuit BIST may test whether signal paths connecting the memory controller 401 and the memory device 402 are defective and provide failure information when the memory system 400 is rebooted.

The memory device 402 may include a serial-presence detect (SPD) device and/or a mode register set (MRS). Product information of the memory device 402 may be stored in an SPD or an electrically-erasable-programmable read-only memory (EEPROM) device that is typically included in a memory device, a memory module, or the like. The SPD may store data characterizing various properties of a memory device or a memory module. For example, the SPD device (SPD) stores information on a repair method supported by the memory device (402), and the SPD device (SPD) is the memory controller (401) of the memory system (400) or the memory system ( 400) may provide information about the repair method to a basic input-output system (BIOS) of the computing system including the computer. The built-in self-test circuit BIST may provide failure information of signal paths to the memory device 402 as well as the internal control circuit of the memory controller 401 , and the provided failure information is stored in the mode register set MRS. can be

36 is a block diagram illustrating an example of an internal configuration of a memory device included in the memory system of FIG. 35 .

Referring to FIG. 36 , the internal circuit 403 of the memory device includes a control logic 410 , an address register 420 , a bank control logic 430 , a row address multiplexer 440 , a column address latch 450 , and a row decoder. 460 , a column decoder 470 , a memory cell array 480 , a sense amplifier unit 485 , an input/output gating circuit 490 , a data input/output buffer 495 , and a refresh counter 445 .

The memory cell array 480 may include a plurality of bank arrays 480a to 480h. The row decoder 460 includes a plurality of bank row decoders 460a to 460h respectively connected to the plurality of bank arrays 480a to 480h, and the column decoder 470 includes a plurality of bank arrays 480a to 480h. includes a plurality of column decoders 470a to 470h respectively connected to can

The address register 420 may receive an address signal ADD including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller. The address register 420 provides the received bank address BANK_ADDR to the bank control logic 430 , the received row address ROW_ADDR to the row address multiplexer 440 , and the received column address COL_ADDR It may be provided to the column address latch 450 .

The bank control logic 430 may generate bank control signals in response to the bank address BANK_ADDR. In response to the bank control signals, a bank row decoder corresponding to a bank address BANK_ADDR among the plurality of bank row decoders 460a to 460h is activated, and a bank address among the plurality of bank column decoders 470a to 470h is activated. A bank column decoder corresponding to (BANK_ADDR) may be activated.

The row address multiplexer 440 may receive a row address ROW_ADDR from the address register 220 and a refresh row address REF_ADDR from the refresh counter 445 . The row address multiplexer 440 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 440 may be applied to the bank row decoders 460a to 460h, respectively.

The bank row decoder activated by the bank control logic 430 among the bank row decoders 460a to 460h decodes the row address RA output from the row address multiplexer 440 to generate a word line corresponding to the row address. can be activated. For example, the activated bank row decoder may apply a word line driving voltage to a word line corresponding to a row address.

The column address latch 450 may receive the column address COL_ADDR from the address register 420 and temporarily store the received column address COL_ADDR. Also, the column address latch 450 may gradually increase the received column address COL_ADDR in a burst mode. The column address latch 450 may apply the temporarily stored or gradually increased column address COL_ADDR to the bank column decoders 470a to 470h, respectively.

The bank column decoder activated by the bank control logic 430 among the bank column decoders 470a to 470h activates the sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input/output gating circuit 490 . can do it

The input/output gating circuit 490 includes circuits for gating input/output data, input data mask logic, read data latches for storing data output from the bank arrays 480a to 480h, and the bank arrays 480a to 480a. 480h) and write drivers for writing data.

Data DQ to be read from one of the bank arrays 480a to 480h may be sensed by a sense amplifier corresponding to the one bank array and stored in the read data latches. The data DQ stored in the read data latches may be provided to the memory controller through the data input/output buffer 495 . Data DQ to be written to one of the bank arrays 480a to 480h may be provided from the memory controller to the data input/output buffer 495 . The data DQ provided to the data input/output buffer 495 may be written to the single bank array through the write drivers.

The control logic 410 may control the operation of the semiconductor memory device. For example, the control logic 410 may generate control signals to perform a write operation or a read operation on the semiconductor memory device. The control logic 410 may include a command decoder 411 for decoding a command CMD received from the memory controller and a mode register set (MRS) 412 for setting an operation mode of the semiconductor memory device. can

For example, the command decoder 411 may generate the control signals corresponding to the command CMD by decoding the write enable signal, the row address strobe signal, the column address strobe signal, the chip select signal, and the like. The mode register set 412 may store product information such as failure information of the aforementioned signal paths and a repair method of the memory controller 401 of FIG. 35 . In an embodiment, the above-described mode signal MD and/or the bad information signal FLI may be generated based on the information signal stored in the mode register set 412 .

37 is a diagram illustrating an example of a fuse circuit providing a mode signal.

Referring to FIG. 37 , the fuse circuit may be selectively programmed according to a repair method of an external device to provide the above-described mode signal MD. For example, the fuse circuit may be included in the memory device 402 of FIG. 35 , and may include a first fuse FS1 and a second fuse FS2 that are selectively programmed according to a repair method of the memory controller 401 . can For example, when the memory controller 401 coupled to the memory device 402 is a type that does not support the repair signal path, the first fuse FS1 is cut and the second fuse FS2 is electrically The connected mode signal MD may have a logic high level H corresponding to the power voltage VDD. On the other hand, when the memory controller 401 coupled to the memory device 402 supports the repair signal path, the second fuse FS2 is cut and the first fuse FS1 is electrically connected to the mode The signal MD may have a logic low level L corresponding to the ground voltage VSS.

In an embodiment, the repair method may be determined and the logic level of the mode signal MD may be fixed when the system is constructed using the fuse circuit of FIG. 37 . In another embodiment, information on the repair method of the system may be stored in the mode register set described with reference to FIGS. 35 and 36 , and the logic level of the mode signal MD may be determined based on the stored information.

38 is a diagram illustrating a stacked memory chip according to embodiments of the present invention.

Referring to FIG. 38 , the stacked memory chip 500 may include a base substrate 510 and a plurality of semiconductor dies SD1 , SD2 , and SD3 stacked on the base substrate 510 . 38 illustrates three semiconductor dies SD1 , SD2 , and SD3 for convenience, the number of semiconductor dies may be variously changed.

The base substrate 510 may be a printed circuit board (PCB). An external connection member 520 , for example, a conductive bump may be formed on a lower surface of the base substrate 510 . The semiconductor dies SD1 , SD2 , and SD3 may be electrically connected to each other and connected to an external device through a plurality of signal paths SP1 , SP2 , SP3 , and SP4 . Each of the signal paths SP1 , SP2 , SP3 , and SP4 may include at least one pad PD, at least one conductive bump BP, and at least one through-silicon via TSV. The signal paths SP1 , SP2 , SP3 , and SP4 may include normal signal paths and at least one repair signal path. Meanwhile, the semiconductor dies SD1 , SD2 , and SD3 may be electrically connected to the base substrate 510 using a bonding wire BW. The stacked semiconductor dies SD1 , SD2 , and SD3 may be packaged using the sealing member 530 .

Each of the semiconductor dies SD1 , SD2 , and SD3 includes an internal circuit that performs a unique function, a plurality of normal input/output terminals connected to an external processor through normal signal paths, and at least one repair signal path with the processor. Included in the normal signal paths based on an input/output terminal unit including at least one repair input/output terminal selectively connected, a mode signal indicating whether the repair signal path is used, and a failure information signal indicating failure information of the normal signal paths A repair circuit for repairing a defective signal path may be included. FIG. 38 shows only the conversion units CU included in the repair circuit, and for convenience, the internal circuit of the semiconductor die, the repair control unit, and the like are omitted.

The stacked memory chip 500 according to embodiments of the present invention may include an adaptive repair circuit to efficiently repair systems employing different repair methods. In addition, the stacked memory chip 500 supports different repair methods using the same device configuration, thereby reducing system design and manufacturing costs.

39 is a diagram illustrating a system according to embodiments of the present invention.

Referring to FIG. 39 , the system 600 may include a board 610 and a plurality of subsystems SSYSa, SSYSb, SSYSc, and SYCd mounted on the board 610 .

For example, the first subsystem SSYSa and the second subsystem SSYSb may be mounted on the interposer 620 and electrically connected to each other using signal lines of the interposer. For example, the fourth subsystem SSYCd may be stacked on the third subsystem SSYSc to form a package on package (PoP) structure. The interposer 620 and the PoP may be electrically connected to each other through lines of a signal bus formed on a board.

At least one of the subsystems SSYSa, SSYSb, SSYSc, and SYCd may include an adaptive repair circuit (not shown) according to embodiments of the present invention as described above. By using the repair circuit, systems employing different repair methods can be efficiently repaired, and design and manufacturing costs of the system can be reduced.

40 and 41 are diagrams illustrating memory modules according to embodiments of the present invention.

40 and 41 , each of the memory modules 701 and 702 may include a module substrate 710 , a plurality of semiconductor memory chips SMC, and a buffer chip BC.

The semiconductor memory chips SMC are mounted on the module substrate 710 , and the semiconductor memory chips SMC receive data DQ from an external device such as a memory controller in a write mode through a data bus 712 or receive data DQ in a read mode. Data DQ may be transmitted to an external device.

The buffer chip BC is mounted on the module substrate 710 , and buffers the command-address signals CMD and ADD received from the outside through the control bus 711 to form semiconductor memory chips through the internal buses 713 and 714 . (SMC). The buffer chip BC may include a register for storing control information of the memory modules 701 and 702 .

In an embodiment, as shown in FIG. 40 , the buffer chip BC may include the adaptive repair circuit REP according to the embodiments of the present invention as described above. Signal paths for transmitting the command-address signals CMD and ADD between the memory module 701 and the external memory controller may be efficiently repaired using the adaptive repair circuit REP.

In another embodiment, as shown in FIG. 41 , the semiconductor memory chips SMC may include the adaptive repair circuit REP according to the embodiments of the present invention as described above. Signal paths for transmitting data DQ between the memory module 702 and an external memory controller may be efficiently repaired using the adaptive repair circuit REP.

42 is a diagram illustrating an example in which memory modules according to embodiments of the present invention are connected to a memory controller.

Referring to FIG. 42 , the memory controller 815 mounted on the main board 817 and the plurality of connection sockets 870 are electrically connected to each other through the system bus 820 . A required number of the memory modules MM1 , MM2 , and MM3 shown in FIGS. 40 and 41 may be mounted in the connection socket 870 . Meanwhile, termination resistors 880 may be provided on the main board 817 for impedance matching.

In case a bad signal path is included in the system bus 820 connecting the memory controller 815 and the memory modules MM1, MM2, and MM3, the memory controller 815 and the memory modules MM1, MM2, and MM3 ) may each include a repair circuit for repairing a bad signal path. At least one of the memory controller 815 and the memory modules MM1 , MM2 , and MM3 may include an adaptive repair circuit (not shown) according to embodiments of the present invention as described above. Signal paths between the memory controller 815 and the memory modules MM1 , MM2 , and MM3 may be efficiently repaired using the adaptive repair circuit REP.

43 is a diagram illustrating a structure of a stacked memory device according to an embodiment of the present invention.

43 , the semiconductor memory device 901 may include a plurality of semiconductor dies or semiconductor layers (LA1 to LAk, where k is a natural number equal to or greater than 3). The lowermost semiconductor layer LA1 may be a master layer, and the remaining semiconductor layers LA2 to LAk may be slave layers.

The semiconductor layers LA1 to LAk transmit and receive signals to each other through the through via TSV, and the master layer LA1 may communicate with an external memory controller (not shown) through the chip input/output pad unit. The chip input/output pad unit may be formed on a lower surface of the master layer LA1 or formed on a base substrate (not shown).

Each of the first semiconductor layer 910 to the kth semiconductor layer includes various peripheral circuits 922 for driving the memory cell array region 921 . For example, the peripheral circuits 922 include a row driver (X-Driver) for driving a word line of each memory cell array region 921 and a column driver (Y-Driver) for driving a bit line of each memory region and a data input/output unit for controlling input/output of data, a command buffer for receiving and buffering a command CMD from the outside, and an address buffer for receiving and buffering an address from the outside.

The first semiconductor layer 910 may further include control logic. The control logic may control access to the memory area 921 based on a command and an address signal provided from a memory controller (not shown) and generate control signals for accessing the memory area 921 .

Each of the first semiconductor layer 910 to the k-th semiconductor layer 920 may include the repair circuit (REP) 960 according to the above-described embodiments of the present invention. When a bad signal path is included among signal paths with the memory controller, the bad signal path may be efficiently repaired in the first semiconductor layer 910 to the kth semiconductor layer using the repair circuit 960 .

44 is a block diagram illustrating a memory system according to embodiments of the present invention.

Referring to FIG. 44 , the memory system 1000 may include a memory module 1010 and a memory controller 1020 . The memory module 1010 may include at least one semiconductor memory chip (DRAM) 1030 mounted on a module board. For example, the semiconductor memory chip 1030 may be implemented as a DRAM chip. Also, each semiconductor memory chip 1030 may include a plurality of semiconductor dies stacked vertically. The semiconductor dies may include one interface die 1031 and at least one memory die or slave die 1032 . Signal transmission between the semiconductor dies stacked on each other may be performed through a through silicon via (TSV) and/or a bonding wire.

The memory module 1010 may communicate with the memory controller 1020 through a system bus. A data signal DQ, a command/address CMD/ADD, and a clock signal CLK may be transmitted/received between the memory module 1010 and the memory controller 1020 through the system bus.

At least one of the memory module 1010 and the memory controller 1020 may include an adaptive repair circuit (not shown) as described above. Signal paths between the memory controller 1020 and the memory module 1010 may be efficiently repaired using the adaptive repair circuit.

45 is a block diagram illustrating a mobile system according to embodiments of the present invention.

Referring to FIG. 45 , the mobile system 1200 includes an application processor 1210 , a communication unit 1220 , a memory device 1230 , a nonvolatile memory device 1240 , a user interface 1250 , and a power supply ( 1260). According to an embodiment, the mobile system 1200 includes a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), and a digital camera (Digital). Camera), a music player, a portable game console, a navigation system, and the like, may be any mobile system.

The application processor 1210 may execute applications that provide an Internet browser, a game, a video, and the like. According to an embodiment, the application processor 1210 may include one processor core (Single Core) or a plurality of processor cores (Multi-Core). For example, the application processor 1210 may include a multi-core, such as a dual-core, a quad-core, or a hexa-core (Hexa-Core). Also, according to an embodiment, the application processor 1210 may further include a cache memory located inside or outside.

The communication unit 1220 may perform wireless communication or wired communication with an external device. For example, the communication unit 1220 may include Ethernet (Ethernet) communication, near field communication (NFC), radio frequency identification (RFID) communication, mobile communication (Mobile Telecommunication), memory card communication, universal serial Bus (Universal Serial Bus; USB) communication may be performed. For example, the communication unit 1220 may include a baseband chipset, and may support communication such as GSM, GPRS, WCDMA, and HSxPA.

The memory device 1230 may store data processed by the application processor 1210 or may operate as a working memory. For example, the memory device 1230 may be a dynamic random access memory such as DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, RDRAM, or the like.

The nonvolatile memory device 1240 may store a boot image for booting the mobile system 1200 . For example, the nonvolatile memory device 1240 may include an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistance random access memory (RRAM), or a nanometer (NFGM). Floating Gate Memory), Polymer Random Access Memory (PoRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or similar memory.

User interface 1250 may include one or more input devices, such as a keypad, a touch screen, and/or one or more output devices, such as speakers, display devices. The power supply 1260 may supply the operating voltage of the mobile system 1200 . In addition, according to an embodiment, the mobile system 1200 may further include a camera image processor (CIS), a memory card, a solid state drive (SSD), and a hard disk. A storage device such as a hard disk drive (HDD) and a CD-ROM may be further included.

The mobile system 1200 or components of the mobile system 1200 may be mounted using various types of packages, for example, Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs). ), PLCC(Plastic Leaded Chip Carrier), PDIP(Plastic Dual In-Line Package), Die in Waffle Pack, Die in Wafer Form, COB(Chip On Board), CERDIP(Ceramic Dual In-Line Package), MQFP(Plastic Metric Quad Flat Pack), TQFP(Thin Quad Flat-Pack), SOIC(Small Outline Integrated Circuit), SSOP(Shrink Small Outline Package), TSOP(Thin Small Outline Package), TQFP(Thin Quad Flat-Pack), SIP( It may be mounted using packages such as System In Package), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), and Wafer-Level Processed Stack Package (WSP).

At least one of the application processor 1210 , the connectivity unit 1220 , the memory device 1230 , the non-volatile memory device 1240 , and the user interface 1250 may include an adaptive repair circuit (not shown) as described above. may include. Signal paths between components may be efficiently repaired using the adaptive repair circuit.

46 is a block diagram illustrating a computing system according to embodiments of the present invention.

Referring to FIG. 46 , the computing system 1300 includes a processor 1310 , an input/output hub 1320 , an input/output controller hub 1330 , at least one memory module 1340 , and a graphics card 1350 . According to an embodiment, the computing system 1300 may include a personal computer (PC), a server computer, a workstation, a laptop, a mobile phone, and a smart phone. , personal digital assistant (PDA), portable multimedia player (PMP), digital camera (Digital Camera), digital TV (Digital Television), set-top box (Set-Top Box), music player (Music Player), a portable game console (portable game console), may be any computing system, such as a navigation (Navigation) system.

The processor 1310 may execute various computing functions, such as specific calculations or tasks. For example, the processor 1310 may be a microprocessor or a central processing unit (CPU). According to an embodiment, the processor 1310 may include one processor core (Single Core) or a plurality of processor cores (Multi-Core). For example, the processor 1310 may include a multi-core such as a dual-core, a quad-core, or a hexa-core (Hexa-Core). Also, although the computing system 1300 including one processor 1310 is illustrated in FIG. 46 , the computing system 1300 may include a plurality of processors according to an embodiment. Also, according to an embodiment, the processor 1310 may further include a cache memory located inside or outside.

The processor 1310 may include a memory controller 1311 that controls the operation of the memory module 1340 . The memory controller 1311 included in the processor 1310 may be referred to as an integrated memory controller (IMC). The memory interface between the memory controller 1311 and the memory module 1340 may be implemented as one channel including a plurality of signal lines or as a plurality of channels. Also, one or more memory modules 1340 may be connected to each channel. According to an embodiment, the memory controller 1311 may be located in the input/output hub 1320 . The input/output hub 1520 including the memory controller 1311 may be referred to as a memory controller hub (MCH).

The input/output hub 1320 may manage data transmission between devices such as the graphic card 1350 and the processor 1310 . The input/output hub 1320 may be connected to the processor 1510 through various interfaces. For example, the input/output hub 1320 and the processor 1310 may include a Front Side Bus (FSB), a System Bus, a HyperTransport, and a Lightning Data Transport; LDT), QuickPath Interconnect (QPI), and Common System Interface (CSI) may be connected through various standard interfaces. 46 illustrates a computing system 1300 including one input/output hub 1320 , but according to an embodiment, the computing system 1300 may include a plurality of input/output hubs.

The input/output hub 1320 may provide various interfaces with devices. For example, the input/output hub 1320 may include an Accelerated Graphics Port (AGP) interface, a Peripheral Component Interface-Express (PCIe) interface, a Communications Streaming Architecture (CSA) interface, and the like. can provide

The graphic card 1350 may be connected to the input/output hub 1320 through AGP or PCIe. The graphic card 1350 may control a display device (not shown) for displaying an image. The graphic card 1350 may include an internal processor for processing image data and an internal semiconductor memory device. According to an embodiment, the input/output hub 1320 may include a graphics device inside the input/output hub 1320 together with the graphics card 1350 located outside the input/output hub 1320 or instead of the graphics card 1350. can The graphic device included in the input/output hub 1520 may be called integrated graphics. Also, the input/output hub 1320 including the memory controller and the graphic device may be referred to as a graphics and memory controller hub (GMCH).

The input/output controller hub 1330 may perform data buffering and interface arbitration so that various system interfaces operate efficiently. The input/output controller hub 1330 may be connected to the input/output hub 1320 through an internal bus. For example, the input/output hub 1320 and the input/output controller hub 1330 may be connected through a direct media interface (DMI), a hub interface, an enterprise southbridge interface (ESI), PCIe, etc. .

The input/output controller hub 1330 may provide various interfaces with peripheral devices. For example, the input/output controller hub 1330 may include a Universal Serial Bus (USB) port, a Serial Advanced Technology Attachment (SATA) port, a General Purpose Input/Output (GPIO), and a low pin count (Low Pin Count; LPC) bus, Serial Peripheral Interface (SPI), PCI, PCIe, etc. can be provided.

According to an embodiment, the processor 1310 , the input/output hub 1320 , and the input/output controller hub 1330 are implemented as separate chipsets or integrated circuits, respectively, or the processor 1310 , the input/output hub 1320 , or the input/output controller hub Two or more components of 1330 may be implemented as one chipset.

At least one of the processor 1310 , the input/output hub 1320 , the input/output controller hub 1330 , the memory module 1340 , and the graphic card 1350 may include an adaptive repair circuit (not shown) as described above. . Signal paths between components may be efficiently repaired using the adaptive repair circuit.

The apparatus and system including the adaptive repair circuit according to embodiments of the present invention may be usefully used in any apparatus or system requiring signal transmission between components. In particular, the adaptive repair circuit according to embodiments of the present invention is a computer, a laptop, a cell phone, a smart phone, an MP3 player, and a personal digital assistant that require high performance and low power. ; PDA), PMP (Portable Multimedia Player; PMP), digital TV, digital camera, portable game console (portable game console), such as electronic devices can be usefully applied.

Although the present invention has been described with reference to preferred embodiments, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention as set forth in the following claims. you will understand that you can

100: repair circuit
200: repair control unit
300: path conversion circuit
TN: Normal input/output terminal
TR: Repair input/output terminal
ND: I/O node of the internal circuit
MS: main signal
SS: sub signal
MSP: main signal path
SSP: sub-signal path
RSP: repair signal path
MD: mode signal
FLI: Bad information signal
PCON: path control signal
PSL: path selection signal
BLK: block control signal

Claims (10)

internal circuitry that performs its own function;
an input/output terminal unit including a plurality of normal input/output terminals connected to an external device through a plurality of normal signal paths and at least one repair input/output terminal selectively connected to the external device through at least one repair signal path; and
a repair circuit for repairing a bad signal path included in the normal signal paths based on a mode signal indicating whether the repair signal path is used or a bad information signal indicating failure information of the normal signal paths;
the repair circuit selectively operates in one of a first repair mode not using the repair input/output terminal and a second repair mode using the repair input/output terminal based on the mode signal;
and the normal input/output terminals include main input/output terminals for transmitting main signals for a main operation of the internal circuit and at least one sub input/output terminal for transmitting a sub signal for a sub operation of the internal circuit. delete According to claim 1,
in the first repair mode, the repair circuit repairs a defective input/output terminal corresponding to the defective signal path among the normal input/output terminals using the sub input/output terminal;
the internal circuit stops the sub-operation in the first repair mode;
In the second repair mode, the repair circuit repairs a defective input/output terminal corresponding to the defective signal path among the normal input/output terminals using the repair input/output terminal. According to claim 1,
and an initialization circuit connected to the repair input/output terminal and configured to apply an initialization voltage to the repair input/output terminal in response to the mode signal. According to claim 1,
The normal input/output terminals are grouped into a plurality of groups, and at least one repair input/output terminal is independently allocated to each of the groups, or at least one repair input/output terminal is common to at least two of the groups. Device characterized in that it is assigned. internal circuitry that performs its own function;
an input/output terminal unit including a plurality of normal input/output terminals connected to an external device through a plurality of normal signal paths and at least one repair input/output terminal selectively connected to the external device through at least one repair signal path; and
a repair circuit for repairing a bad signal path included in the normal signal paths based on a mode signal indicating whether the repair signal path is used or a bad information signal indicating failure information of the normal signal paths;
wherein the repair circuit replaces a defective input/output terminal corresponding to the defective signal path among the normal input/output terminals with the normal input/output terminal adjacent to the defective input/output terminal or the repair input/output terminal adjacent to the defective input/output terminal; or and performing a multiplexing repair operation of replacing a bad input/output terminal corresponding to the bad signal path among normal input/output terminals with a sub input/output terminal corresponding to one of the normal input/output terminals or the repair input/output terminal. internal circuitry that performs its own function;
an input/output terminal unit including a plurality of normal input/output terminals connected to an external device through a plurality of normal signal paths and at least one repair input/output terminal selectively connected to the external device through at least one repair signal path; and
a repair circuit for repairing a bad signal path included in the normal signal paths based on a mode signal indicating whether the repair signal path is used or a bad information signal indicating failure information of the normal signal paths;
The repair circuit is
a repair control unit generating a plurality of path selection signals based on the mode signal and the failure information signal; and
In response to each of the path selection signals comprising a plurality of conversion units that respectively control the electrical connection between each input/output node of the internal circuit and two or more input/output terminals of the input/output terminal part,
The normal input/output terminals may include main input/output terminals for transmitting main signals for a main operation of the internal circuit and at least one sub input/output terminal for transmitting a sub signal for a sub operation of the internal circuit. device to do. 8. The method of claim 7,
Among the conversion units, a sub conversion unit corresponding to the sub input/output terminal blocks an electrical connection between the internal circuit and the sub conversion unit in response to a block control signal. a first subsystem;
a second subsystem; and
a plurality of normal signal paths connecting the first subsystem and the second subsystem;
The first subsystem is
internal circuitry that performs its own function;
An input/output terminal unit including a plurality of normal input/output terminals connected to the second subsystem through the normal signal paths and at least one repair input/output terminal selectively connected to the second subsystem through at least one repair signal path ; and
a repair circuit for repairing a bad signal path included in the normal signal paths based on a mode signal indicating whether the repair signal path is used or a bad information signal indicating failure information of the normal signal paths;
the repair circuit selectively operates in one of a first repair mode not using the repair input/output terminal and a second repair mode using the repair input/output terminal based on the mode signal;
wherein the normal input/output terminals include main input/output terminals for transmitting main signals for a main operation of the internal circuit and at least one sub input/output terminal for transmitting a sub signal for a sub operation of the internal circuit. base substrate; and
a plurality of semiconductor dies stacked on the base substrate;
Each of the semiconductor dies,
internal circuitry that performs its own function;
an input/output terminal unit including a plurality of normal input/output terminals connected to an external processor through normal signal paths and at least one repair input/output terminal selectively connected to the processor through at least one repair signal path; and
a repair circuit for repairing a bad signal path included in the normal signal paths based on a mode signal indicating whether the repair signal path is used or a bad information signal indicating failure information of the normal signal paths;
the repair circuit selectively operates in one of a first repair mode not using the repair input/output terminal and a second repair mode using the repair input/output terminal based on the mode signal;
and the normal input/output terminals include main input/output terminals for transmitting main signals for a main operation of the internal circuit and at least one sub input/output terminal for transmitting a sub signal for a sub operation of the internal circuit.

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