KR102251280B1 - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor package according to an embodiment of the present disclosure includes a semiconductor chip having a chip pad formed on a first surface thereof; A first insulating layer on the first surface of the semiconductor chip; A first conductive via electrically connected to the chip pad and formed through the first insulating layer; A redistribution layer electrically connected to the first conductive via and buried in the first insulating layer; A second insulating layer on the first insulating layer and in contact with the redistribution layer; A second conductive via electrically connected to the redistribution layer and formed through the second insulating layer; A UBM electrically connected to the second conductive via; And an external connection terminal electrically connected to the UVM.

Description

Semiconductor package and semiconductor package manufacturing method {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

The technical idea of the present disclosure relates to a semiconductor package and a method of manufacturing a semiconductor package, and more specifically, to a semiconductor package in which production cost is reduced through a simplified process, and a method of manufacturing the semiconductor package.

As the storage capacity of the semiconductor chip is increased, the semiconductor package including the semiconductor chip is required to be thin and light. In order to produce a high-capacity, miniaturized semiconductor package, a number of manufacturing processes and inspection processes for determining whether the manufacturing processes operate normally are performed. Recently, semiconductor package manufacturing companies are attempting to reduce the production cost of a semiconductor package by simplifying the manufacturing processes and the inspection processes.

One of the technical problems to be solved by the technical idea of the present disclosure is to provide a semiconductor package having excellent durability and low risk of damage from external impact.

One of the technical problems to be solved by the technical idea of the present disclosure is to provide a method of manufacturing a semiconductor package capable of reducing production costs through a simplified manufacturing process.

One of the technical problems to be solved by the technical idea of the present disclosure is to provide a method of manufacturing a semiconductor package capable of producing a semiconductor package that is thin, light, and excellent in durability.

In order to achieve the above object, according to an embodiment of the present disclosure, a semiconductor chip having a chip pad formed on a first surface thereof; A first insulating layer on the first surface of the semiconductor chip; A first conductive via electrically connected to the chip pad and formed through the first insulating layer; A redistribution layer electrically connected to the first conductive via and buried in the first insulating layer; A second insulating layer on the first insulating layer and in contact with the redistribution layer; A second conductive via electrically connected to the redistribution layer and formed through the second insulating layer; A UBM electrically connected to the second conductive via; And an external connection terminal electrically connected to the UVM.

In an exemplary embodiment, the first insulating layer and the second insulating layer are characterized in that they include a non-photosensitive material.

In an exemplary embodiment, materials of the first insulating layer and the second insulating layer are different.

In an exemplary embodiment, side surfaces of the redistribution layer are surrounded by the first insulating layer, and a first surface of the redistribution layer exposed on the first insulating layer abuts the second insulating layer. It is done.

In an exemplary embodiment, the UVM is buried in the second insulation layer, the sides of the UVM are surrounded by the second insulation layer, and the first UVM exposed on the second insulation layer. The surface is at the same height as the second insulating layer, and the external connection terminal is in contact with the first surface of the UVM.

In an exemplary embodiment, the sum of the thicknesses of the first conductive via, the redistribution layer, the second conductive via, and the UVM is equal to the sum of the thicknesses of the first insulating layer and the second insulating layer. It is characterized by that.

In an exemplary embodiment, the UVM is formed to protrude from the second insulating layer, and the external connection terminals surround side surfaces of the UVM.

In an exemplary embodiment, the UVM is buried in the second insulation layer, the sides of the UVM are surrounded by the second insulation layer, and the first UVM exposed on the second insulation layer. A surface is closer to the semiconductor chip than a surface exposed to the outside of the second insulating layer, the external connection terminal abuts the first surface of the UVM, and the first surface of the UVM and the external connection terminal are It is characterized in that a step is formed between the surface formed in contact and the surface exposed to the outside of the second insulating layer.

In an exemplary embodiment, a surface formed by contacting the redistribution layer and the second insulating layer is at the same height as a surface formed by contacting the first insulating layer and the second insulating layer.

In an exemplary embodiment, a surface formed by contacting the redistribution layer and the second insulating layer is closer to the semiconductor chip than a surface formed by contacting the first and second insulating layers, and the redistribution layer and A step is formed between a surface formed by contacting the second insulating layer and a surface formed by contacting the first insulating layer and the second insulating layer.

In an embodiment of the present disclosure, applying a first insulating layer on a first surface of a semiconductor chip on which a chip pad is formed; Stamping the first insulating layer to form a first via hole and a redistribution pattern; Exposing the chip pad by etching the first insulating layer in the portion where the first via hole is formed; Forming a first conductive via and a redistribution layer by filling the first via hole and the redistribution pattern with a first conductive material; Etching the first conductive material and exposing the redistribution layer and the first insulating layer to the outside; Applying a second insulating layer on the first insulating layer; Stamping the second insulating layer to form a second via hole and a UVM pattern; Exposing the redistribution layer by etching the second insulating layer in the portion where the second via hole is formed; Filling the second via hole and the UVM pattern with a second conductive material to form a second conductive via and a UVM; Etching the second conductive material and exposing the UVM and the second insulating layer to the outside; And mounting an external connection terminal on the UVM.

In an exemplary embodiment, the forming of the first via hole and the redistribution pattern by stamping the first insulating layer may include stamping the first insulating layer to form the first via hole and the redistribution pattern. It characterized in that it includes; forming at the same time.

In an exemplary embodiment, the forming of the first via hole and the redistribution pattern by stamping the first insulating layer may include stamping the first insulating layer with a via hole stamp having a first protrusion formed thereon. 1 forming a via hole; And stamping the first insulating layer with a redistribution stamp having a second protrusion formed thereon to form the redistribution pattern.

In an exemplary embodiment, in the step of forming the first via hole by stamping the first insulating layer with the via hole stamp, the first protrusion may include a convex curved surface from a lower portion.

In an exemplary embodiment, the step of forming the redistribution pattern by stamping the first insulating layer with the redistribution stamp having the second protrusion formed thereon, wherein the second protrusion is buried in the first insulating layer. ; And forming the redistribution pattern by removing the buried second protrusion from the first insulating layer, wherein in the step of burying the second protrusion in the first insulating layer, the redistribution stamp When looking down from the top, the center of the first via hole is characterized in that it does not overlap with the second protrusion.

In an exemplary embodiment, the step of forming the first via hole and the redistribution pattern by stamping the first insulating layer may include stamping the first insulating layer with a stamp having a protrusion formed thereon. 1 forming the via hole and the redistribution pattern; and wherein the surface of the protrusion is patterned in a hatcning shape.

In an embodiment of the present disclosure, applying a first insulating layer on a first surface of a semiconductor chip on which a chip pad is formed; Stamping the first insulating layer to form a first via hole and a redistribution pattern; Exposing the chip pad by etching the first insulating layer in the portion where the first via hole is formed; Forming a first conductive via and a redistribution layer by filling the first via hole and the redistribution pattern with a first conductive material; Etching the first conductive material and exposing the redistribution layer and the first insulating layer to the outside; Applying a second insulating layer on the first insulating layer; Stamping the second insulating layer to form a second via hole; Exposing the redistribution layer by etching the second insulating layer in the portion where the second via hole is formed; Filling the second via hole with a second conductive material to form a second conductive via; Etching the second conductive material and exposing the second insulating layer to the outside; Forming a UVM on the second insulating layer through a photolithography process; And mounting an external connection terminal on the UVM.

In an exemplary embodiment, the mounting of the external connection terminal includes mounting the external connection terminal on the second insulating layer so as to surround a side surface of the UVM.

The semiconductor package according to the exemplary embodiment of the present disclosure has excellent durability and may reduce the risk of damage from external impact.

In the method of manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure, a semiconductor package may be manufactured at a low production cost, including a stamping process.

A method of manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure may include a stamping process to produce a semiconductor package that is thin, light, and excellent in durability.

1 is a cross-sectional view of a first semiconductor package according to an exemplary embodiment of the present disclosure.
2 is a cross-sectional view of a second semiconductor package according to an exemplary embodiment of the present disclosure.
3 is a flowchart of a method of manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.
4 is a diagram illustrating a step of applying a first insulating layer on a first surface of a semiconductor chip according to an exemplary embodiment of the present disclosure.
5 is a diagram illustrating a step of forming a first via hole and a redistribution pattern by stamping a first insulating layer according to an exemplary embodiment of the present disclosure.
6 is a side view of a first stamp according to an embodiment of the present disclosure.
7 is a bottom view of a protrusion of a first stamp according to an embodiment of the present disclosure.
8 is a diagram illustrating a first via hole formed through a first stamping process according to an exemplary embodiment of the present disclosure.
9 is a diagram illustrating a step of etching a first via hole according to an embodiment of the present disclosure.
10 is a diagram illustrating a first via hole etched by the plasma etching process according to an embodiment of the present disclosure.
11 is a diagram illustrating a first via hole cleaned by an ultrasonic cleaning process according to an exemplary embodiment of the present disclosure.
12 is a diagram illustrating a step of forming a first via hole by stamping a first insulating layer with a via hole stamp according to an embodiment of the present disclosure.
13 is a diagram illustrating a step of etching a first via hole according to an embodiment of the present disclosure.
14 and 15 are views illustrating a step of forming a redistribution pattern by stamping a first insulating layer with a redistribution stamp according to an exemplary embodiment of the present disclosure.
16 is a diagram illustrating a step of thermally curing a first insulating layer having a first via hole and a redistribution pattern formed thereon.
17 is a diagram illustrating a step of forming a first conductive via and a redistribution layer according to an exemplary embodiment of the present disclosure.
18 is a diagram illustrating a step of etching a first conductive material according to an embodiment of the present disclosure
19 is a diagram illustrating a step of applying a second insulating layer on the first insulating layer according to an exemplary embodiment of the present disclosure.
20 is a diagram illustrating a step of forming a second via hole and a UVM pattern by stamping a second insulating layer according to an exemplary embodiment of the present disclosure.
21 is a diagram illustrating a step of etching a second via hole according to an embodiment of the present disclosure.
22 is a diagram illustrating a step of forming a second conductive via and a first MB according to an embodiment of the present disclosure.
23 is a diagram illustrating a step of etching a second conductive material according to an embodiment of the present disclosure.
24 is a diagram illustrating a step of mounting a first external connection terminal according to an embodiment of the present disclosure.
25 is a flowchart of a method of manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.
26 is a diagram illustrating a step of forming a second MBM through a photolithography process on a second insulating layer according to an embodiment of the present disclosure.
27 is a diagram illustrating a step of mounting a second external connection terminal according to an embodiment of the present disclosure.
28 is a schematic block diagram of an electronic system including a semiconductor package according to an embodiment of the present disclosure.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the embodiments of the present disclosure may be modified in various forms, and the scope of the concept of the present disclosure should not be construed as being limited by the embodiments described below. It is preferable that the embodiments of the present disclosure be interpreted as being provided in order to more completely explain the concept of the present disclosure to those with average knowledge in the art. Identical symbols mean the same elements all the time. Furthermore, various elements and areas in the drawings are schematically drawn. Accordingly, the concept of the present disclosure is not limited by the relative size or spacing drawn in the accompanying drawings.

Terms such as first and second may be used to describe various constituent elements, but the constituent elements are not limited by the terms. These terms are only used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the rights of the concept of the present disclosure, a first component may be referred to as a second component, and conversely, a second component may be referred to as a first component.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the concept of the present disclosure. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, expressions such as "comprises" or "have" are intended to designate the presence of features, numbers, steps, actions, components, parts, or a combination thereof described in the specification, but one or more other features or It is to be understood that it does not preclude the possibility of the presence or addition of numbers, actions, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical terms and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the concept of the present disclosure belongs. In addition, terms commonly used, as defined in the dictionary, should be construed as having a meaning consistent with what they mean in the context of the technology to which they are related, and in an excessively formal sense unless explicitly defined herein. It will be understood that it should not be interpreted.

Prior to describing the technical concepts of the present disclosure with reference to the accompanying drawings, in defining lengths of components of the first and second semiconductor packages 100a and 100b, the length of the first direction X is defined as the width, The length in the second direction Y is referred to as the width, and the length in the third direction Z is referred to as the thickness. However, the terms defined above may be referred to as lengths in different directions for convenience of description.

1 is a cross-sectional view of a first semiconductor package 100a according to an exemplary embodiment of the present disclosure. The first semiconductor package 100a may be a wafer level package (WLP). For example, the first semiconductor package 100a may be a fan-out wafer level package (FOWLP). However, the present invention is not limited thereto, and the first semiconductor package 100a may be a panel level package (PLP).

Referring to FIG. 1, a first semiconductor package 100a according to an exemplary embodiment of the present disclosure includes a semiconductor chip 101, a chip pad 102, a first insulating layer 103, and a first conductive via 104. , Redistribution layer 105, second insulating layer 106, second conductive via 107, first under bump material (UBM, 108a), first external connection terminal 109a, and protective layer It may include (110).

The semiconductor chip 101 of the first semiconductor package 100a according to the exemplary embodiment of the present disclosure may include a plurality of individual devices of various types. For example, the plurality of individual devices may include various microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) such as a CMOS transistor (complementary metal-insulator-semiconductor transistor), and a system LSI. (large scale integration), an image sensor such as a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), an active device, a passive device, and the like.

In one embodiment, the semiconductor chip 101 may be a memory semiconductor chip. The memory semiconductor chip is, for example, a volatile memory semiconductor chip such as dynamic random access memory (DRAM) or static random access memory (SRAM), or phase-change random access memory (PRAM), magneto-resistive random access memory (MRAM). ), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM).

In one embodiment, the semiconductor chip 101 may be a logic chip. For example, the semiconductor chip 101 may be a central processor unit (CPU), a micro processor unit (MPU), a graphic processor unit (GPU), or an application processor (AP).

Referring to FIG. 1, the first semiconductor package 100a is illustrated as including one semiconductor chip 101, but the first semiconductor package 100a may include a plurality of semiconductor chips 101. The plurality of semiconductor chips 101 included in the first semiconductor package 100a may be the same type of semiconductor chips or different types of semiconductor chips. In an embodiment, the first semiconductor package 100a may be a system in package (SIP) in which different types of semiconductor chips are electrically connected to each other to operate as a single system.

In one embodiment, the width (length in the X direction) and the width (length in the Y direction) of the semiconductor chip 101 may be about 2 millimeters to about 10 millimeters. More specifically, the width and width of the semiconductor chip 101 may be about 4 millimeters to about 7 millimeters. However, the present invention is not limited thereto, and the width and width of the semiconductor chip 101 may have more various values. Further, the thickness (length in the Z direction) of the semiconductor chip 101 may be about 100 micrometers to about 400 micrometers. More specifically, the thickness of the semiconductor chip 101 may be about 150 micrometers to about 300 micrometers. However, the present invention is not limited thereto, and the thickness of the semiconductor chip 101 may have various values.

In an embodiment, the semiconductor chip 101 may include a first surface 121 and a second surface 122 facing the first surface 121. A chip pad 102 may be formed on the first surface 121 of the semiconductor chip 101. The chip pad 102 may be electrically connected to a plurality of individual devices of various types formed on the semiconductor chip 101. The chip pad 102 may have a thickness between about 0.5 micrometers and about 1.5 micrometers. However, the present invention is not limited thereto, and the chip pad 102 may have various thickness values. Further, although not shown in FIG. 1, a protective layer (not shown) may be covered on the first surface 121 of the semiconductor chip 101.

The first insulating layer 103 of the first semiconductor package 100a according to the exemplary embodiment of the present disclosure may be on the first surface 121 of the semiconductor chip 101. More specifically, the first insulating layer 103 may be between the first surface 121 and the second insulating layer 106 of the semiconductor chip 101. In one embodiment, the first insulating layer 103 may have a thickness value of about 20 micrometers to about 50 micrometers between the first surface 121 and the second insulating layer 106 of the semiconductor chip 101. have.

In one embodiment, the first insulating layer 103 may include a non-conductive material. For example, the first insulating layer 103 may include polyimide or epoxy. However, the present invention is not limited thereto, and the first insulating layer 103 may include a silicon oxide film, a silicon nitride film, an insulating polymer, or a combination thereof.

In one embodiment, a first via hole (FIG. 9, H1) and a redistribution pattern (FIG. 9, P1) through a first stamping process (FIG. 5, S202) to be described later in the first insulating layer 103 Since may be formed, the first insulating layer 103 may include not only a photosensitive material but also a non-photosensitive material.

In an embodiment, a first via hole H1 may be formed in the first insulating layer 103 through a first stamping process S202. More specifically, the first via hole H1 may be formed through the first insulating layer 103 in the portion where the chip pad 102 is formed. The first via hole H1 may have a tapered structure. More specifically, the first via hole H1 may have a tapered structure in which a cross-sectional area increases in a direction away from the chip pad 102. However, the present invention is not limited thereto, and the first via hole H1 may have various structures.

In one embodiment, the diameter of the first via hole H1 may be about 5 micrometers to about 20 micrometers. For example, when the first via hole H1 has a tapered structure, the diameter of the first via hole H1 in a region adjacent to the chip pad 102 may be about 5 micrometers, and the redistribution layer 105 The first via hole H1 may have a diameter of about 15 micrometers in an area adjacent to the. In addition, when the first via hole H1 has a cylindrical structure, the diameter of the first via hole H1 in the area adjacent to the chip pad 102 and the area adjacent to the redistribution layer 105 may be about 10 micrometers. have. However, the present invention is not limited to the above, and a value of the diameter of the first via hole H1 may vary according to various shapes of the first via hole H1.

In an embodiment, a plurality of first via holes H1 may be formed in the first insulating layer 103. The distance d1 between the first via holes H1 in the first direction X may be about 30 micrometers to 100 micrometers. However, the present invention is not limited thereto, and the separation distance d1 between the first via holes H1 in the first direction X may have various values.

The first conductive via 104 of the first semiconductor package 100a according to an embodiment of the present disclosure may be a conductive material filling the first via hole H1. The conductive material may be a metal material having excellent conductivity, such as copper, gold, or silver.

In one embodiment, the first conductive via 104 may contact the chip pad 102 and may be electrically connected to the chip pad 102. The first conductive via 104 may be electrically connected to the chip pad 102, and accordingly, the first conductive via 104 may be electrically connected to a plurality of individual devices of various types on the semiconductor chip 101. have. In addition, the first conductive via 104 may be electrically connected to the redistribution layer 105 to be described later.

The redistribution layer 105 of the first semiconductor package 100a according to the exemplary embodiment of the present disclosure may be a wiring layer for electrically connecting the first conductive via 104 and the second conductive via 107. As shown in FIG. 1, the redistribution layer 105 is located between the first conductive via 104 and the second conductive via 107 and includes the first conductive via 104 and the second conductive via 107. Can be electrically connected.

In one embodiment, as shown in FIG. 1, the redistribution layer 105 may be buried in the first insulating layer 103. More specifically, the first surface 105a of the redistribution layer 105 may be substantially at the same height as the first insulating layer 103. In other words, the surface formed by contacting the redistribution layer 105 and the second insulating layer 106 may be at substantially the same height as the surface formed by contacting the first insulating layer 103 and the second insulating layer 106. I can. In addition, a surface of the redistribution layer 105 facing the first surface 105a and side surfaces of the redistribution layer 105 may be surrounded by the first insulating layer 103. Since the redistribution layer 105 can be buried inside the first insulating layer 103, the redistribution layer 105 can be firmly positioned inside the first insulating layer 103, and the first semiconductor package The thickness of (100a) can be made thinner.

In an embodiment, unlike FIG. 1, the first surface 105a of the redistribution layer 105 may be at a lower height than the first insulating layer 103. In other words, the surface formed by contacting the first surface 105a and the second insulating layer 106 of the redistribution layer 105 is greater than the surface formed by contacting the first insulating layer 103 and the second insulating layer 106. It may be close to the semiconductor chip 101. Accordingly, a surface formed by contacting the first surface 105a and the second insulating layer 106 of the redistribution layer 105 and a surface formed by contacting the first insulating layer 103 and the second insulating layer 106 There may be a step difference between them. In one embodiment, the redistribution layer 105 may include a plurality of redistribution lines. The separation distance d2 between the redistribution lines may be about 0.5 micrometers to about 3 micrometers. More specifically, the separation distance d2 between the redistribution lines may be about 0.5 micrometers to about 1.5 micrometers. However, the present invention is not limited thereto, and the separation distance d2 between redistribution lines may have various values. Also, the width of the redistribution lines may be about 0.5 micrometers to about 1.5 micrometers. However, the present invention is not limited thereto, and the widths of redistribution lines may have various values. Further, the thickness of the redistribution lines may be about 1 micrometer to about 5 micrometers. However, the present invention is not limited thereto, and the thickness of the redistribution lines may have various values. Due to the semiconductor package manufacturing methods (S200, S300) of the present disclosure to be described later, the redistribution layer 105 has a relatively narrow separation distance (d2), a small width, and a small thickness as compared to the prior art. I can. Accordingly, the redistribution layer 105 may be precisely and finely arranged within the first insulating layer 103.

In one embodiment, the material of the redistribution layer 105 may include a metal material having excellent conductivity, such as copper, gold, or silver. Also, the redistribution layer 105 may be made of substantially the same material as the material of the first conductive via 104. For example, when the material of the first conductive via 104 is copper, the material of the redistribution layer 105 may include copper.

The second insulating layer 106 of the first semiconductor package 100a according to the exemplary embodiment of the present disclosure may be on the first insulating layer 103. More specifically, the second insulating layer 106 may be on the first insulating layer 103 while contacting the redistribution layer 105. Further, the second insulating layer 106 may have a thickness of about 20 micrometers to about 50 micrometers on the first insulating layer 103.

In one embodiment, the second insulating layer 106 may be different from the material of the first insulating layer 103. In this case, a boundary surface may be formed between the first insulating layer 103 and the second insulating layer 106. The boundary surface may be substantially at the same height as the first surface 105a of the redistribution layer 105 described above. However, the present invention is not limited thereto, and the material of the first insulating layer 103 and the second insulating layer 106 may be the same material. In this case, a boundary surface may not be formed between the first insulating layer 103 and the second insulating layer 106.

In one embodiment, the second insulating layer 106 may include a non-conductive material. For example, the second insulating layer 106 may include a photosensitive material such as polyimide or an epoxy. However, the present invention is not limited thereto, and the second insulating layer 106 may include a silicon oxide film, a silicon nitride film, an insulating polymer, or a combination thereof.

In addition, a second via hole H2 and a UBM pattern P2 may be formed in the second insulating layer 106 through a second stamping process S207 to be described later. Accordingly, the second insulating layer 106 may include not only a photosensitive material but also a non-photosensitive material.

In an embodiment, a second via hole H2 may be formed in the second insulating layer 106 through a second stamping process S207. More specifically, the second via hole H2 may be formed through the second insulating layer 106 in the portion where the redistribution layer 105 is formed. The number of second via holes H2 formed through the second insulating layer 106 may be plural. The second via hole H2 may have a tapered shape. More specifically, the second via hole H2 may have a tapered shape in which a cross-sectional area increases in a direction away from the first insulating layer 103. However, the present invention is not limited thereto, and the second via hole H2 may have various shapes.

In an embodiment, the second via hole H2 may be located outside the first via hole H1. In other words, the second via hole H2 may be closer to the side surface of the first semiconductor package 100a than the first via hole H1. Accordingly, the separation distance d3 between the second via holes H2 may have a value greater than the separation distance d2 between the first via holes H1. However, the present invention is not limited thereto, and the second via hole H2 may be located inside the first via hole H1. In other words, the second via hole H2 may be farther from the side surface of the first semiconductor package 100a than the first via hole H1.

In one embodiment, the diameter of the second via hole H2 may be about 5 micrometers to about 20 micrometers. For example, when the second via hole H2 has a tapered structure, the diameter of the second via hole H2 in a region adjacent to the first insulating layer 103 may be about 5 micrometers, and In the region adjacent to 108a, the diameter of the second via hole H2 may be about 15 micrometers. In addition, when the second via hole H2 has a cylindrical structure, the diameters of the second via hole H2 in the area adjacent to the first insulating layer 103 and the area adjacent to the first UBM 108a are about 10 microns. Meters can have substantially the same value as each other. However, it is not limited to the above, and the diameter of the first via hole H1 may have various values according to various shapes of the first via hole H1.

The second conductive via 107 of the first semiconductor package 100a according to the exemplary embodiment of the present disclosure may be a conductive material filling the second via hole H2. The conductive material may be a metal material having excellent conductivity, such as copper, gold, or silver.

In one embodiment, the second conductive via 107 may contact the redistribution layer 105 and the first MB 108a. Accordingly, a plurality of individual devices of various types on the semiconductor chip 101 are provided through the first conductive via 104, the redistribution layer 105, the second conductive via 107, and the first UVM 108a. It may be electrically connected to the first external connection terminal 109a.

The first MB 108a of the first semiconductor package 100a according to the exemplary embodiment of the present disclosure may be a pad for electrically connecting the redistribution layer 105 and the first external connection terminal 109a. As shown in FIG. 1, the first UBM 108a is located between the second conductive via 107 and the first external connection terminal 109a, so that the redistribution layer 105 and the first external connection terminal ( 109a) can be electrically connected.

In one embodiment, as shown in FIG. 1, the first MB 108a may be buried in the second insulating layer 106. More specifically, the first surface 108i of the first UVM 108a may be substantially at the same height as the second insulating layer 106.

In an embodiment, unlike FIG. 1, the first surface 108i of the first UVM 108a may be at a lower height than the second insulating layer 106. In other words, the surface formed by the first surface 108i of the first UVM 108a and the first external connection terminal 109a abuts against the surface exposed to the outside of the second insulating layer 106 It can be close to. Accordingly, a step occurs between the surface formed by contacting the first surface 108i of the first UVM 108a and the first external connection terminal 109a and the surface exposed to the outside of the second insulating layer 106. I can.

In one embodiment, a surface of the first UVM 108a facing the first surface 108i and side surfaces of the first UVM 108a may be surrounded by the second insulating layer 106. Since the first UVM 108a can be buried inside the second insulating layer 106, the first UVM 108a can be firmly positioned inside the second insulating layer 106, and the first The thickness of the semiconductor package 100a may be reduced.

In one embodiment, the material of the first UVM 108a may include a metal material having excellent conductivity, such as copper, gold, or silver. In addition, the first MB 108a may be made of substantially the same material as the material of the second conductive via 107. For example, when the material of the second conductive via 107 is copper, the material of the first UVM 108a may include copper.

The first external connection terminal 109a of the first semiconductor package 100a according to the exemplary embodiment of the present disclosure may be located under the first MB 108a and may be electrically connected to the first MB 108a. . In addition, the first external connection terminal 109a may contact the first surface 108i of the first UVM 108a.

In an embodiment, the first semiconductor package 100a may be electrically connected to an external device such as a system substrate or a main board through the first external connection terminal 109a. As shown in FIG. 1, the first external connection terminal 109a may include a solder ball. The solder ball may include at least one of tin, silver, copper, and aluminum. In addition, the solder ball may have a ball shape, as shown in FIG. 1, but is not limited thereto, and may have various shapes such as a cylinder, a polygonal column, and a polyhedron.

The protective layer 110 of the first semiconductor package 100a according to the exemplary embodiment of the present disclosure may be on the second surface 122 of the semiconductor chip 101. The protective layer 110 may be a layer formed to block the semiconductor chip 101 from a harmful environment. In one embodiment, the protective layer 110 may include various oxide films. The protective layer 110 may have a thickness of about 15 micrometers to about 30 micrometers on the second surface 122 of the semiconductor chip 101.

In the first semiconductor package 100a according to the exemplary embodiment of the present disclosure, the redistribution layer 105 and the first UVM 108a may be buried in the first insulating layer 103 and the second insulating layer 106, respectively. Thus, the sum of the thicknesses of the first conductive via 104, the redistribution layer 105, the second conductive via 107, and the first UVM 108a is the first insulating layer 103 and the second insulating layer. It may be substantially equal to the sum of the thicknesses of the layers 106.

The first semiconductor package 100a according to the exemplary embodiments of the present disclosure may be produced by the method S200 of manufacturing a semiconductor package including first and second stamping processes S202 and S207. Accordingly, the production cost of the first semiconductor package 100a may be reduced.

In addition, in the first semiconductor package 100a according to the embodiments of the present disclosure, the redistribution layer 105 and the first UVM 108a are respectively attached to the first insulating layer 103 and the second insulating layer 106. Since it can be embedded, it can be thin and light, but also excellent in durability.

2 is a cross-sectional view of a second semiconductor package 100b according to an exemplary embodiment of the present disclosure. 2, a second semiconductor package 100b according to an exemplary embodiment of the present disclosure includes a semiconductor chip 101, a chip pad 102, a first insulating layer 103, and a first conductive via 104. , Redistribution layer 105, second insulating layer 106, second conductive via 107, second under bump material (UBM, 108b), second external connection terminal 109b, and protective layer It may include (110).

The semiconductor chip 101, the chip pad 102, the first insulating layer 103, the first conductive via 104, the redistribution layer 105, and the second insulating layer 106 of the second semiconductor package 100b The technical concept of the second conductive via 107 and the protective layer 110 is substantially the same as the technical concept of the first semiconductor package 100a described with reference to FIG. 1, and thus detailed information will be omitted.

In one embodiment, the second UVM 108b of the second semiconductor package 100b may be formed to protrude from the second insulating layer 106. More specifically, unlike the first BB 108a of the first semiconductor package 100a of FIG. 1, the second BB 108b of the second semiconductor package 100b is buried in the second insulating layer 106 It may not be formed, and may be formed to protrude from the second insulating layer 106. Accordingly, in a step before the second external connection terminal 109b is formed, side surfaces of the second UBM 108b may be exposed to the outside. The second UVM 108b of the second semiconductor package 100b may be formed through a conventional photolithography process.

In an embodiment, the second external connection terminals 109b of the second semiconductor package 100b may be formed to surround exposed sides of the second UVM 108b. Accordingly, the second external connection terminal 109b of the second semiconductor package 100b may be rigidly mounted on the semiconductor package 100b. Accordingly, durability of the second external connection terminal 109b may be excellent, and a risk of damage to the second semiconductor package 100b may be reduced.

3 is a flowchart of a method S200 of manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure. More specifically, FIG. 3 may be a flowchart of a method S200 of manufacturing the first semiconductor package 100a.

In the semiconductor package manufacturing method S200 of the present disclosure, the step of applying the first insulating layer 103 on the first surface 121 of the semiconductor chip 101 (S201), and stamping the first insulating layer 103 ( stamping) to form the first via hole H1 and the redistribution pattern P1 (S202), etching the first via hole H1 (S203), the first conductive via 104 and the redistribution The step of forming the layer 105 (S204), the step of etching the first conductive material (M1) (S205), the step of applying the second insulating layer 106 on the first insulating layer 103 (S206) , Stamping the second insulating layer 103 to form the second via hole H2 and the UBM pattern P2 (S207), etching the second via hole H2 (S208), the second Forming the conductive via 107 and the first MB 108a (S209), etching the second conductive material M2 (S210), and mounting the first external connection terminal 109a ( S211) may be included.

4 is a diagram illustrating a step S201 of applying a first insulating layer 103 on the first surface 121 of the semiconductor chip 101 according to an exemplary embodiment of the present disclosure. 3 and 4 together, the semiconductor package manufacturing method (S200) of the present disclosure is a step of applying the first insulating layer 103 on the first surface 121 of the semiconductor chip 101 (S201) It may include. More specifically, in the step of applying the first insulating layer 103, the first insulating layer 103 is applied on the first surface 121 of the semiconductor chip 101 on which the chip pad 102 is formed, by about 20 micrometers. It may be a step of applying to a thickness value of about 50 micrometers. As described above, the first insulating layer 103 may include a non-photosensitive material.

5 is a diagram illustrating a step S202 of forming a first via hole H1 and a redistribution pattern P1 by stamping the first insulating layer 103 according to an exemplary embodiment of the present disclosure. 3 and 5, the method S200 of manufacturing a semiconductor package of the present disclosure includes stamping the first insulating layer 103 to form a first via hole H1 and a redistribution pattern P1. (Hereinafter, a first stamping process, S202) may be included.

In one embodiment, in the first stamping process (S202), the first insulating layer 103 is pressed with the first stamp 41 including the protrusions 44 having a size of a micrometer unit or a nanometer unit. It may be a step of forming the first via hole H1 and the redistribution pattern P1 in the insulating layer 103.

In one embodiment, the protrusion 44 of the first stamp 41 may include a first via hole protrusion 42 and a redistribution protrusion 43. More specifically, the first via hole protrusion 42 may form a first via hole H1 in the first insulating layer 103, and the redistribution protrusion 43 is cultivated in the first insulating layer 103 A line pattern P1 may be formed. In one embodiment, after the first stamping process (S202), a thermal curing process may be performed on the first insulating layer 103. The first via hole H1 and the redistribution pattern P1 may be stably formed in the first insulating layer 103 through the thermal curing process.

In one embodiment, the protrusion 44 of the first stamp 41 may include both the first via hole protrusion 42 and the redistribution protrusion 43. Accordingly, the first stamping process S202 may include stamping the first insulating layer 103 to form the first via hole H1 and the redistribution pattern P1 at the same time.

In the semiconductor package manufacturing method S200 according to the exemplary embodiment of the present disclosure, since the first via hole H1 and the redistribution pattern P1 may be formed through the first stamping process S202, the first insulating layer (103) may include a variety of materials. More specifically, since the first via hole H1 and the redistribution pattern P1 can be formed in the first insulating layer 103 through the first stamping process S202 rather than the photolithography process, the first insulation The layer 103 may include a non-photosensitive material. Accordingly, the selection of the material for the first insulating layer 103 can be widened, and the manufacturing cost of the first semiconductor package 100a can be reduced.

In one embodiment, when forming the first via hole H1 and the redistribution pattern P1 in the first insulating layer 103 through the first stamping process (S202), the first insulating layer 103 The thickness can be thicker than when compared to a conventional photolithography process. Accordingly, durability of the first semiconductor package 100a may be increased.

6 is a side view of a first stamp 41 according to an embodiment of the present disclosure. As described above, the first stamp 41 may include a protrusion 44 for patterning the first insulating layer 103. As described above, the protrusion 44 may include a first via hole protrusion 42 and a redistribution protrusion 43.

In one embodiment, the first via hole protrusion 42 of the first stamp 41 may include a curved surface that is convex from the bottom. Since the first via hole protrusion 42 of the first stamp 41 may include the convex curved surface from the bottom, the chip pad 102 by the first via hole protrusion 42 in the first stamping process (S202). ) Physical damage can be prevented.

7 is a bottom view of the protrusion 44 of the first stamp 41 according to an embodiment of the present disclosure. In one embodiment, the surface of the protrusion 44 of the first stamp 41 may be patterned in a hatching shape. More specifically, in the first stamping process (S202 ), the surface of the protrusion 44 that contacts the first insulating layer 103 may be patterned in a hatched shape. For example, the surface of the protrusion 44 may be hatched with a hatched pattern or may be hatched in an uneven shape.

In one embodiment, the surface of the protrusion 44 of the first stamp 41 may be patterned in a hatched shape, so that the first insulating layer 103 in the first stamping process S202 using the first stamp 41 A large load may not be applied to the device. In addition, since the surface of the protrusion 44 may be patterned in a hatched shape, the surfaces of the first via hole H1 and the redistribution pattern P1 formed on the first insulating layer 103 may also have a hatched shape. Accordingly, the cross-sectional area of the first insulating layer 103 exposed to the outside may be increased, and forming the first conductive via 104 in the first via hole H1 through a plating method and a redistribution pattern ( The speed of steps of forming the redistribution layer 105 on P1) may be increased.

8 is a diagram illustrating a first via hole H1 formed through a first stamping process S202 according to an exemplary embodiment of the present disclosure. 8, the diameter of the first via hole H1 formed through the first stamping process (S202) may be about 5 micrometers to 10 micrometers, and the depth may be about 8 micrometers to 20 micrometers. I can. However, the present invention is not limited thereto, and the diameter and depth of the first via hole H1 formed through the first stamping process S202 may have various values.

9 is a diagram illustrating an operation (S203) of etching a first via hole H1 according to an exemplary embodiment of the present disclosure. 3 and 9, the method S200 of manufacturing a semiconductor package of the present disclosure may include etching the first via hole H1 (S203 ). More specifically, the step of etching the first via hole H1 (S203) may be a step of etching the first insulating layer 103 located at the lowermost portion of the first via hole H1. The first insulating layer 103 located at the lowermost portion of the first via hole H1 may be etched to expose the chip pad 102 to the outside.

In an embodiment, the step of etching the first via hole H1 (S203) may include etching the first via hole H1 using plasma (hereinafter, a plasma etching process). More specifically, the plasma etching process may include injecting a process gas into a vacuum chamber and then supplying electrical energy to the process gas. The process gas may be in a plasma state by the supplied electric energy. Reactive atoms of the process gas dissociated in the plasma state may etch the first insulating layer 103 located at the lowermost portion of the first via hole H1 to expose the chip pad 102 to the outside.

10 is a diagram illustrating a first via hole H1 etched by the plasma etching process according to an exemplary embodiment of the present disclosure. Referring to FIG. 10, the diameter of the first via hole H1 etched by the plasma etching process may be about 6 micrometers to 15 micrometers, and the depth may be about 5 micrometers to 16 micrometers. . However, the present invention is not limited thereto, and the diameter and depth of the first via hole H1 etched by the plasma etching process may have various values.

11 is a diagram illustrating a first via hole H1 cleaned by an ultrasonic cleaning process according to an exemplary embodiment of the present disclosure. In an embodiment, the step of etching the first via hole H1 (S203) may selectively include cleaning the first via hole H1 by the ultrasonic cleaning process. In addition, the ultrasonic cleaning process may be performed after the plasma etching process described above.

In one embodiment, the ultrasonic cleaning process applies high-frequency vibration energy to the first insulating layer 103 remaining at the bottom of the first via hole H1 after the above-described plasma etching process, so that the first via hole H1 The first insulating layer 103 on the upper part of) may be removed to expose the chip pad 102 to the outside.

In one embodiment, when the first insulating layer 103 located at the lowermost portion of the first via hole H1 is etched through the above-described plasma etching process to expose the chip pad 102 to the outside, the first of the present disclosure 1 In the step of etching the via hole H1 (S203), the ultrasonic cleaning process may be omitted.

Referring to FIG. 11, the diameter of the first via hole H1 cleaned by the ultrasonic cleaning process may be about 8 micrometers to 20 micrometers, and the depth may be about 3 micrometers to 12 micrometers. However, the present invention is not limited thereto, and the diameter and depth of the first via hole H1 cleaned by the ultrasonic cleaning process may have various values.

12 to 16 are diagrams illustrating a first stamping process (S202) and etching a first via hole (H1) (S203) of a method of manufacturing a semiconductor package (S200) according to an exemplary embodiment of the present disclosure.

12 to 16, the first stamping process (S202) is a first via hole (H1) by stamping the first insulating layer 103 with a via hole stamp 50 in which the first protrusion 51 is formed. And forming a redistribution pattern P1 by stamping the first insulating layer 103 with the redistribution stamp 60 having the second protrusion 61 formed thereon (S202a) and forming the redistribution pattern P1 (S202b). have.

In an embodiment, the first stamping process (S202) is a first via hole (H1) and a redistribution pattern (P1) in the first insulating layer 103 with the first stamp 41, as shown in FIG. It may include forming at the same time. In addition, in the first stamping process (S202), as shown in FIGS. 12 to 16, the first via hole H1 and the redistribution pattern P1 are formed with the via hole stamp 50 and the redistribution stamp 60. It may also include the step of sequentially forming.

12 is a diagram illustrating a step S202a of forming a first via hole H1 by stamping the first insulating layer 103 with the via hole stamp 50 according to an exemplary embodiment of the present disclosure. The via hole stamp 50 may include a first protrusion 51, and the first protrusion 51 may form a first via hole H1 in the first insulating layer 103 through a stamping process. .

In one embodiment, the first protrusion 51 may include a curved surface that is convex from the bottom. Since the first protrusion 51 of the via hole stamp 50 may include a convex curved surface from the bottom, physical damage to the chip pad 102 by the first protrusion 51 during the first stamping process (S202) Can be prevented.

13 is a diagram illustrating an operation (S203) of etching a first via hole H1 according to an exemplary embodiment of the present disclosure. More specifically, the step of etching the first via hole H1 (S203) may be a step of etching the first insulating layer 103 located at the lowermost portion of the first via hole H1. The first insulating layer 103 located at the lowermost portion of the first via hole H1 may be etched to expose the chip pad 102 to the outside.

In an embodiment, the step of etching the first via hole H1 (S203) includes the first insulating layer 103 located at the lowermost portion of the first via hole H1 using the above-described plasma etching process and ultrasonic cleaning process. ) May be included.

The step of etching the first via hole H1 of the present disclosure described with reference to FIG. 9 (S203) is performed after the first via hole H1 and the redistribution pattern P1 are formed in the first insulating layer 103 Could be However, the step of etching the first via hole H1 (S203) is performed after the step (S202a) of forming the first via hole H1 in the first insulating layer 103 and the first when referring to FIG. 13. It may be performed before the step S202b of forming the redistribution pattern P1 on the insulating layer 103.

14 and 15 are views illustrating a step S202b of forming a redistribution pattern P1 by stamping the first insulating layer 103 with the redistribution stamp 60 according to an exemplary embodiment of the present disclosure. The redistribution stamp 60 may include a second protrusion 61, and the second protrusion 61 may form a redistribution pattern P1 on the first insulating layer 103 through a stamping process.

In one embodiment, the step of forming the redistribution pattern P1 by stamping the first insulating layer 103 with the redistribution stamp 60 (S202b) includes the second protrusion 61 being the first insulating layer 103 The step of being buried in the inside, and the step of forming the rewiring pattern P1 by separating the buried second protrusion 61 from the first insulating layer 103.

Referring to FIG. 14, in the step in which the second protrusion 61 is buried in the first insulating layer 103, the second protrusion 61 increases the width of the first via hole H1 in the first direction X. May be located in excess. In addition, the first via hole H1 may be located within a range of a length of the first direction X formed by the second protrusion 61. For example, when the redistribution stamp 60 is viewed from top to bottom, the center of the first via hole H1 may overlap the second protrusion 61.

Referring to FIG. 15, in the step in which the second protrusion 61 is buried in the first insulating layer 103, the second protrusion 61 increases the width of the first via hole H1 in the first direction X. Can be positioned so as not to exceed. In addition, the first via hole H1 may be located outside the range of the length of the first direction X formed by the second protrusion 61. For example, when the redistribution stamp 60 is viewed from top to bottom, the center of the first via hole H1 may not overlap with the second protrusion 61.

In one embodiment, the center of the first via hole H1 may not overlap with the second protrusion 61, so that the first via hole is embedded in the first insulating layer 103 of the second protrusion 61. The change in the shape of (H1) can be minimized.

16 is a diagram illustrating a step of thermally curing the first insulating layer 103 in which the first via hole H1 and the redistribution pattern P1 are formed. Through the thermal curing process, the first via hole H1 and the redistribution pattern P1 may be stably formed in the first insulating layer 103.

17 is a diagram illustrating a step S204 of forming the first conductive via 104 and the redistribution layer 105 according to an exemplary embodiment of the present disclosure. 3 and 17, the method S200 of manufacturing a semiconductor package of the present disclosure may include a step S204 of forming the first conductive via 104 and the redistribution layer 105. More specifically, the forming of the first conductive via 104 may include filling the first via hole H1 formed by the above-described stamping process and etching process with the first conductive material M1. In addition, forming the redistribution layer 105 may include filling the redistribution pattern P1 formed by the above-described stamping process with the first conductive material M1. The first conductive material M1 may include various metal materials. For example, the first conductive material M1 may include a metal material having excellent conductivity, such as copper, gold, or silver.

Referring to FIG. 17, when the step (S204) of forming the first conductive via 104 and the redistribution layer 105 is completed, the first conductive material M1 is used as the first insulating layer 103 and cultivated. The line layer 105 may be covered with a thickness of about 1 micrometer to about 4 micrometers.

18 is a diagram illustrating a step S205 of etching the first conductive material M1 according to an embodiment of the present disclosure. 3 and 18, the method S200 of manufacturing a semiconductor package of the present disclosure may include etching the first conductive material M1 (S205 ). More specifically, in the step of etching the first conductive material M1 (S205), as described above, the first conductive material M1 covering the first insulating layer 103 and the redistribution layer 105 is etched, It may include exposing the redistribution layer 105 and the first insulating layer 103 to the outside.

In one embodiment, when the redistribution layer 105 and the first insulating layer 103 are exposed to the outside, the first surface 105a and the first insulating layer 103 of the redistribution layer 105 are substantially It can be at the same height. Also, a surface and side surfaces of the redistribution layer 105 facing the first surface 105a may be surrounded by the first insulating layer 103. Since the redistribution layer 105 can be buried inside the first insulating layer 103, the redistribution layer 105 can be firmly positioned inside the first insulating layer 103, and the first semiconductor package The thickness of (100a) can be made thinner.

In an embodiment, unlike FIG. 18, the first surface 105a of the redistribution layer 105 may be at a lower height than the first insulating layer 103. In other words, the first surface 105a of the redistribution layer 105 may be closer to the semiconductor chip 101 than the surface exposed to the outside of the first insulating layer 103. Accordingly, a step may occur between the first surface 105a of the redistribution layer 105 and the surface exposed to the outside of the first insulating layer 103.

19 is a view showing a step (S206) of applying the second insulating layer 106 on the first insulating layer 103 according to an embodiment of the present disclosure. 3 and 19, the method S200 of manufacturing a semiconductor package of the present disclosure may include a step S206 of applying the second insulating layer 106 on the first insulating layer 103. . More specifically, in the step of applying the second insulating layer 106 (S206), the second insulating layer 106 on the first insulating layer 103 has a thickness of about 20 micrometers to about 50 micrometers. It may be a step of applying.

In one embodiment, the material of the first insulating layer 103 and the second insulating layer 106 may be substantially the same. However, the present invention is not limited thereto, and materials of the first insulating layer 103 and the second insulating layer 106 may be different.

FIG. 20 is a diagram illustrating a step S207 of forming a second via hole H2 and a UBM pattern P2 by stamping the second insulating layer 106 according to an exemplary embodiment of the present disclosure. 3 and 20, the method S200 of manufacturing a semiconductor package according to the present disclosure includes stamping the second insulating layer 106 to form a second via hole H2 and a UVM pattern P2. (Hereinafter, a second stamping process, S207) may be included. Since the technical idea of the second stamping process is substantially the same as the technical idea of the first stamping process described above, detailed information will be omitted.

In one embodiment, in the second stamping process (S207), the second insulating layer 106 is pressed with the second stamp 70 including the protrusions 73 in the micrometer unit or the nanometer unit, and the second insulating layer ( The step of forming the second via hole H2 and the UBM pattern P2 in 106) may be included. For example, the second stamping process S207 may include simultaneously forming a second via hole H2 and a UVM pattern P2 in the second insulating layer 106.

In one embodiment, the second stamp 70 protrusion 73 may include a second via hole protrusion 71 and a UBM protrusion 72. More specifically, the second via hole protrusion 71 may form a second via hole H2 in the second insulating layer 106, and the UBM protrusion 72 may be formed in the second insulating layer 106. An M pattern P2 may be formed.

In an embodiment, after the second stamping process (S207), an additional thermal curing process may be performed. The second via hole H2 and the UVM pattern P2 may be stably formed in the second insulating layer 106 through the thermal curing process.

In the semiconductor package manufacturing method S200 according to the exemplary embodiment of the present disclosure, the second via hole H2 and the UBM pattern P2 may be formed through the second stamping process S207, so that the second insulating layer (103) may include a variety of materials. More specifically, since the second via hole H2 and the UBM pattern P2 may be formed in the second insulating layer 106 through the second stamping process (S207), the second insulating layer 106 It may contain a photosensitive material. Accordingly, the selection of a material for the second insulating layer 106 may be wider, and the manufacturing cost of the first semiconductor package 100a may be reduced.

21 is a diagram illustrating an operation (S208) of etching a second via hole H2 according to an embodiment of the present disclosure. 3 and 21, the method S200 of manufacturing a semiconductor package of the present disclosure may include etching the second via hole H2 (S208 ). More specifically, the step of etching the second via hole H2 (S208) may be a step of etching the second insulating layer 106 located at the lowermost portion of the second via hole H2. The second insulating layer 106 located at the bottom of the second via hole H2 may be etched to expose the redistribution layer 105 to the outside.

In an embodiment, the step of etching the second via hole H2 (S208) may include the above-described plasma etching process. In addition, the step of etching the second via hole H2 (S208) may selectively include the above-described ultrasonic cleaning process. Since the technical idea of the plasma etching process and the ultrasonic cleaning process is substantially the same as the above-described technical idea, detailed information will be omitted.

In one embodiment, the diameter of the second via hole H2 etched by the step S208 of etching the second via hole H2 may be about 5 micrometers to about 20 micrometers, and the depth may be about 3 micrometers. It may be between micrometers and 12 micrometers.

22 is a diagram illustrating a step S209 of forming the second conductive via 107 and the first MB 108a according to an embodiment of the present disclosure. 3 and 22, the method S200 of manufacturing a semiconductor package of the present disclosure may include forming the second conductive via 107 and the first MB 108a (S209). More specifically, in the forming of the second conductive via 107, the second via hole H2 formed by the above-described second stamping process (S207) and etching process (S208) is used as a second conductive material (M2). It may include a filling step. In addition, the forming of the first UVM 108a may include filling the UVM pattern P2 formed by the above-described second stamping process S207 with the second conductive material M2. The conductive material may include various metal materials. For example, the second conductive material M2 may include a metal material having excellent conductivity, such as copper, gold, or silver.

Referring to FIG. 22, when the step (S204) of forming the second conductive via 107 and the first MB 108a is completed, the second conductive material M2 is used as the second insulating layer 106 and The first UVM 108a may be covered with a thickness of about 1 micrometer to about 4 micrometers.

23 is a diagram illustrating a step S210 of etching the second conductive material M2 according to an embodiment of the present disclosure. 3 and 23, the method S200 of manufacturing a semiconductor package of the present disclosure may include etching the second conductive material M2 (S210 ). More specifically, in the step of etching the second conductive material M2 (S210), as described above, the second conductive material M2 covering the second insulating layer 106 and the first UVM 108a is etched. , Exposing the first UVM 108a and the second insulating layer 106 to the outside.

In one embodiment, when the second insulating layer 106 and the first UVM 108a are exposed to the outside, the second insulating layer 106 and the first surface 108i of the first UVM 108a are It can be at substantially the same height. In addition, a surface and side surfaces of the first UVM 108a facing the first surface 108i may be surrounded by the second insulating layer 106. Since the first UVM 108a can be buried inside the second insulating layer 106, the first UVM 108a can be firmly positioned inside the second insulating layer 106, and is a semiconductor package. The thickness of (100) can be made thinner.

In an embodiment, unlike FIG. 23, the surface exposed to the outside of the first UVM 108a may be at a lower height than the surface exposed to the outside of the second insulating layer 106. In other words, the surface exposed to the outside of the first UVM 108a may be closer to the semiconductor chip 101 than the surface exposed to the outside of the second insulating layer 103. Accordingly, a step may occur between a surface exposed to the outside of the first UVM 108a and a surface exposed to the outside of the second insulating layer 106.

24 is a diagram illustrating a step (S211) of mounting a first external connection terminal 109a according to an embodiment of the present disclosure. 3 and 24, the method S200 of manufacturing a semiconductor package of the present disclosure may include mounting the first external connection terminal 109a (S211). More specifically, in the step of mounting the first external connection terminal 109a (S211), the first external connection terminal 109a is mounted on the first UVM 108a, 1 A step (S211) of electrically connecting the external connection terminals 109a may be included.

Referring to FIG. 24, the step of mounting the first external connection terminal 109a includes mounting the external connection terminal 109 so as to contact the first surface 108i of the first UVM 108a. I can. In addition, the step of mounting the first external connection terminal 109a (S11) may include processing the first external connection terminal 109a into various shapes such as a cylinder, a polygonal column, and a polyhedron.

25 is a flowchart of a method S300 of manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure. More specifically, FIG. 25 may be a flowchart of a method S200 of manufacturing the second semiconductor package 100b.

In the semiconductor package manufacturing method (S300) of the present disclosure, the step of applying the first insulating layer 103 on the first surface 121 of the semiconductor chip 101 (S301), stamping the first insulating layer 103 ( Stamping) to form the first via hole H1 and the redistribution pattern P1 (S302), etching the first via hole H1 (S303), the first conductive via 104 and the redistribution The step of forming the layer 105 (S304), the step of etching the first conductive material (M1) (S305), the step of applying the second insulating layer 106 on the first insulating layer 103 (S306) , Stamping the second insulating layer 103 to form a second via hole H2 (S307), etching the second via hole H2 (S308), and forming a second conductive via 107 (S309), etching the second conductive material (M2) (S310), forming a second MB (108b) on the second insulating layer (106) through a photolithography process (S311), And mounting the second external connection terminal 109b (S312).

In an embodiment, the step of applying the first insulating layer 103 on the first surface 121 of the semiconductor chip 101 (S301), and stamping the first insulating layer 103 to obtain a first via. Forming the hole H1 and the redistribution pattern P1 (S302), etching the first via hole H1 (S303), forming the first conductive via 104 and the redistribution layer 105 Step S304, etching the first conductive material M1 (S305), and applying the second insulating layer 106 on the first insulating layer 103 (S306), the second insulating layer Stamping 103 to form a second via hole H2 (S307), etching the second via hole H2 (S308), and forming a second conductive via 107 (S309) , And etching the second conductive material M2 (S310) is substantially the same as the technical idea described with reference to FIGS. 3 to 23, and thus detailed information will be omitted.

26 is a diagram illustrating a step (S311) of forming a second BB 108b on the second insulating layer 106 through a photolithography process according to an embodiment of the present disclosure.

In one embodiment, the second UVM 108b may be formed on the second insulating layer 106 through a photolithography process. Accordingly, the second UVM 108b may not be buried in the second insulating layer 106 and may be formed to protrude from the second insulating layer 106. Accordingly, the side surface of the UBM 108b may be exposed to the outside.

27 is a diagram illustrating a step (S312) of mounting a second external connection terminal 109b according to an embodiment of the present disclosure. In one embodiment, the step of mounting the second external connection terminal 109b (S312) includes mounting the external connection terminal on the second insulating layer 106 so as to surround the side surface of the second UVM 109b. Can include. Accordingly, the second external connection terminal 109b of the second semiconductor package 100b may be rigidly mounted on the second semiconductor package 100b. Accordingly, durability of the second external connection terminal 109b may be increased, and a risk of damage to the second semiconductor package 100b may be reduced.

The semiconductor package manufacturing methods S200 and S300 according to the embodiments of the present disclosure may include the above-described processes to reduce the production cost of the first and second semiconductor packages 100a and 100b.

In addition, the semiconductor package manufacturing methods S200 and S300 according to the embodiments of the present disclosure can produce thin, light, and durable first and second semiconductor packages 100a and 100b including the above-described processes. have.

28 is a block diagram schematically illustrating an electronic system 1700 including first and second semiconductor packages 100a and 100b according to an embodiment of the present disclosure.

Referring to FIG. 28, the electronic system 1700 may include first and second semiconductor packages 100a and 100b according to the technical idea of the present disclosure. The electronic system 1700 may be included in a mobile device or a computer. For example, the electronic system 1700 may include a memory system 1701, a microprocessor 1702, a RAM 1703, and a user interface 1704 for performing data communication.

As described above, exemplary embodiments have been disclosed in the drawings and specification. In the present specification, embodiments have been described using specific terms, but these are used only for the purpose of describing the technical idea of the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (21)

A semiconductor chip in which a chip pad is formed on a first surface;
A first insulating layer on the first surface of the semiconductor chip;
A first conductive via electrically connected to the chip pad and formed through the first insulating layer;
A redistribution layer electrically connected to the first conductive via and buried in the first insulating layer;
A second insulating layer on the first insulating layer and in contact with the redistribution layer;
A second conductive via electrically connected to the redistribution layer and formed through the second insulating layer;
A UBM buried in the second insulating layer so as to be electrically connected to the second conductive via, and having a side surface surrounded by the second insulating layer and a surface coplanar with the surface of the second insulating layer; And
An external connection terminal contacting the surface of the UVM and electrically connected to the UVM;
Including,
The surface of the second insulating layer, the surface of the UVM, and one surface of the external connection terminal in contact with the UVM are on the same plane,
A surface formed by contacting the redistribution layer and the second insulating layer is disposed closer to the semiconductor chip than a surface formed by contacting the first insulating layer and the second insulating layer,
The semiconductor package, wherein the thickness of the first insulating layer and the thickness of the second insulating layer are 20 micrometers to 50 micrometers, respectively. The method of claim 1,
Wherein the first insulating layer and the second insulating layer include a non-photosensitive material. The method of claim 1,
The semiconductor package, characterized in that the material of the first insulating layer and the second insulating layer are different. The method of claim 3,
Side surfaces of the redistribution layer are surrounded by the first insulating layer,
A semiconductor package, wherein a first surface of the redistribution layer exposed on the first insulating layer contacts the second insulating layer. delete The method of claim 1,
A semiconductor package, wherein the sum of the thicknesses of the first conductive via, the redistribution layer, the second conductive via, and the UVM is equal to the sum of the thicknesses of the first insulating layer and the second insulating layer. delete delete delete delete Applying a first insulating layer on the first surface of the semiconductor chip on which the chip pad is formed;
Stamping the first insulating layer to form a first via hole and a redistribution pattern;
Forming a first conductive via and a redistribution layer by filling the first via hole and the redistribution pattern with a first conductive material;
Applying a second insulating layer on the first insulating layer;
Stamping the second insulating layer to form a second via hole and a UVM pattern;
Filling the second via hole and the UVM pattern with a second conductive material to form a second conductive via and a UVM; And
Mounting an external connection terminal on the UBM;
A semiconductor package manufacturing method comprising a. The method of claim 11,
Exposing the chip pad by etching the first insulating layer in the portion where the first via hole is formed;
Etching the first conductive material and exposing the redistribution layer and the first insulating layer to the outside;
Exposing the redistribution layer by etching the second insulating layer in the portion where the second via hole is formed; And
Etching the second conductive material and exposing the UVM and the second insulating layer to the outside;
A semiconductor package manufacturing method comprising a. The method of claim 11,
Stamping the first insulating layer to form the first via hole and the redistribution pattern,
Stamping the first insulating layer to form the first via hole and the redistribution pattern at the same time;
Method for manufacturing a semiconductor package comprising a The method of claim 11,
Stamping the first insulating layer to form the first via hole and the redistribution pattern,
Stamping the first insulating layer with a via hole stamp having a first protrusion formed thereon to form the first via hole; And
Stamping the first insulating layer with a redistribution stamp having a second protrusion formed thereon to form the redistribution pattern;
A method of manufacturing a semiconductor package comprising a. The method of claim 14,
In the step of forming the first via hole by stamping the first insulating layer with the via hole stamp,
The method of manufacturing a semiconductor package, wherein the first protrusion includes a curved surface convex from a lower portion. The method of claim 14,
The step of forming the redistribution pattern by stamping the first insulating layer with the redistribution stamp having the second protrusion formed thereon,
Filling the second protrusion in the first insulating layer; And
The buried second protrusion is separated from the first insulating layer to form the redistribution pattern; Including,
In the step of embedding the second protrusion in the first insulating layer, when the redistribution stamp is viewed from top to bottom, the center of the first via hole does not overlap with the second protrusion. Way. The method of claim 11,
The step of forming the first via hole and the redistribution pattern by stamping the first insulating layer,
Forming the first via hole and the redistribution pattern by stamping the first insulating layer with a stamp having a protrusion formed thereon,
A method of manufacturing a semiconductor package, wherein the surface of the protrusion is patterned in a hatching shape. Applying a first insulating layer on the first surface of the semiconductor chip on which the chip pad is formed;
Stamping the first insulating layer to form a first via hole and a redistribution pattern;
Forming a first conductive via and a redistribution layer by filling the first via hole and the redistribution pattern with a first conductive material;
Applying a second insulating layer on the first insulating layer;
Stamping the second insulating layer to form a second via hole;
Filling the second via hole with a second conductive material to form a second conductive via;
Forming a UVM on the second insulating layer through a photolithography process; And
Mounting an external connection terminal on the UBM;
A semiconductor package manufacturing method comprising a. The method of claim 18,
Exposing the chip pad by etching the first insulating layer in the portion where the first via hole is formed;
Etching the first conductive material and exposing the redistribution layer and the first insulating layer to the outside;
Exposing the redistribution layer by etching the second insulating layer in the portion where the second via hole is formed; And
Etching the second conductive material and exposing the second insulating layer to the outside;
A semiconductor package manufacturing method comprising a. The method of claim 18,
Mounting the external connection terminal
And mounting the external connection terminal on the second insulating layer to surround a side surface of the UVM. delete

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