KR102256085B1 - Display device and driving method of the same - Google Patents

Abstract

The display device according to the present invention includes a display panel and a gate driving circuit that supplies a gate output signal to gate lines of the display panel, including a plurality of stages to which gate shift clocks are applied, and a default resolution different from that of the display panel. When information on the variant resolution is input, a first control unit for generating a modulated data enable signal by modulating the input data enable signal corresponding to the default resolution according to the variant resolution, and the modulated data enable signal Based on this, a second control unit is provided to adjust the output timing of the reset logic pulses for simultaneously resetting the stages and to adjust the number of gate logic clocks that are the basis for the generation of the gate shift clocks.

Description

Display device and its driving method {DISPLAY DEVICE AND DRIVING METHOD OF THE SAME}

The present invention relates to a display device and a driving method thereof.

Currently, various flat panel displays (FPDs) are being developed and marketed. A gate driving circuit of such a display device generally drives gate lines of a display panel using a gate shift register.

The gate driving circuit of the display device may be directly formed in a non-display area of the display panel through a TFT (Thin Film Transistor) process of a gate driver in panel (GIP) method in order to reduce a process procedure and manufacturing cost. The gate driving circuit formed by the GIP method is advantageous in reducing the bezel of the display device compared to the integrated circuit (IC) type gate driving circuit.

The gate shift register of the gate driving circuit includes a plurality of stages (SG1 to SG6, ...) connected in a cascade as shown in FIG. 1 and sequentially outputs the gate according to the gate shift clock (Gate CLK1 to 6). A signal (or scan signal) (Vg1 to Vg6,...) may be generated. Among the stages SG1 to SG6, ...), some of the stages SG1 to SG3 may be set simultaneously in response to the gate start signal VST applied from the outside, and other stages except for the some stages SG1 to SG3. The stages SG4 to SG6, ... may be set in response to a carry signal from the previous stages. For example, the nth stage (n is a positive integer greater than 4) may be set by receiving a gate output signal output from the n-3th stage as a carry signal. The stages SG1 to SG6, ... may be first reset in response to a reset signal from subsequent stages. For example, the m-th stage (m is a positive integer) may receive a gate output signal output from the m+3-th stage as a reset signal and may be first reset.

The gate shift register further includes an additional reset process of resetting all stages at the same time every frame in order to increase the safety of the operation. In other words, at the end of each frame when the scan signal is output, the stages SG1 to SG6, ... are re-reset simultaneously in response to the gate start signal VST applied from the outside, and unnecessary residuals of each stage. Discharge the electric charge.

Meanwhile, the gate start signal VST and the gate shift clocks Gate CLK1 to 6 required for the operation of the gate shift register are generated by the level shifter. The level shifter generates a gate start signal (VST) suitable for driving the pixel array by level shifting the gate logic signal (GSP) of the TTL (Transistor Transistor Logic) level input from the timing controller, and also generates the TTL level input from the timing controller. Gate shift clocks (Gate CLK1 to 6) suitable for driving the pixel array are generated based on the gate logic clock GCLK. As shown in FIG. 2, the gate start signal VST includes a start signal VTS_S used to set some stages and a reset signal VTS_E used to secondary reset all stages at the same time. The signal VTS_S is synchronized with the start logic pulse GSP_S of the gate logic signal GSP, and the reset signal VTS_E is synchronized with the reset logic pulse GSP_E of the gate logic signal GSP. In general, within one frame, the gate logic clock (GCLK) is located between the start logic pulse (GSP_S) and the reset logic pulse (GSP_E) of the gate logic signal (GSP), and is set to a number corresponding to the vertical resolution of the display panel. do.

As described above, in the prior art, the gate logic signal GSP and the gate logic clock GCLK are fixed and fixed according to the predetermined resolution of the display panel, that is, the default resolution. That is, in FIG. 2, the gate logic clock GCLK is set to have the number of vertical resolutions (eg, 1080) of the display panel during one frame, and the reset logic pulse GSP_E of the gate logic signal GSP is It is generated after a predetermined period of delay from the last pulse (for example, the 1080th pulse) of the logic clock GCLK.

Since the timing controller fixes the gate logic timing according to the default resolution, if the resolution of the display panel is changed to a variant resolution smaller than the default resolution, it cannot cope with it. As shown in FIG. 3, the gate logic timing is changed even if the display panel is changed to a variant size smaller than the original size (e.g., corresponding to the default resolution (1920*1080)) (e.g., corresponding to the variant resolution (1920*200)). However, regardless of such a resolution change, since it is fixed to the default value, it causes a reliability problem of the panel.

Specifically, the user may process (eg, cut) the display panel into a different size from the original size for various purposes. The vertical resolution of the display panel may be changed from the default resolution 1080 to the variant resolution 200 by the user. In this case, stages after the 200th stage (the stage 1080 from the 201st stage) are removed. Accordingly, under the reset structure as shown in FIG. 1, the 198th to 200th stages do not receive the gate output signal for the primary reset from the lower stages (201th to 203th stages), so that the 198th to 200th stages The primary reset of the gate logic signals GSP is impossible, and the leakage current continues to be affected until the time when the reset logic pulse GSP_E of the gate logic signal GSP is generated.

However, since the reset logic pulse GSP_E of the gate logic signal GSP is generated after a fixed timing according to the default resolution 1080, that is, delayed for a predetermined period from the 1080th pulse of the gate logic clock GCLK, as described above, 198 The th to 200 th stages are affected by the leakage current for a long time (Pa in FIG. 2) within one frame. The gate output signals of the 198th to 200th stages may be distorted due to the influence of the leakage current. If the gate output signal is distorted, the charging capacity of the image data in the corresponding display line is degraded, so that a line dim can be seen.

Accordingly, an object of the present invention is to provide a display device and a method of driving the same to increase panel reliability by adjusting the gate logic timing according to the release resolution when a release resolution different from the default resolution of the display panel is detected.

In order to achieve the above object, a display device according to an embodiment of the present invention includes a display panel and a plurality of stages to which gate shift clocks are applied, and a gate driving circuit that supplies a gate output signal to gate lines of the display panel. And, when information about a variant resolution different from the default resolution of the display panel is input, a first for generating a modulated data enable signal by modulating an input data enable signal corresponding to the default resolution according to the variant resolution. Based on the control unit and the modulated data enable signal, the output timing of the reset logic pulse for simultaneously resetting the stages is adjusted, and the number of gate logic clocks that are the basis for the generation of the gate shift clocks And a second control unit to adjust.

The display device further includes a memory for storing the release resolution information in advance and supplying it to the first control unit.

The display device further includes an image analysis unit that analyzes the input digital video data to derive the variant resolution information and then supplies it to the first control unit.

When the information on the variant resolution is input, the first control unit generates a masking signal suitable for the variant resolution, and then logically calculates the masking signal and the input data enable signal to generate the modulated data enable signal. Generate.

When the variant resolution is less than the default resolution, the second control unit sets the output timing of the reset logic pulse to a second timing that is faster than the first timing corresponding to the default resolution based on the modulated data enable signal. In addition, the number of gate logic clocks is reduced to a second value smaller than the first value corresponding to the default resolution.

According to an exemplary embodiment of the present invention, a method of driving a display device having a display panel and a gate driving circuit that supplies a gate output signal to gate lines of the display panel including a plurality of stages to which gate shift clocks are applied, includes: A first step of generating a modulated data enable signal by modulating an input data enable signal corresponding to the default resolution according to the variant resolution when information on a variant resolution different from the default resolution of the display panel is input; Based on the modulated data enable signal, the output timing of the reset logic pulse for simultaneously resetting the stages is adjusted, and the number of gate logic clocks that are the basis for the generation of the gate shift clocks is adjusted. Includes two steps.

According to the present invention, when a variant resolution different from the default resolution of the display panel is detected, the gate logic timing is adjusted according to the release resolution, thereby improving panel reliability.

1 is a diagram showing a configuration of a gate shift register.
2 is a view showing a gate logic timing fixed according to a conventional default resolution, a gate start signal and a gate shift clock according thereto.
3 is a diagram illustrating an example in which a resolution of a display panel is changed to a value smaller than a default value as the panel is cut.
4 is a block diagram showing a display device according to an exemplary embodiment of the present invention.
5 and 6 are diagrams showing examples of adjusting gate logic timing according to an anomaly resolution.
7 is a diagram showing an internal configuration of a timing controller according to a scheme for detecting a variant resolution.
FIG. 8 is a diagram illustrating a timing controller modulating a data enable signal according to an anomaly resolution.
9 is a view showing another scheme for detecting a variant resolution and an internal configuration of a timing controller according thereto.
10 is a diagram showing input data corresponding to a default resolution and image data corresponding to a variant resolution.
11 is a diagram showing a driving method according to the present invention for adjusting gate logic timing according to an anomaly resolution.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted. In the following description, the display device is described centering on the liquid crystal display device, but it should be noted that the technical idea of the present invention is not limited to the liquid crystal display device and can be applied to other display devices.

4 schematically shows a display device according to an exemplary embodiment of the present invention. 5 and 6 show examples of adjusting gate logic timing according to anomalous resolution.

4, the display device of the present invention includes a display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, a power circuit including a level shifter 15, and the like. It is equipped with.

The display panel 10 includes data lines and gate lines intersecting each other, and pixels arranged in a matrix form.

The display device of the present invention may be implemented in all known liquid crystal modes such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS (Fringe Field Switching). In addition, the display device of the present invention may be implemented in any form such as a transmissive liquid crystal display, a transflective liquid crystal display, and a reflective liquid crystal display.

The display panel 10 includes an upper substrate and a lower substrate facing each other with a liquid crystal cell Clc interposed therebetween. In the display panel 10, the image data RGB is displayed on a pixel array in which pixels are arranged in a matrix form. The pixel array includes a TFT array formed on a lower substrate and a color filter array formed on an upper substrate. In a TFT array, thin film transistors (TFTs) are formed at each intersection of data lines and gate lines. The TFT supplies a data voltage from the data line to the pixel electrode 1 of the liquid crystal cell Clc in response to the gate output signal from the gate line. Each of the liquid crystal cells Clc implements a desired gray scale by controlling the light transmittance by a potential difference between the data voltage charged in the pixel electrode 1 and the common voltage Vcom applied to the common electrode 2. A storage capacitor Cst for maintaining the data voltage charged in the pixel electrode 1 for one frame period is connected to the liquid crystal cell Clc. The color filter array includes a color filter and a black matrix. A polarizing plate is attached to each of the upper and lower glass substrates of the display panel 10 and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

The data driving circuit 12 may be implemented as a source drive IC. The data driving circuit 12 receives digital video data RGB from the timing controller 11. The data driving circuit 12 converts digital video data (RGB) into a gamma compensation voltage in response to a source timing control signal from the timing controller 11 to generate a data voltage, and synchronizes the data voltage to the gate output signal. It is supplied to the data lines of the display panel 10 as possible. The data driving circuit 12 may be connected to the data lines of the display panel 10 through a chip on glass (COG) process or a tape automated bonding (TAB) process.

The gate driving circuit 13 may be directly formed on the lower substrate of the display panel 10 in a GIP (Gate In Panel) method. The gate driving circuit 13 may be formed in the non-display area BZ outside the pixel area in which an image is displayed on the display panel 10. The gate driving circuit 13 generates a gate output signal (scan signal) based on the gate control signals VST and Gate CLKs input from the level shifter 15, and gates the gate in a line-sequential manner. Supply to the lines. One display line to be charged with the data voltage is selected according to the gate output signal.

The gate shift register of the gate driving circuit includes a plurality of stages (SG1 to SG6, ...) connected in a cascade as shown in FIG. 1 and sequentially outputs the gate according to the gate shift clock (Gate CLK1 to 6). A signal (or scan signal) (Vg1 to Vg6,...) may be generated. Among the stages SG1 to SG6, ...), some of the stages SG1 to SG3 may be set simultaneously in response to the gate start signal VST applied from the outside, and other stages except for the some stages SG1 to SG3. The stages SG4 to SG6, ... may be set in response to a carry signal from the previous stages. For example, the nth stage (n is a positive integer greater than 4) may be set by receiving a gate output signal output from the n-3th stage as a carry signal. The stages SG1 to SG6, ... may be first reset in response to a reset signal from subsequent stages. For example, the m-th stage (m is a positive integer) may receive a gate output signal output from the m+3-th stage as a reset signal and may be first reset. The gate shift register further includes an additional reset process of resetting all stages at the same time every frame in order to increase the safety of the operation. That is, the stages SG1 to SG6, ... are secondarily reset at the same time in response to the gate start signal VST applied from the outside to discharge unnecessary residual charge of each stage.

The level shifter 15 generates a gate start signal VST and gate shift clocks Gate CLK1 to 6 required for the operation of the gate shift register. The level shifter 15 level-shifts a gate logic signal (GSP) of a TTL (Transistor Transistor Logic) level input from the timing controller 11 to generate a gate start signal (VST) suitable for driving a pixel array, and a timing controller Based on the TTL level gate logic clock GCLK input from (11), gate shift clocks (Gate CLK1 to 6) suitable for driving the pixel array are generated. 5 and 6, the gate start signal VST includes a start signal VTS_S used to set some stages and a reset signal VTS_E used to secondary reset all stages at the same time. , The start signal VTS_S is synchronized with the start logic pulse GSP_S of the gate logic signal GSP, and the reset signal VTS_E is synchronized with the reset logic pulse GSP_E of the gate logic signal GSP. .

The timing controller 11 receives digital video data (RGB) from an external host system through a predetermined interface circuit, and transmits the digital video data (RGB) to the data driving circuit 12 through a predetermined interface circuit. do.

The timing controller 11 is a timing signal corresponding to the default resolution of the display panel 10 from an external host system through a predetermined interface circuit, that is, a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and a data enable signal. (Data Enable, DE), etc. are input. The timing controller 11 generates a gate logic signal GSP and a gate logic clock GCLK based on the timing signal. In general, within one frame, the gate logic clock (GCLK) is located between the start logic pulse (GSP_S) and the reset logic pulse (GSP_E) of the gate logic signal (GSP), and is set to a number corresponding to the vertical resolution of the display panel. do.

When information about a variant resolution different from the default resolution of the display panel 10 is input, the timing controller 11 uses gate shift clocks (Gate CLK1 to 6) to minimize leakage current due to an incomplete primary reset. The number of gate logic clocks (GCLK), which is the basis for the generation of, is adjusted according to the variant resolution, and the output timing of the reset logic pulse (GSP_E) of the gate logic signal (GSP) for secondary reset of the stages at the same time is adjusted. Can be adjusted. That is, the timing controller 11 of the present invention does not fix the gate logic timing according to the default resolution, but when the resolution of the display panel 10 is changed to a variant resolution smaller than the default resolution, the gate logic timing can be changed accordingly. Is designed.

For example, when the display panel is changed to a variant size smaller than the original size (e.g., corresponding to the default resolution (1920*1080)) as shown in FIG. 3 (e.g., corresponding to the variant resolution (1920*200)) , The timing controller 11 reduces the number of gate logic clocks GCLK to 200 according to the vertical anomaly resolution 200 as shown in FIGS. 5 and 6, and outputs a reset logic pulse (GSP_E) within one frame. The timing may be advanced by "Td" from the first viewpoint t1 corresponding to the default vertical resolution 1080 to the second viewpoint t2 corresponding to the variant vertical resolution 200. At this time, the reset signal VTS_E of the gate start signal VST is also synchronized with the reset logic pulse GSP_E of the gate logic signal GSP, and is advanced to the second time point t2.

For various purposes, the user can process (eg, cut) the display panel in a different size from the original size. In this case, the lower stages of the gate shift register (for the vertical resolution '200', the 198th to the 200th Stages) may become impossible to perform a primary reset. However, as in the present invention, if the reset signal VTS_E of the gate start signal VST is advanced in accordance with the deform resolution of the display panel 10, the period in which the leakage current is caused in the lower stages is minimized, and accordingly, the conventional Panel reliability problems such as do not occur.

The level shifter 15 of the present invention outputs the gate control signals VST and Gate CLK1 to 6 based on the gate logic timing adjusted for the variant resolution. The level shifter 15 may generate a gate shift clock (Gate CLK1-6) based only on the gate logic clock (GCLK) as shown in FIG. 5, and as shown in FIG. 6, the gate modulation clock ( A gate shift clock (Gate CLK1-6) may be generated based on MCLK).

In FIG. 5, each gate shift clock is raised in synchronization with a rising edge of the k+1th gate logic clock GCLK, and a falling edge of the k+3rd gate logic clock GCLK. It can be polled in synchronization with. In FIG. 6, each gate shift clock is raised in synchronization with a rising edge of the k+1th gate logic clock GCLK, and a rising edge of the k+3rd gate modulation clock MCLK. The first polling may be performed in synchronization with the k+3 th gate modulation clock MCLK and the second polling may be performed in synchronization with the falling edge of the k+3 th gate modulation clock MCLK. The shape of the gate output signal applied to the TFT of the display panel 10 is determined according to the gate shift clock. Accordingly, when the gate shift clock is generated in the form of FIG. 6, the off characteristic of the gate output signal is improved, thereby reducing the kick back voltage. This is described in detail in Patent Publication No. 10-2014-0041023, Patent Publication No. 10-2011-0101901, etc. previously filed by the applicant of the present application.

7 is a diagram illustrating a method of detecting an anomaly resolution and an internal configuration of a timing controller according thereto. In addition, FIG. 8 shows that the timing controller modulates the data enable signal according to the variant resolution.

Referring to FIG. 7, the timing controller 11 of the present invention includes a first control unit 111 that modulates a data enable signal and a second control unit 112 that controls a gate logic timing in accordance with a modulated data enable signal MDE. ), and a third control unit 113 for arranging digital video data according to the modulated data enable signal MDE.

The display device of the present invention may further include a memory 20 that stores the variant resolution information VRI in advance and then supplies it to the first control unit 111. When information (VRI) on a variant resolution different from the default resolution of the display panel is input from the memory 20, the first control unit 111 receives the input data enable signal DE corresponding to the default resolution. By modulating accordingly, a modulated data enable signal (MDE) may be generated.

To this end, the first controller 111 generates a masking signal (MSK) suitable for the variant vertical resolution (for example, "200") as shown in FIG. 8 when the information on the variant resolution (VRI) is input. , The modulated data enable signal MDE may be generated by performing a logical operation on the masking signal MSK and the input data enable signal DE.

The second control unit 112 adjusts the output timing of the reset logic pulse GSP_E for simultaneously resetting the stages of the gate shift register based on the modulated data enable signal MDE (as shown in FIGS. 5 and 6 ). t1 to t2), and the number of gate logic clocks GCLK, which is the basis for the generation of the gate shift clocks Gate CLK1 to 6, may be adjusted.

The third control unit 113 processes, arranges and outputs the input digital video data RGB according to the modulated data enable signal MDE.

9 shows another scheme for detecting a variant resolution and an internal configuration of a timing controller according thereto. In addition, FIG. 10 shows input data corresponding to the default resolution and image data corresponding to the variant resolution.

Referring to FIG. 9, the timing controller 11 of the present invention includes a first control unit 111 that modulates a data enable signal and a second control unit 112 that controls a gate logic timing in accordance with a modulated data enable signal MDE. ), and a third control unit 113 for arranging digital video data according to the modulated data enable signal MDE.

The display device of the present invention may further include an image analysis unit 30 that analyzes input digital video data RGB to derive variant resolution information VRI and then supplies it to the first control unit 111. The data pattern as shown in FIG. 10A may be designed in advance by a user and supplied to the image analysis unit 30 through a system. In the data pattern of Fig. 10A, image data is data for image display, and dummy data indicates data not related to image display. When the data pattern as shown in FIG. 10A is repeatedly input for a predetermined period of time or more, the image analysis unit 30 detects a resolution (1920*200) corresponding to only image data as a variant resolution, and the variant resolution information (VRI) Can be printed.

The first control unit 111 modifies the input data enable signal DE corresponding to the default resolution when information (VRI) about a variant resolution different from the default resolution of the display panel is input from the image analysis unit 30. By modulating according to the resolution, a modulated data enable signal (MDE) may be generated.

To this end, the first controller 111 generates a masking signal (MSK) suitable for the variant vertical resolution (for example, "200") as shown in FIG. 8 when the information on the variant resolution (VRI) is input. , The modulated data enable signal MDE may be generated by performing a logical operation on the masking signal MSK and the input data enable signal DE.

The second control unit 112 adjusts the output timing of the reset logic pulse GSP_E for simultaneously resetting the stages of the gate shift register based on the modulated data enable signal MDE (as shown in FIGS. 5 and 6 ). t1 to t2), and the number of gate logic clocks GCLK, which is the basis for the generation of the gate shift clocks Gate CLK1 to 6, may be adjusted.

The third control unit 113 processes, arranges and outputs the input digital video data RGB according to the modulated data enable signal MDE.

11 shows a driving method of the present invention in which the gate logic timing is adjusted according to the release resolution.

In the method of driving a display device according to the present invention, when information about a variant resolution different from the default resolution of the display panel is input, the input data enable signal corresponding to the default resolution is modulated according to the variant resolution, Generates (S10, S20).

Next, the method of driving the display device according to the present invention adjusts the output timing of the reset logic pulse for simultaneously resetting the stages of the gate shift register based on the modulated data enable signal, and generates gate shift clocks. The number of gate logic clocks that are based on is adjusted (S30).

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
15: level shifter 20: memory
30: image analysis unit 111,112,113: first to third control unit

Claims (10)

Display panel;
A gate driving circuit for supplying a gate output signal to gate lines of the display panel including a plurality of stages to which gate shift clocks are applied;
A first controller configured to generate a modulated data enable signal by modulating an input data enable signal corresponding to the default resolution according to the variant resolution when information on a variant resolution smaller than the default resolution of the display panel is input; And
Based on the modulated data enable signal, adjusting the output timing of the reset logic pulse for simultaneously resetting the stages, and adjusting the number of pulses of the gate logic clock that is the basis for the generation of the gate shift clocks. It has a second control unit,
The output timing of the reset logic pulse is adjusted within a fixed one frame period, and is pulled from a first timing corresponding to the default resolution to a second timing preceding it,
The number of pulses of the gate logic clock is adjusted within the fixed one frame period, but decreases from a first value corresponding to the default resolution to a second value smaller than that,
The second value is the same as the vertical resolution value of the variant resolution.
The method of claim 1,
A display device further comprising a memory for storing the deformed resolution information in advance and supplying it to the first control unit.
The method of claim 1,
A display device further comprising an image analysis unit for analyzing input digital video data to derive the variant resolution information and then supplying it to the first control unit.
The method of claim 1,
When the information on the variant resolution is input, the first control unit generates a masking signal suitable for the variant resolution, and then logically calculates the masking signal and the input data enable signal to generate the modulated data enable signal. Generating display.
delete A method of driving a display device having a display panel and a gate driving circuit that supplies a gate output signal to gate lines of the display panel, including a plurality of stages to which gate shift clocks are applied,
A first step of generating a modulated data enable signal by modulating an input data enable signal corresponding to the default resolution according to the variant resolution when information on a variant resolution smaller than the default resolution of the display panel is input; And
Based on the modulated data enable signal, adjusting the output timing of the reset logic pulse for simultaneously resetting the stages, and adjusting the number of pulses of the gate logic clock that is the basis for the generation of the gate shift clocks. Including a second step,
The output timing of the reset logic pulse is adjusted within a fixed one frame period, and is pulled from a first timing corresponding to the default resolution to a second timing preceding it,
The number of pulses of the gate logic clock is adjusted within the fixed one frame period, but decreases from a first value corresponding to the default resolution to a second value smaller than that,
The second value is the same as the vertical resolution value of the release resolution.
The method of claim 6,
The method of driving a display device further comprising the step of pre-storing the type resolution information in a memory.
The method of claim 6,
The method of driving a display device further comprising the step of analyzing input digital video data to derive the variant resolution information.
The method of claim 6,
The first step,
Generating a masking signal suitable for the variant resolution when information on the variant resolution is input; And
And generating the modulated data enable signal by performing a logical operation on the masking signal and the input data enable signal.
delete

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