KR102221543B1 - Power amplification circuit - Google Patents

Abstract

The power amplification circuit 1 includes an amplifying transistor 20, a variable voltage power supply 11 that supplies a variable voltage Vcc2 to the collector of the amplifying transistor 20, and a DC bias current to the base of the amplifying transistor 20. A bias circuit 22 having a constant current amplifying transistor 220 to output and a current limiting circuit 23 for limiting a direct current bias current are provided, and the current limiting circuit 23 includes a current limiting transistor 230 and a current limiting It has a resistance element 232 connected to the collector of the transistor 230 and the variable voltage power supply 11, and a resistance element 231 connected to the base of the current limiting transistor 230 and the base of the constant current amplifying transistor 220. .

Description

Power amplifier circuit {POWER AMPLIFICATION CIRCUIT}

The present invention relates to a power amplifier circuit.

[0003] With the miniaturization and weight reduction of mobile communication devices, there is a demand for miniaturization and reduction in power consumption of power amplifiers as well as miniaturization and longevity of mounted batteries. As a countermeasure for lowering the power consumption of the power amplifier, a method of tracking the power amplitude (envelope) of a high-frequency signal (envelope tracking method) and varying the voltage supply level to the power amplifier according to the envelope has been proposed (for example, Patent Document 1). Specifically, the voltage supply level to the power amplifier is increased in accordance with the rise of the envelope of the high-frequency signal, and the voltage supply level to the power amplifier is decreased in accordance with the decrease in the envelope. As a result, it is said that the power consumption (current consumption) of the power amplifier can be reduced.

Japanese Patent Laid-Open No. 2016-32301

However, for example, in a conventional power amplifier using an emitter-grounded bipolar transistor, even if the power supply voltage (collector voltage) is varied according to the power amplitude of the high-frequency signal, the direct current bias current supplied to the base terminal of the transistor Is approximately constant.

Since the collector-emitter current (driving current), which strongly affects the power addition efficiency, is correlated with the base-emitter current (DC bias current), if the base-emitter current is approximately constant, the collector-emitter current Also becomes approximately constant. For this reason, even if the power supply voltage (collector voltage) is varied in accordance with the power amplitude, the power addition efficiency is not significantly improved, and effective reduction of power consumption is not realized.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a power amplifier circuit with improved power addition efficiency.

In order to achieve the above object, a power amplifying circuit according to an aspect of the present invention is a power amplifying circuit for power amplifying a high-frequency signal, and has a first terminal, a second terminal, and a first control terminal, and the first control A first amplification transistor for power-amplifying a high-frequency signal input from a terminal and outputting the power-amplified high-frequency signal from the first terminal, a variable voltage power supply for supplying a variable voltage to the first terminal, and a DC bias current. A bias circuit for outputting and a current limiting circuit for limiting the DC bias current, the bias circuit having a third terminal, a fourth terminal, and a second control terminal, and the first control terminal from the fourth terminal And a constant current amplifying transistor that outputs the DC bias current toward, and the current limiting circuit has a fifth terminal, a sixth terminal, and a third control terminal, and the sixth terminal is connected to the fourth terminal. A transistor, one end connected to the fifth terminal, the other end connected to the variable voltage power supply, a first resistance element, one end connected to the third control terminal, and the other end connected to the second terminal It has a second resistance element connected to the control terminal.

(Effects of the Invention)

According to the present invention, it is possible to provide a power amplifier circuit with improved power addition efficiency.

1 is a configuration diagram of a power amplifier circuit and a peripheral circuit thereof according to a first embodiment.
2 is a configuration diagram of a power amplifier circuit and a peripheral circuit thereof according to Modification Example 1 of Embodiment 1. FIG.
3 is a schematic circuit diagram showing the connection of an amplifying transistor and its peripheral circuit.
4A is a graph showing a relationship between a power supply voltage and a collector current of a power amplifying circuit according to a comparative example.
4B is a graph showing the relationship between the power supply voltage and the collector current of the power amplifier circuit according to the first embodiment.
5A is a graph showing a relationship between high-frequency output power and power addition efficiency of a power amplifying circuit according to a comparative example.
5B is a graph showing the relationship between high-frequency output power and power addition efficiency of the power amplifying circuit according to the first embodiment.
6 is a graph for explaining the operation of the current limiting circuit according to the first embodiment.
7A is a configuration diagram of a power amplifier circuit and a peripheral circuit thereof according to Modification Example 2 of Embodiment 1. FIG.
7B is a configuration diagram of a power amplifying circuit and a peripheral circuit thereof according to Modification Example 3 of Embodiment 1. FIG.
8A is a graph comparing AM-AM characteristics of the power amplifying circuit according to the first embodiment and the power amplifying circuit according to the second modified example.
8B is a graph comparing AM-PM characteristics of the power amplifying circuit according to the first embodiment and the power amplifying circuit according to the second modified example.
9 is a configuration diagram of a power amplifying circuit and a peripheral circuit thereof according to the second embodiment.
10 is a graph showing the relationship between the transmission power of the mobile terminal and its frequency.
11A is a schematic waveform diagram illustrating the APT mode.
11B is a schematic waveform diagram explaining the ET mode.
12A is a graph showing a relationship between a high frequency output power and a gain and an APT variable voltage of a power amplifying circuit according to a comparative example. (b) is a graph showing the relationship between the high-frequency output power and the gain and the APT variable voltage of the power amplifying circuit according to the second embodiment.
13A is a graph showing a relationship between a high-frequency output power, a gain, a collector current, and the like of a power amplifying circuit according to a comparative example. (b) is a graph showing the relationship between the high-frequency output power of the power amplifying circuit according to the second embodiment, a gain, a collector current, and the like.
14 is a configuration diagram of a power amplifier circuit and a peripheral circuit thereof according to a modified example of the second embodiment.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the embodiment and its drawings. In addition, all of the embodiments described below represent comprehensive or specific examples. Numerical values, shapes, materials, constituent elements, arrangements and connection forms of constituent elements shown in the following embodiments are examples and are not intended to limit the present invention. Among the constituent elements in the following embodiments, constituent elements not described in the independent claims are described as arbitrary constituent elements. In addition, the size or ratio of the sizes of the components shown in the drawings is not necessarily strict.

(Embodiment 1)

[One. Configuration of power amplifier circuit]

1 is a configuration diagram of a power amplifying circuit 1 and a peripheral circuit thereof according to the first embodiment. In the figure, the power amplifier circuit 1 and constant current sources 14 and 24 according to the present embodiment are shown. As shown in the figure, the power amplifier circuit 1 includes a high-frequency input terminal 100, a high-frequency output terminal 200, amplifying transistors 10 and 20, a variable voltage power supply 11 and 21, and a bias voltage. Circuits 12 and 22, a current limiting circuit 23, resistance elements 151 and 251, capacitors 152, 153 and 252, and an impedance matching circuit 254 are provided.

With the above configuration, the power amplification circuit 1 amplifies the high-frequency signal input from the high-frequency input terminal 100 by the amplifying transistors 10 and 20, and outputs the amplified high-frequency signal from the high-frequency output terminal 200. .

The amplifying transistor 10 has a base terminal, a collector terminal, and an emitter terminal, power amplifying a high-frequency signal input from the base terminal, and outputting the power-amplified high-frequency signal from the collector terminal.

The amplifying transistor 20 has a base terminal (first control terminal), a collector terminal (first terminal), and an emitter terminal (second terminal), and power amplifies a high-frequency signal input from the base terminal (first control terminal). And a second amplification transistor that outputs the power-amplified high-frequency signal from a collector terminal (first terminal).

The amplifying transistors 10 and 20 are, for example, bipolar transistors having a base terminal, an emitter terminal, and a collector terminal. Further, the amplification transistors 10 and 20 are not limited to bipolar transistors, and may be, for example, MOS field-effect transistors (Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET)).

The variable voltage power supply 11 supplies the variable voltage Vcc1 to the collector terminal of the amplifying transistor 10. The variable voltage power supply 21 supplies the variable voltage Vcc2 to the collector terminal of the amplifying transistor 20. Further, the variable voltages Vcc1 and Vcc2 are synchronously variable. That is, when the variable voltage Vcc1 increases, the variable voltage Vcc2 also increases, and when the variable voltage Vcc1 decreases, the variable voltage Vcc2 also decreases.

The bias circuit 12 outputs a DC bias current toward the base terminal of the amplifying transistor 10. More specifically, the bias circuit 12 includes a constant current amplifying transistor 120, diode-connected transistors 121 and 122, a capacitor 123, and a resistance element 124.

The constant current amplifying transistor 120 has a collector terminal, an emitter terminal, and a base terminal, and outputs a DC bias current from the emitter terminal toward the base terminal of the amplifying transistor 10. With this configuration, the constant current output from the constant current source 14 is input to the base terminal of the constant current amplifying transistor 120, the constant current is amplified to become a direct current bias current, and from the emitter terminal of the constant current amplifying transistor 120 It is applied to the base terminal of the amplifying transistor 10 via the resistance element 151.

The bias circuit 22 outputs an effective direct current bias current Ief toward the base terminal of the amplifying transistor 20. More specifically, the bias circuit 22 includes a constant current amplifying transistor 220, diode-connected transistors 221 and 222, a capacitor 223, and a resistance element 224.

The constant current amplifying transistor 220 has a collector terminal (third terminal), an emitter terminal (fourth terminal), and a base terminal (second control terminal), and a DC bias current (Ief) from the emitter terminal (fourth terminal) ) To the base terminal (first control terminal) of the amplifying transistor 20. With this configuration, the constant current output from the constant current source 24 is input to the base terminal of the constant current amplifying transistor 220, the constant current is amplified to become a direct current bias current Ief, and the emitter of the constant current amplifying transistor 220 It is applied to the base terminal of the amplifying transistor 20 via the resistance element 251 from the terminal terminal (the fourth terminal).

The current limiting circuit 23 is a circuit that limits the DC bias current output from the bias circuit 22. More specifically, the current limiting circuit 23 includes a current limiting transistor 230 and resistance elements 231 and 232.

The current limiting transistor 230 has a collector terminal (the fifth terminal), an emitter terminal (the sixth terminal), and a base terminal (the third control terminal), and the emitter terminal (the sixth terminal) is a constant current amplifying transistor 220 ) Is connected to the emitter terminal (the 4th terminal).

The resistance element 232 is a first resistance element having one end connected to the collector terminal (the fifth terminal) of the current limiting transistor 230 and the other end connected to the variable voltage power supply 11. Further, the other end of the resistance element 232 may be connected to a variable voltage power supply 21.

The resistance element 231 has one end connected to the base terminal (third control terminal) of the current limiting transistor 230, and the other end connected to the base terminal (second control terminal) of the constant current amplifying transistor 220. It is the second resistance element.

When the variable voltage Vcc1 (Vcc2) is smaller than the reference voltage by the above connection configuration, the current limiting circuit 23 increases the potential difference between the variable voltage Vcc1 (Vcc2) and the reference voltage, the constant current amplifying transistor ( DC current flowing from the base terminal (second control terminal) of 220) through the base terminal (third control terminal) of the current limiting transistor 230 to the collector terminal (the fifth terminal) of the current limiting transistor 230 Increase the limiting current. In addition, the reference voltage is a maximum variable voltage set when, for example, a high frequency input signal input to the power amplifier circuit 1 has a maximum power amplitude.

The capacitors 152, 153, and 252 are capacitor elements for DC blocking that remove a DC component of a high-frequency signal.

The impedance matching circuit 254 is a circuit that matches the output impedance of the amplifying transistor 10 and the input impedance of the amplifying transistor 20.

In addition, in the power amplification circuit according to the present invention, the resistance elements 151 and 251, the capacitors 152, 153 and 252, and the impedance matching circuit 254 are appropriately deleted or different according to the required specifications of the power amplifying circuit. It is replaced by a circuit element, and is not an essential component.

The power amplification circuit 1 according to the present embodiment includes an amplifying transistor 20, a variable voltage power supply 11 supplying a variable voltage Vcc2 (and Vcc1) to a collector terminal of the amplifying transistor 20, and amplifying A bias circuit 22 having a constant current amplifying transistor 220 for outputting a DC bias current to a base terminal of the transistor 20 and a current limiting circuit 23 for limiting the DC bias current are provided. The current limiting circuit 23 includes a current limiting transistor 230, a collector terminal of the current limiting transistor 230 and a resistance element 232 connected to the variable voltage power supply 11, and a base terminal of the current limiting transistor 230. And a resistance element 231 connected to the base terminal of the constant current amplifying transistor 220.

According to this, as the potential difference between the reference voltage and the variable voltage Vcc2 (and Vcc1) increases, the direct current limiting current flowing from the base terminal of the constant current amplifying transistor 220 to the collector terminal of the current limiting transistor 230 can be increased. .

That is, since the base current (base-emitter current) of the amplifying transistor 20 is limited with the reduction of the variable voltage (Vcc2 (and Vcc1)), the collector current (collector-emitter current) of the amplifying transistor 20 is reduced. It can be reduced. That is, since the optimum DC bias current (Ief) according to the size of the variable voltage (Vcc2 (and Vcc1)) can be flowed, it is necessary to improve the power-added efficiency (PAE) of the power amplifying circuit 1 It becomes possible. In addition, the circuit operation of the current limiting circuit 23 will be described later with reference to FIG. 6.

In addition, with the reduction of the variable voltage Vcc2 (and Vcc1) driving the amplifying transistor 20, the direct current bias current Ief for optimizing the operating point of the amplifying transistor 20 is reduced by one transistor (current limiting transistor (current limiting transistor)). 230)) and a current limiting circuit 23 composed of two resistance elements 231 and 232. Thereby, the current limiting circuit 23 can be realized by a simplified circuit configuration, and it is possible to contribute to the miniaturization of the power amplifying circuit 1.

Further, in the present embodiment, a two-stage power amplifier circuit 1 in which the amplifying transistors 10 and 20 are cascaded is shown, but the number of stages of the amplifying transistors may be three or more. Thereby, the gain (gain) of the power amplifying circuit can be adjusted according to the number of stages of the amplifying transistor, and it becomes possible to increase the gain (gain) as the number of stages increases.

Further, in the case of a power amplifying circuit having a configuration in which a plurality of amplifying transistors are cascaded, like the power amplifying circuit 1 according to the present embodiment, the amplifying transistor to which the current limiting circuit 23 is connected is a plurality of amplifying transistors. It is preferable that it is arranged at the last stage closest to the output terminal of the power amplifier circuit.

That is, the power amplifying circuit 1 according to the present embodiment has a plurality of cascade-connected amplifying transistors including the amplifying transistor 20 as the first amplifying transistor. In addition, among the plurality of amplifying transistors, the amplifying transistor 20 disposed at the last end closest to the output terminal of the power amplifying circuit 1 is the first amplifying transistor. A variable voltage power supply 21, a bias circuit 22, and a current limiting circuit 23 are disposed at the last stage.

As a result, since the optimum DC bias current Ief according to the magnitude of the variable voltage can be passed at the last stage where the power level of the high-frequency signal is highest, it becomes possible to effectively improve the power addition efficiency of the power amplifier circuit.

[2. Configuration of power amplifier circuit according to Modification Example 1]

FIG. 2 is a configuration diagram of a power amplifier circuit 1A and a peripheral circuit thereof according to Modification Example 1 of Embodiment 1. FIG. In the figure, a power amplification circuit 1A, constant current sources 14 and 24, an envelope detection circuit 3, an RF signal processing circuit (RFIC) 4, and baseband signal processing according to the present modification. The circuit (BBIC) 5 is shown.

The power amplifier circuit 1A differs from the power amplifier circuit 1 according to the first embodiment only in that a power supply control circuit 2 is further added. Hereinafter, the same points as those of the power amplifying circuit 1 according to the first embodiment of the power amplifying circuit 1A according to the present modified example will be omitted, and different points will be mainly described.

The power supply control circuit 2 controls the variable voltages Vcc1 and Vcc2 according to ^{the power amplitude (√(i 2} +Q ² )) of the high frequency input signal (or high frequency output signal) output from the envelope detection circuit 3 . The power supply control circuit 2 is, for example, a DC-DC converter. Further, when the power supply control circuit 2 is constituted by a DC-DC converter, the variable voltage power supplies 11 and 21 may also be included in the DC-DC converter.

In addition, when i and Q are high-frequency signals (voltage) as Acos(2πfct+φ) (A: voltage amplitude, fc: frequency, φ: phase), i(t)=A(t)cosφ(t) , And Q(t)=A(t)sinφ(t).

The envelope detection circuit 3 extracts the i/Q data of the BBIC 5, detects the high frequency power amplitude (√(i ² +Q ² )) of the high frequency input signal (or high frequency output signal), and the power control circuit Print in (2).

The BBIC 5 is a circuit that processes a signal using an intermediate frequency band of a lower frequency than a high frequency input signal input to the power amplification circuit 1A. In addition, the BBIC 5 carries i/Q data of the high-frequency input signal.

The RFIC 4 generates a high-frequency input signal input to the power amplifying circuit 1A based on i/Q data output from the BBIC 5 or the like.

According to the above configuration, the power supply control circuit 2 receives information of the high frequency power amplitude (√(i ² +Q ² )) of the high frequency input signal (or high frequency output signal), and applies the variable voltage Vcc2 (and Vcc1). Control. That is, the power amplification circuit 1A varies the variable voltage Vcc2 (and Vcc1) based on an envelope tracking (ET) method that tracks the power amplitude of a high-frequency input signal. Therefore, according to the power amplification circuit 1A according to the present modification, the power addition efficiency of the power amplification circuit 1A based on the ET method is reduced, similar to the power amplification circuit 1 according to the first embodiment, a simplified current limit. It becomes possible to improve by the configuration of the circuit 23.

Here, the relationship between the high-frequency output power of the power amplifier circuit 1A and the variable voltage Vcc2 (and Vcc1) in the ET system is shown.

3 is a schematic circuit diagram showing the connection of an amplifying transistor and its peripheral circuit. In the figure, an emitter grounding type bipolar transistor, a power supply voltage Vcc, a load impedance (50Ω), and an inductor for impedance matching are shown.

In the circuit shown in Fig. 3, when a high frequency input signal is input from the base terminal and a high frequency output signal is output from the collector terminal, the output power (Pout) and the power supply voltage (Vcc) of the high frequency output signal are the following equations: It satisfies the relational expression of 1.

In Equation 1, Vsat represents the voltage between the collector and the emitter, and R _L represents the load impedance, for example, 50 (Ω).

In the case of employing the ET method as in this modification, since the amplifying transistor operates in the saturation region, Vsat becomes approximately zero. Therefore, when Vsat=0 is substituted in Equation 1, the output power Pout(W) is expressed as in Equation 2, and the voltage component Pout(V) of the output power is expressed as in Equation 3.

Here, k1 and k2 are integers.

As shown in Equation 3, in the case of the ET method, the voltage component Pout(V) of the output power of the high-frequency output signal is expressed as a linear function of the power supply voltage Vcc. Accordingly, in the power amplifying circuit 1A according to the present modification, when operating the current limiting circuit 23, the power level of the high-frequency signal is not monitored, but the power level is linear (a linear function). Monitor the relevant supply voltage (Vcc).

More specifically, the current limiting circuit 23 monitors the variable voltage (Vcc2 (and Vcc1)) by the ET method, and a DC bias sufficient at a high variable voltage (Vcc2 (and Vcc1)) (≒ high high frequency signal power). A current is made to flow through the bias circuit 22, and a DC bias current is not unnecessarily flowed through the bias circuit 22 at a low variable voltage (Vcc2 (and Vcc1)) (≒ low high frequency signal power). Thereby, since the collector current (driving current) Icc2 suitable for the ET system can be passed, it becomes possible to effectively improve the power addition efficiency of the power amplifier circuit 1A based on the ET system.

[3. Amplification characteristics of power amplifier circuit]

4A is a graph showing a relationship between a variable voltage Vcc and a collector current Ic of a power amplifying circuit according to a comparative example. 4B is a graph showing the relationship between the variable voltage Vcc2 and the collector current Icc2 of the power amplifier circuit 1 according to the first embodiment. In addition, in the power amplification circuit according to the comparative example, there is no current limiting circuit 23 in the power amplification circuit 1 according to the first embodiment, and the bias circuit 22 is directly connected to the base terminal of the amplifying transistor 20. It has a connected circuit configuration.

4A and 4B show the static characteristics (direct current characteristics) of the variable voltage-collector current when the base-emitter voltage V _{BE of the amplifying transistor 20 is changed.}

In the power amplification circuit according to the comparative example, as shown in Fig. 4A, the collector current Ic is substantially constant with respect to a change in the variable voltage Vcc (0.5V to 4.0V). In the power amplification circuit according to the comparative example, even if the variable voltage (Vcc) is reduced in response to the power amplitude of the high-frequency signal by, for example, the ET method, the bias circuit 22 directly reaches the base terminal of the amplifying transistor 20. The supplied DC bias current (base-emitter current) is substantially constant by the constant current output from the constant current source 24. Accordingly, the collector current Ic flowing depending on the DC bias current does not correspond to a decrease in the variable voltage Vcc, but becomes substantially constant.

In contrast, in the power amplifying circuit 1 according to the present embodiment, as shown in Fig. 4B, the collector current Icc2 decreases in response to a decrease in the variable voltage Vcc2 (0.5V to 4.0V). This means that in the power amplification circuit 1 according to the present embodiment, the current limiting circuit 23 limits (reduces) the direct current bias current Ief output from the bias circuit 22 in response to a decrease in the variable voltage Vcc2. It is due to what you are doing. That is, in the power amplification circuit 1 according to the present embodiment, when the variable voltage Vcc2 is reduced in correspondence with the power amplitude of the high-frequency signal by, for example, the ET method, the amplifying transistor 20 from the bias circuit 22 The DC bias current Ief (base-emitter current) supplied to the base terminal of is limited by the current limiting circuit 23 and thus decreases. Accordingly, the collector current Icc2 flowing depending on the DC bias current Ief also decreases corresponding to the decrease in the variable voltage Vcc2.

5A is a graph showing a relationship between high-frequency output power and power addition efficiency of a power amplifying circuit according to a comparative example. 5B is a graph showing the relationship between the high-frequency output power and the power addition efficiency of the power amplifying circuit 1 according to the first embodiment. More specifically, FIG. 5A shows the characteristics of the high frequency output power Pout-power addition efficiency when the variable voltage Vcc is changed by the ET method in the power amplification circuit according to the comparative example. In addition, FIG. 5B shows the characteristics of the high frequency output power Pout-power addition efficiency when the variable voltage Vcc2 is changed by the ET method in the power amplification circuit 1 according to the first embodiment.

As shown in FIGS. 5A and 5B, as the variable voltage Vcc2 (or Vcc) is decreased in a predetermined high-frequency output power Pout, the power addition efficiency increases. However, when comparing FIGS. 5A and 5B, for example, when the high frequency output power Pout is 20 dBm, in the power amplification circuit according to the comparative example (FIG. 5A ), the power addition efficiency is 49%. In the power amplification circuit 1 according to (Fig. 5B), the power addition efficiency is improved to 52%. In addition, when the high-frequency output power Pout is 15 dBm, the power amplification circuit 1 according to the first embodiment (Fig. 5B), whereas the power addition efficiency is 37% in the power amplification circuit according to the comparative example (Fig. 5A). In, the power-added efficiency is improved to 43%.

When the variable voltage Vcc2 (or Vcc) is decreased in correspondence with the power amplitude of the high-frequency signal by the ET method, the power addition efficiency increases as the variable voltage decreases. However, in the power amplification circuit according to the comparative example, the variable voltage Vcc decreases, but the collector current Ic is approximately constant. On the other hand, in the power amplifying circuit 1 according to the first embodiment, the collector current Icc2 decreases as well as the variable voltage Vcc2 decreases. Therefore, in the power amplification circuit 1 according to the first embodiment, the power addition efficiency defined by the product of the variable voltage Vcc2 (and Vcc1) and the collector current Icc2 can be effectively improved.

Next, the operation of the current limiting circuit 23 according to the present embodiment will be described.

6 is a graph for explaining the operation of the current limiting circuit 23 according to the first embodiment. In (a) of the figure, a graph showing the relationship between the collector-emitter voltage Vce (see Fig. 1) of the current limiting transistor 230 and the variable voltage Vcc2 is shown. In (b) of the figure, a graph showing the relationship between the DC bias current Ief (see Fig. 1) and the variable voltage Vcc2 output from the bias circuit 22 to the base terminal of the amplifying transistor 20 is shown. have. In (c) of the figure, a graph showing the relationship between the collector current Icc2 (see Fig. 1) and the variable voltage Vcc2 of the amplifying transistor 20 is shown. In (d) of the figure, a current (Isub_c) flowing from the variable voltage power supply 11 (or 21) toward the collector terminal of the current limiting transistor 230 (see Fig. 1) and a variable voltage ( A graph showing the relationship of Vcc2) is shown. In (e) of the figure, the relationship between the current Isub_b (see Fig. 1) and the variable voltage Vcc2 flowing from the bias circuit 22 toward the base terminal of the current limiting transistor 230 is shown. The graph shown is shown. In (f) of the figure, a current Isub (see Fig. 1) and a variable voltage (Vcc2) flowing from the emitter terminal of the current limiting transistor 230 toward the connection point of the current limiting circuit 23 and the bias circuit 22 A graph showing the relationship of) is shown. Here, Isub=Isub_b+Isub_c holds.

When the variable voltage (Vcc2 (and Vcc1)) decreases and Vcc2 becomes lower than 1.5V, the collector potential becomes lower than the base potential of the current limiting transistor 230, and the current from the base terminal of the current limiting transistor 230 toward the collector terminal Flows out (in Fig. 6(d), Isub_c becomes a negative current). At this time, the constant current supplied to the base terminal of the constant current amplifying transistor 220 of the bias circuit 22 is partially branched toward the resistance element 231 and Isub_b flows (Isub_b in Fig. 6E). Becomes a positive current). As a result, the direct current bias current Ief output from the emitter terminal of the constant current amplifying transistor 220 decreases corresponding to the amount in which the constant current diverges toward the resistance element 231 (Fig. 6(b)). In, Ief decreases). As the DC bias current Ief decreases, the collector current Icc2 also decreases (Fig. 6(c)). That is, the current limiting circuit 23 reduces the DC bias current Ief by accepting the constant current before being amplified by the DC bias current Ief as the variable voltage Vcc2 decreases. In addition, since the constant current branched toward the resistance element 231 is the current level before being amplified by the direct current bias current Ief, the current flowing toward the connection point of the current limiting circuit 23 and the bias circuit 22 (Isub) is also sufficiently small compared to the DC bias current Ief (Fig. 6(f)). For this reason, the current Isub does not affect the increase or decrease of the DC bias current Ief with respect to the increase or decrease of the variable voltage Vcc2.

That is, when the variable voltage Vcc2 (and Vcc1) is smaller than the reference voltage, the current limiting circuit 23 is the base of the constant current amplifying transistor 220 as the potential difference between the reference voltage and the variable voltage Vcc2 (and Vcc1) increases. The direct current limiting current (-Isub_c), which is a direct current flowing from the terminal to the collector terminal of the current limiting transistor 230 via the base terminal of the current limiting transistor 230, is increased.

By the above operation of the current limiting circuit 23, by a simplified circuit composed of one current limiting transistor 230 and two resistance elements 231 and 232, the amplifying transistor ( The collector current Icc2 of 20) can be reduced.

In addition, as described in FIGS. 6A to 6F, according to the current limiting circuit 23 according to the present embodiment, the power addition efficiency in particular at medium power (≒20dBm) and low power (<15dBm) Can be effectively improved.

Further, in the current limiting circuit 23, a resistance element may be inserted in series into the emitter terminal of the current limiting transistor 230. Thereby, it becomes possible to adjust the rate of change of the DC bias current Ief with respect to the change of the variable voltage Vcc2 (and Vcc1).

[4. Configuration of power amplifier circuit according to Modification Example 2]

7A is a configuration diagram of a power amplifier circuit 1B and a peripheral circuit thereof according to Modification Example 2 of Embodiment 1. FIG. In the figure, the power amplifier circuit 1B and the constant current sources 14 and 24 according to the present modification are shown. As shown in the figure, the power amplifier circuit 1B includes a high-frequency input terminal 100, a high-frequency output terminal 200, amplifying transistors 10 and 20, a variable voltage power supply 11 and 21, and a bias. Circuits 12 and 22 and a current limiting circuit 23A are provided. The power amplification circuit 1B further includes a resistance element, a capacitor, and an impedance matching circuit, similar to the power amplification circuit 1 according to the first embodiment. The power amplification circuit 1B shown in the figure differs from the power amplification circuit 1 according to the first embodiment in the configuration of the current limiting circuit 23A. Hereinafter, with respect to the power amplifying circuit 1B according to the present modification, a description of the same configuration as that of the power amplifying circuit 1 according to the first embodiment will be omitted, and other configurations will be mainly described.

The current limiting circuit 23A is a circuit that limits the DC bias current output from the bias circuit 22. More specifically, the current limiting circuit 23A includes a current limiting transistor 230, resistance elements 231, 232A, and 232B, and capacitors 233 and 234.

The current limiting transistor 230 has a collector terminal (the fifth terminal), an emitter terminal (the sixth terminal), and a base terminal (the third control terminal), and the emitter terminal (the sixth terminal) is a constant current amplifying transistor 220 ) Is connected to the emitter terminal (the 4th terminal).

The resistance element 231 has one end connected to the base terminal (third control terminal) of the current limiting transistor 230, and the other end connected to the base terminal (second control terminal) of the constant current amplifying transistor 220. It is the second resistance element.

The resistance element 232A is a first divided resistor having one end connected to the collector terminal (the fifth terminal) of the current limiting transistor 230 and the other end connected to one end of the resistance element 232B. The resistance element 232B is a second divided resistor whose other end is connected to the variable voltage power supply 11. Further, the other end of the resistance element 232B may be connected to a variable voltage power supply 21.

The capacitor 233 is a first capacitive element connected in parallel to the resistance element 232A. The capacitor 234 is a second capacitor connected between the base terminal (the third control terminal) and the collector terminal (the fifth terminal) of the current limiting transistor 230.

Further, a resistance element may be inserted in series between the emitter terminal of the current limiting transistor 230 and the emitter terminal of the constant current amplifying transistor 220. Thereby, it becomes possible to adjust the rate of change of the DC bias current Ief with respect to the change of the variable voltage Vcc2 (and Vcc1).

[5. Configuration of power amplification circuit according to Modification Example 3]

7B is a configuration diagram of a power amplifier circuit 1C and a peripheral circuit thereof according to Modification Example 3 of the first embodiment. In the figure, the power amplifier circuit 1C and the constant current sources 14 and 24 according to the present modification are shown. As shown in the figure, the power amplifier circuit 1C includes a high-frequency input terminal 100, a high-frequency output terminal 200, amplifying transistors 10 and 20, a variable voltage power supply 11 and 21, and a bias. Circuits 12 and 22 and a current limiting circuit 23B are provided. Like the power amplification circuit 1 according to the first embodiment, the power amplification circuit 1C further includes a resistance element, a capacitor, and an impedance matching circuit. The power amplification circuit 1C shown in the figure differs from the power amplification circuit 1 according to the first embodiment in the configuration of the current limiting circuit 23B. Hereinafter, with respect to the power amplifying circuit 1C according to the present modification, a description of the same configuration as the power amplifying circuit 1 according to the first embodiment will be omitted, and other configurations will be mainly described.

The current limiting circuit 23B is a circuit that limits the DC bias current output from the bias circuit 22. More specifically, the current limiting circuit 23B includes a current limiting transistor 230, resistance elements 231, 232A, and 232B, and capacitors 234 and 236.

The current limiting transistor 230 has a collector terminal (a fifth terminal), an emitter terminal (a sixth terminal), and a base terminal (a third control terminal), and an emitter terminal (a sixth terminal) is a resistance element 235 It is connected to the emitter terminal (the fourth terminal) of the constant current amplifying transistor 220 via the terminal.

The resistance element 231 has one end connected to the base terminal (third control terminal) of the current limiting transistor 230, and the other end connected to the base terminal (second control terminal) of the constant current amplifying transistor 220. It is the second resistance element.

The resistance element 232A is a first divided resistor having one end connected to the collector terminal (the fifth terminal) of the current limiting transistor 230 and the other end connected to one end of the resistance element 232B. The resistance element 232B is a second divided resistor whose other end is connected to the variable voltage power supply 11. Further, the other end of the resistance element 232B may be connected to a variable voltage power supply 21.

The capacitor 236 is a first capacitor connected between the connection point of the resistance elements 232A and 232B and the emitter terminal (the sixth terminal) of the current limiting transistor 230. The capacitor 234 is a second capacitor connected between the base terminal (the third control terminal) and the collector terminal (the fifth terminal) of the current limiting transistor 230.

Further, a resistance element may be inserted in series between the emitter terminal of the current limiting transistor 230 and the emitter terminal of the constant current amplifying transistor 220. Thereby, it becomes possible to adjust the rate of change of the DC bias current Ief with respect to the change of the variable voltage Vcc2 (and Vcc1).

[6. Distortion characteristics of the power amplifying circuit according to Modification Example 2 and Modification Example 3]

8A is a graph comparing AM (amplitude modulation)-AM (amplitude modulation) characteristics of the power amplification circuit 1 according to the first embodiment and the power amplification circuit 1B according to the second modification. 8B is a graph comparing AM (amplitude modulation)-PM (phase modulation) characteristics of the power amplification circuit 1 according to the first embodiment and the power amplification circuit 1B according to the second modification. Here, the AM-AM characteristic is a characteristic representing the ratio of the amplitude of the input signal and the amplitude of the output signal of the power amplifier circuit. In addition, the AM-PM characteristic is a characteristic representing the ratio of the amplitude of the input signal and the phase of the output signal of the power amplifying circuit. Fig. 8A shows the relationship between the high-frequency output power and the AM-AM characteristics, and Fig. 8B shows the relationship between the high-frequency output power and the AM-PM characteristics.

The power amplification circuit 1B according to the modification 2 is compared with the power amplification circuit 1 according to the first embodiment, both of the AM-AM characteristics (Gradient of Voltage Gain) and the AM-PM characteristics (Gradient of Voltage Phase). It is close to 0 in. That is, in the power amplification circuit 1B according to the second modification, the addition of the capacitors 233 and 234 in the current limiting circuit 23A improves nonlinearity and improves distortion characteristics.

In addition, the same thing as the power amplification circuit 1B according to the modification example 2 can be said for the power amplification circuit 1C according to the modification example 3, and the capacitors 234 and 236 are added to the current limiting circuit 23B. As a result, nonlinearity is improved, and it becomes possible to improve distortion characteristics.

(Embodiment 2)

In the first embodiment, in a two-stage power amplification circuit 1 in which the amplification transistors 10 and 20 are cascaded, a configuration in which the current limiting circuit 23 is connected to the amplifying transistor 20 at the rear stage (power stage). Exemplified. On the other hand, in the present embodiment, a configuration in which a current limiting circuit is connected to the amplifying transistor 10 at the front end (drive stage) is illustrated.

9 is a configuration diagram of a power amplifier circuit 1D and a peripheral circuit thereof according to the second embodiment. In the figure, the power amplifier circuit 1D and the constant current sources 14 and 24 according to the present embodiment are shown. As shown in the figure, the power amplifier circuit 1D includes a high-frequency input terminal 100, a high-frequency output terminal 200, amplifying transistors 10 and 20, variable voltage power supplies 11 and 21, and bias. Circuits 12 and 22, current limiting circuits 13 and 23, resistance elements 151 and 251, capacitors 152, 153 and 252, and impedance matching circuit 254 are provided.

With the above configuration, the power amplification circuit 1D amplifies the high-frequency signal input from the high-frequency input terminal 100 by the amplifying transistors 10 and 20, and outputs the amplified high-frequency signal from the high-frequency output terminal 200. .

The power amplifier circuit 1D according to the second embodiment differs from the power amplifier circuit 1 according to the first embodiment in that a current limiting circuit 13 is added. Hereinafter, the same configuration as the power amplification circuit 1 according to the first embodiment of the power amplification circuit 1D according to the present embodiment will be omitted, and other configurations will be mainly described.

The amplifying transistor 10 has a base terminal (first control terminal), a collector terminal (first terminal), and an emitter terminal (second terminal), and power amplifies a high-frequency signal input from the base terminal (first control terminal). And a first amplification transistor of a front end (drive end) that outputs the power-amplified high-frequency signal from a collector terminal (first terminal).

The amplifying transistor 20 has a base terminal (first control terminal), a collector terminal (first terminal), and an emitter terminal (second terminal), and power amplifies a high-frequency signal input from the base terminal (first control terminal). And a first amplification transistor at a rear stage (power stage) for outputting the power-amplified high-frequency signal from a collector terminal (first terminal).

The bias circuit 12 outputs an effective DC bias current Ief1 toward the base terminal of the amplifying transistor 10. More specifically, the bias circuit 12 includes a constant current amplifying transistor 120, diode-connected transistors 121 and 122, a capacitor 123, and a resistance element 124.

The constant current amplifying transistor 120 has a collector terminal (third terminal), an emitter terminal (fourth terminal), and a base terminal (second control terminal), and a direct current bias current (Ief1) from the emitter terminal (the fourth terminal). ) To the base terminal (first control terminal) of the amplifying transistor 10. With this configuration, the constant current output from the constant current source 14 is input to the base terminal of the constant current amplifying transistor 120, the constant current is amplified to become a direct current bias current Ief1, and the emitter of the constant current amplifying transistor 120 It is applied to the base terminal of the amplifying transistor 10 via the resistance element 151 from the terminal terminal (the fourth terminal).

The bias circuit 22 outputs an effective DC bias current Ief2 toward the base terminal of the amplifying transistor 20. More specifically, the bias circuit 22 includes a constant current amplifying transistor 220, diode-connected transistors 221 and 222, a capacitor 223, and a resistance element 224.

The constant current amplifying transistor 220 has a collector terminal (third terminal), an emitter terminal (fourth terminal), and a base terminal (second control terminal), and a direct current bias current (Ief2) from the emitter terminal (fourth terminal). ) To the base terminal (first control terminal) of the amplifying transistor 20. With this configuration, the constant current output from the constant current source 24 is input to the base terminal of the constant current amplifying transistor 220, and the constant current is amplified to become a direct current bias current Ief2, and the emitter of the constant current amplifying transistor 220 It is applied to the base terminal of the amplifying transistor 20 via the resistance element 251 from the terminal terminal (the fourth terminal).

The current limiting circuit 13 is a circuit that limits the DC bias current output from the bias circuit 12. More specifically, the current limiting circuit 13 includes a current limiting transistor 130 and resistance elements 131 and 132.

The current limiting transistor 130 has a collector terminal (the fifth terminal), an emitter terminal (the sixth terminal), and a base terminal (the third control terminal), and the emitter terminal (the sixth terminal) is a constant current amplifying transistor 120 ) Is connected to the emitter terminal (the 4th terminal).

The resistance element 132 is a first resistance element having one end connected to the collector terminal (the fifth terminal) of the current limiting transistor 130 and the other end connected to the variable voltage power supply 11. Further, the other end of the resistance element 132 may be connected to a variable voltage power supply 21.

The resistance element 131 has one end connected to the base terminal (third control terminal) of the current limiting transistor 130, and the other end connected to the base terminal (second control terminal) of the constant current amplifying transistor 120. It is the second resistance element.

The current limiting circuit 13 is the constant current amplifying transistor 120 when the variable voltage Vcc1 (Vcc2) is smaller than the reference voltage by the above-described connection configuration, as the potential difference between the variable voltage Vcc1 (Vcc2) and the reference voltage increases. ), the DC current flowing from the base terminal (the second control terminal) to the collector terminal (the fifth terminal) of the current limiting transistor 130 via the base terminal (the third control terminal) of the current limiting transistor 130 Increase the current. Note that the reference voltage is, for example, a maximum variable voltage set when the high frequency input signal input to the power amplifier circuit 1D has the maximum power amplitude.

The current limiting circuit 23 is a circuit that limits the DC bias current output from the bias circuit 22. More specifically, the current limiting circuit 23 includes a current limiting transistor 230 and resistance elements 231 and 232.

The current limiting transistor 230 has a collector terminal (the fifth terminal), an emitter terminal (the sixth terminal), and a base terminal (the third control terminal), and the emitter terminal (the sixth terminal) is a constant current amplifying transistor 220 ) Is connected to the emitter terminal (the 4th terminal).

The resistance element 232 is a first resistance element having one end connected to the collector terminal (the fifth terminal) of the current limiting transistor 230 and the other end connected to the variable voltage power supply 11. Further, the other end of the resistance element 232 may be connected to a variable voltage power supply 21.

The resistance element 231 has one end connected to the base terminal (third control terminal) of the current limiting transistor 230, and the other end connected to the base terminal (second control terminal) of the constant current amplifying transistor 220. It is the second resistance element.

When the variable voltage Vcc1 (Vcc2) is smaller than the reference voltage by the above connection configuration, the current limiting circuit 23 is the constant current amplifying transistor 220 as the potential difference between the variable voltage Vcc1 (Vcc2) and the reference voltage increases. DC current limiting current, which is a direct current flowing from the base terminal of the current limiting transistor 230 to the collector terminal (the fifth terminal) of the current limiting transistor 230 via the base terminal (third control terminal) of the current limiting transistor 230 Make it bigger.

That is, the power amplifying circuit 1D according to the present embodiment has a plurality of cascade-connected amplifying transistors including the amplifying transistors 10 and 20 as the first amplifying transistors. In addition, among the plurality of amplifying transistors, the amplifying transistor 20 disposed at the last end closest to the output terminal of the power amplifying circuit 1D is the first amplifying transistor. A variable voltage power supply 21, a bias circuit 22, and a current limiting circuit 23 are arranged at the last stage. In addition, of the plurality of amplifying transistors, the amplifying transistor 10 disposed at least one of the front ends of the rearmost end closest to the output terminal of the power amplifying circuit 1D is the first amplifying transistor. A variable voltage power supply 11, a bias circuit 12, and a current limiting circuit 13 are arranged in the front end.

With this configuration, the base current (base-emitter current) of the amplifying transistors 10 and 20 is limited together with the reduction of the variable voltage Vcc2 (and Vcc1), so that the collector current of the amplifying transistors 10 and 20 ( Collector-emitter current) can be reduced. That is, since the optimal DC bias currents Ief1 and Ief2 according to the magnitude of the variable voltage Vcc2 (and Vcc1) can be passed, it is possible to improve the power addition efficiency PAE of the power amplifier circuit 1D. Note that the circuit operation of the current limiting circuits 13 and 23 is the same as the circuit operation of the current limiting circuit 23 in the first embodiment (Fig. 6), and thus a description thereof will be omitted in this embodiment.

In addition, with a decrease in the variable voltage Vcc2 (and Vcc1) driving the amplifying transistors 10 and 20, DC bias currents Ief1 and Ief2 for optimizing the operating points of the amplifying transistors 10 and 20, respectively, It is limited by a current limiting circuit 13 or 23 composed of one transistor (current limiting transistor 130 or 230) and two resistance elements 231 and 232 (or resistance elements 131 and 132). Thereby, the current limiting circuits 13 and 23 can be realized by a simplified circuit configuration, and can contribute to the miniaturization of the power amplifying circuit 1D.

10 is a graph showing the relationship between the transmission power of the mobile terminal and its frequency. The figure shows the distribution of transmission power in WCDMA (registered trademark) (Wideband Code Division Multiple Access), and specifically, shows the frequency of use for each transmission power in WCDMA (registered trademark). From the figure, it can be seen that the frequency at which the transmission power is 0 dBm or less occupies 50% or more. From this, it can be seen that reducing the current consumption of the power amplifier circuit when using low transmission power of 0 dBm or less greatly contributes to lower power consumption of the portable terminal and long-term operation of the battery.

11A is a schematic waveform diagram illustrating an APT (average power tracking) mode. In addition, FIG. 11B is a schematic waveform diagram explaining an ET (envelope tracking) mode. As described in Embodiment 1, the ET mode is a mode in which the power amplitude (envelope) of a high-frequency signal is tracked and the voltage supply level to the power amplifying circuit is varied according to the envelope. In contrast, the APT mode is a mode in which the average power amplitude of the high-frequency signal calculated every predetermined period is tracked, and the voltage supply level to the power amplifying circuit is varied according to the average power amplitude.

In the case of the ET mode, like the power amplification circuit 1 according to the first embodiment, the power addition efficiency PAE can be improved by disposing the current limiting circuit 23 at the rear stage (power stage). On the other hand, in the case of the APT mode, as in the power amplifier circuit 1D according to the present embodiment, by disposing the current limiting circuit 13 in the front end (drive end), for example, high frequency output power (RF output power ( At a low output level such as Pout)) of 0 dBm or less, it becomes possible to reduce the collector current Icc1 according to the variable voltage, similar to the characteristic shown in Fig. 4B. For this reason, it is possible to realize a low collector current Icc1 corresponding to a low output power, and to effectively improve the power addition efficiency PAE.

12A is a high-frequency output power (RF output power (Pout)) of a power amplifying circuit according to a comparative example, a gain (Gain), an APT variable voltage (APT_Vcc), and a noise level in E-UTRA ( E-UTRA) is a graph showing the relationship. In addition, FIG. 12B shows the high-frequency output power (RF output power (Pout)) of the power amplifying circuit according to the second embodiment, the gain (Gain), the APT variable voltage (APT_Vcc), and the E-UTRA. It is a graph showing the relationship between the noise level (E-UTRA).

In addition, the power amplification circuit according to the comparative example does not have the current limiting circuits 13 and 23 in the power amplification circuit 1D according to the second embodiment, and the bias circuit 12 is connected to the base terminal of the amplifying transistor 10. It is directly connected, and has a circuit configuration in which the bias circuit 22 is directly connected to the base terminal of the amplifying transistor 20.

In both the power amplification circuit according to the comparative example and the power amplification circuit 1D according to the second embodiment, the variable voltage Vcc1 (Vcc2) is adjusted according to the magnitude of the high frequency output power by adopting the APT mode. (APT_Vcc(V) in Fig. 12). However, in the region where the high frequency output power is low, the gain of the power amplifying circuit 1D according to the second embodiment is lowered. According to the power amplification circuit 1D according to the second embodiment, the base current (base-emitter current) of the amplifying transistors 10 and 20 increases or decreases in response to the increase or decrease of the variable voltage Vcc1 (Vcc2). Inhibition becomes possible.

13A is a high-frequency output power (RF output power (Pout)), a gain, and a collector current (Icc) of the power amplifying circuit according to a comparative example (sum of the collector currents (Icc1 and Icc2)). It is a graph showing the relationship between, and the noise level (E-UTRA) in E-UTRA. 13B shows the high-frequency output power (RF output power Pout) of the power amplifying circuit according to the second embodiment, the gain, and the collector current Icc (collector currents Icc1 and Icc2). Sum value), and a graph showing the relationship between the noise level (E-UTRA) in E-UTRA. In the region where the high frequency output power is low, the collector current Icc is lower in the power amplifier circuit 1D according to the second embodiment. According to the power amplification circuit 1D according to the second embodiment, the collector by varying the base currents (base-emitter current) of the amplifying transistors 10 and 20 to a minimum in response to a decrease in the variable voltage Vcc1 (Vcc2). It becomes possible to reduce the current.

According to the power amplification circuit 1D according to the present embodiment, since the current limiting circuit 13 is connected to the amplifying transistor 10 in the front end (drive stage), the power added efficiency (PAE) in the case of the APT mode is ) Can be effectively improved. In addition, since the current limiting circuit 23 is connected to the amplifying transistor 20 at the rear stage (power stage), the optimum DC bias current ( Since Ief) can be passed, it becomes possible to effectively improve the power addition efficiency (PAE) in the case of the ET mode.

14 is a configuration diagram of a power amplifier circuit 1E and a peripheral circuit thereof according to a modified example of the second embodiment. In the figure, the power amplifier circuit 1E and the constant current sources 14 and 24 according to the present modification are shown. As shown in the figure, the power amplifier circuit 1E includes a high-frequency input terminal 100, a high-frequency output terminal 200, amplifying transistors 10 and 20, variable voltage power supplies 11 and 21, and bias. Circuits 12 and 22, a current limiting circuit 13, resistance elements 151 and 251, capacitors 152, 153 and 252, and an impedance matching circuit 254 are provided.

With the above configuration, the power amplification circuit 1E amplifies the high-frequency signal input from the high-frequency input terminal 100 by the amplifying transistors 10 and 20, and outputs the amplified high-frequency signal from the high-frequency output terminal 200. .

The power amplification circuit 1E according to the present modification differs from the power amplification circuit 1D according to the second embodiment in that the current limiting circuit 23 is not added. Hereinafter, the same configuration as the power amplification circuit 1D according to the second embodiment of the power amplification circuit 1E according to the present modification will be omitted, and other configurations will be mainly described.

The amplifying transistor 20 has a base terminal, a collector terminal, and an emitter terminal, power amplifying a high-frequency signal input from the base terminal, and outputting the power-amplified high-frequency signal from a collector terminal.

The bias circuit 22 outputs a DC bias current toward the base terminal of the amplifying transistor 20. More specifically, the bias circuit 22 includes a constant current amplifying transistor 220, diode-connected transistors 221 and 222, a capacitor 223, and a resistance element 224.

The constant current amplifying transistor 220 has a collector terminal, an emitter terminal, and a base terminal, and outputs a DC bias current from the emitter terminal toward the base terminal of the amplifying transistor 20. With this configuration, the constant current output from the constant current source 24 is input to the base terminal of the constant current amplifying transistor 220, the constant current is amplified to become a direct current bias current, and from the emitter terminal of the constant current amplifying transistor 220 It is applied to the base terminal of the amplifying transistor 20 via the resistance element 251.

That is, the power amplifying circuit 1E according to the present modification has a plurality of cascade-connected amplifying transistors including the amplifying transistor 10 as the first amplifying transistor. In addition, among the plurality of amplifying transistors, the amplifying transistor 10 disposed at least one of the front ends of the closest end to the output terminal of the power amplifying circuit 1E is the first amplifying transistor. A variable voltage power supply 11, a bias circuit 12, and a current limiting circuit 13 are arranged in the front end.

According to the power amplifying circuit 1E according to the present modification, the current limiting circuit 13 is connected to the amplifying transistor 10 at the front end (drive stage), so that the power added efficiency (PAE) in the case of the APT mode is ) Can be effectively improved.

(Other embodiments, etc.)

As described above, the power amplifier circuit according to the embodiment of the present invention has been described with reference to the embodiment and its modifications, but the power amplifier circuit of the present invention is not limited to the above embodiment and its modifications. Other embodiments realized by combining arbitrary constituent elements in the above embodiments and their modified examples, and various kinds of ideas that those skilled in the art may think of within the scope of not departing from the gist of the present invention with respect to the above embodiments and modifications thereof. Variations obtained by performing modifications and various devices incorporating the power amplifying circuit according to the present invention are also included in the present invention.

For example, the power amplification circuit 1 according to the embodiment and the power amplification circuits 1A to 1C according to the modified examples are not only applied to the ET method as described above, but also the average of high-frequency signals calculated every predetermined period. It is possible to apply it to the APT (Average Power Tracking) method of tracking the power amplitude.

Further, in the power amplifying circuit according to the above-described embodiment and its modified examples, separate high-frequency circuit elements and wirings may be inserted between the paths for connecting the respective circuit elements and signal paths disclosed in the drawings.

The present invention can be widely used in communication devices as a power amplifying circuit for amplifying a high frequency signal.

Claims (9)

As a power amplification circuit that power amplifies a high frequency signal,
A first amplification transistor having a first terminal, a second terminal, and a first control terminal, power amplifying a high frequency signal input from the first control terminal, and outputting the power amplified high frequency signal from the first terminal; ,
A variable voltage power supply for supplying a variable voltage to the first terminal,
A bias circuit for outputting a DC bias current,
And a current limiting circuit for limiting the DC bias current,
The bias circuit,
A constant current amplifying transistor having a third terminal, a fourth terminal, and a second control terminal, and outputting the DC bias current from the fourth terminal toward the first control terminal,
The current limiting circuit,
A current limiting transistor having a fifth terminal, a sixth terminal, and a third control terminal, wherein the sixth terminal is connected to the fourth terminal,
A first resistance element having one end connected to the fifth terminal and the other end connected to the variable voltage power supply,
A power amplification circuit having a second resistance element having one end connected to the third control terminal and the other end connected to the second control terminal. The method of claim 1,
The current limiting circuit limits direct current flowing from the second control terminal to the fifth terminal via the third control terminal as the potential difference between the reference voltage and the variable voltage increases when the variable voltage becomes smaller than the reference voltage. A power amplification circuit that increases the current. The method according to claim 1 or 2,
The first resistance element is composed of a first divided resistor and a second divided resistor connected in series,
The current limiting circuit,
A first capacitor device connected in parallel to the first division resistor,
A power amplifier circuit further comprising a second capacitor connected between the third control terminal and the fifth terminal. The method according to claim 1 or 2,
The first resistance element is composed of a first divided resistor and a second divided resistor connected in series,
The current limiting circuit,
A first capacitor connected between the connection point of the first division resistor and the second division resistor and the sixth terminal,
A power amplifier circuit further comprising a second capacitor connected between the third control terminal and the fifth terminal. The method according to claim 1 or 2,
The power amplification circuit having a plurality of cascade-connected amplifying transistors including the first amplifying transistor. The method of claim 5,
Among the plurality of amplifying transistors, the amplifying transistor disposed at the last end closest to the output terminal of the power amplifying circuit is the first amplifying transistor,
A power amplifying circuit in which the variable voltage power supply, the bias circuit, and the current limiting circuit are disposed at the rear end. The method of claim 5,
Among the plurality of amplifying transistors, an amplifying transistor disposed in at least one of a front end of a terminal closest to an output terminal of the power amplifier circuit is the first amplifying transistor,
A power amplifying circuit in which the variable voltage power supply, the bias circuit, and the current limiting circuit are disposed at at least one end of the front end. The method according to claim 1 or 2,
A power amplification circuit further comprising a power control circuit for controlling the variable voltage according to a high frequency power amplitude of a high frequency input signal input to the power amplification circuit. The method of claim 8,
A power amplification circuit for controlling the variable voltage so that the variable voltage becomes a linear function of the high frequency power amplitude.

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